Nintendo Ultra64 Manual

1
Version 1.1
Nintendo Ultra64 RSP Programmer’s Guide
Silicon Graphics Computer Systems, Inc.
2011 N. Shoreline Blvd.
Mountain View, CA 94043-1389
©1996 Silicon Graphics Computer Systems, Inc. All Rights Reserved.

2

3
Table of Contents
1. Introduction..................................................................................................................... 15
Document Description ................................................................................................. 16
What It Is.................................................................................................................. 16
What It Is Not .......................................................................................................... 16
Information Presentation....................................................................................... 17
RSP Software Development Tools.............................................................................. 19
rspasm....................................................................................................................... 19
cpp............................................................................................................................. 20
m4.............................................................................................................................. 21
buildtask................................................................................................................... 21
rsp2elf ....................................................................................................................... 21
rsp, rspg.................................................................................................................... 21
Gameshop Debugger (gvd)................................................................................... 22
2. RSP Architecture............................................................................................................. 23
Overview........................................................................................................................ 24
Slave to the CPU...................................................................................................... 24
Part of the RCP........................................................................................................ 24
R4000 Core ............................................................................................................... 25
Clock Speed.............................................................................................................. 26
Vector Processor...................................................................................................... 26
Major R4000 Differences .............................................................................................. 27
Pipeline Depth......................................................................................................... 27
No Interrupts, Exceptions, or Traps..................................................................... 27
Coprocessors............................................................................................................ 27
Missing Instructions ............................................................................................... 27

4
Modified Instructions............................................................................................. 28
IMEM.............................................................................................................................. 29
Addressing............................................................................................................... 29
Explicitly Managed................................................................................................. 29
DMEM ............................................................................................................................ 30
Addressing............................................................................................................... 30
Explicitly Managed Resource................................................................................ 30
External Memory Map ................................................................................................. 31
Scalar Unit Registers..................................................................................................... 32
SU Register Format................................................................................................. 32
Register 0.................................................................................................................. 32
Register 31................................................................................................................ 32
SU Control Registers............................................................................................... 33
Vector Unit Registers.................................................................................................... 34
VU Register Format................................................................................................ 34
VU Register Addressing ........................................................................................ 34
Computational Instructions........................................................................ 34
Loads, Stores, and Moves ........................................................................... 35
Accumulator ............................................................................................................ 36
VU Control Registers.............................................................................................. 36
Vector Compare Code Register (VCC) ..................................................... 36
Vector Carry Out Register (VCO).............................................................. 37
Vector Compare Extension Register (VCE).............................................. 38
SU and VU Interaction ................................................................................................. 39
Dual Issue of Instructions...................................................................................... 39
RSP Instruction Set........................................................................................................ 40
Instruction Formats................................................................................................. 40
SU Instruction Format................................................................................. 40

Revision 1.0
5
VU Instruction Format ................................................................................ 40
Distinguishing SU and VU Instructions.............................................................. 40
Illegal Instructions .................................................................................................. 40
Execution Pipeline ........................................................................................................ 41
RSP Block Diagram................................................................................................. 41
Mary Jo’s Rules........................................................................................................ 43
Register Hazards..................................................................................................... 43
SU is Bypassed......................................................................................................... 44
Coprocessor 0 ............................................................................................................... 45
Interrupts, Exceptions, and Processor Status............................................................ 46
Interrupts.................................................................................................................. 46
Exceptions................................................................................................................ 46
Processor Status....................................................................................................... 46
3. Vector Unit Instructions................................................................................................. 47
VU Loads and Stores.................................................................................................... 48
Normal...................................................................................................................... 50
Packed....................................................................................................................... 52
Transpose ................................................................................................................. 54
VU Register Moves....................................................................................................... 56
VU Computational Instructions.................................................................................. 57
Using Scalar Elements of a Vector Register ........................................................ 58
VU Multiply Instructions............................................................................................. 61
Vector Multiply Examples..................................................................................... 64
VU Add Instructions .................................................................................................... 67
Vector Add Examples............................................................................................. 68

6
VU Select Instructions.................................................................................................. 70
Vector Select Examples .......................................................................................... 73
VU Logical Instructions ............................................................................................... 74
VU Divide Instructions ................................................................................................ 75
Reciprocal Table Lookup ....................................................................................... 77
Higher Precision Results........................................................................................ 78
Vector Divide Examples......................................................................................... 78
4. RSP Coprocessor 0 .......................................................................................................... 81
Register Descriptions.................................................................................................... 82
RSP Point of View................................................................................................... 82
$c0................................................................................................................... 83
$c1................................................................................................................... 83
$c2, $c3........................................................................................................... 83
$c4................................................................................................................... 85
$c5................................................................................................................... 88
$c6................................................................................................................... 88
$c7................................................................................................................... 88
$c8................................................................................................................... 88
$c9................................................................................................................... 89
$c10................................................................................................................. 89
$c11................................................................................................................. 90
$c12................................................................................................................. 92
$c13................................................................................................................. 92
$c14................................................................................................................. 93
$c15................................................................................................................. 93
CPU Point of View.................................................................................................. 93
Other RSP Addresses................................................................................... 95
DMA ............................................................................................................................... 96
Alignment Restrictions........................................................................................... 96
Timing....................................................................................................................... 96

Revision 1.0
7
DMA Full.................................................................................................................. 96
DMA Wait................................................................................................................ 96
DMA Addressing Bits ............................................................................................ 97
CPU Semaphore...................................................................................................... 97
DMA Examples ....................................................................................................... 97
Controlling the RDP ................................................................................................... 100
How to Control the RDP Command FIFO........................................................ 100
Examples ................................................................................................................ 101
5. RSP Assembly Language............................................................................................. 105
Different From Other MIPS Assembly Languages ................................................ 106
Why?....................................................................................................................... 106
Major Differences from the R4000 Instruction Set ........................................... 106
Syntax ........................................................................................................................... 107
Tokens..................................................................................................................... 107
Identifiers ............................................................................................................... 107
Constants................................................................................................................ 107
Operators................................................................................................................ 108
Comments.............................................................................................................. 108
Program Sections................................................................................................... 109
Labels...................................................................................................................... 109
Keywords............................................................................................................... 109
Expressions ............................................................................................................ 110
Expression Operators................................................................................ 110
Precedence .................................................................................................. 111
Expression Restrictions............................................................................. 111
Registers ................................................................................................................. 112
Vector Register Element Syntax.......................................................................... 112
Program Statements.............................................................................................. 113
Assembly Directives................................................................................................... 114
.align........................................................................................................................ 114

8
.bound..................................................................................................................... 114
.byte......................................................................................................................... 115
.data......................................................................................................................... 115
.dmax ...................................................................................................................... 115
.end.......................................................................................................................... 116
.ent........................................................................................................................... 116
.half.......................................................................................................................... 116
.name....................................................................................................................... 116
.print........................................................................................................................ 117
.space....................................................................................................................... 117
.symbol ................................................................................................................... 117
.text.......................................................................................................................... 117
.unname.................................................................................................................. 118
.word....................................................................................................................... 118
BNF Specification of the RSP Assembly Language................................................ 119
6. Advanced Information................................................................................................. 125
DMEM Organization and Usage ............................................................................. 126
Jump Tables ........................................................................................................... 126
Constants................................................................................................................ 126
Labels in DMEM ................................................................................................... 127
Dynamic Data........................................................................................................ 127
Diagnostic Information ........................................................................................ 127
Performance Tips........................................................................................................ 128
Dual Execution...................................................................................................... 128
Vectorization.......................................................................................................... 128
Software Pipelining ................................................................................... 130
Loop Inversion ........................................................................................... 131
Loop Unrolling........................................................................................... 132
Program Flow of Control.......................................................................... 132
Profiling RSP Code ............................................................................................... 133

Revision 1.0
9
Microcode Overlays.................................................................................................... 135
Memory System Implications ............................................................................. 135
Entirely Up to You................................................................................................ 135
RSP Assembler Tricks........................................................................................... 136
A Sample RSP Linker ........................................................................................... 136
Overlay Example................................................................................................... 138
Overlay Makefile........................................................................................ 138
Overlay DMEM Initialization .................................................................. 139
Overlay Initialization Code...................................................................... 140
Overlay Decision Code ............................................................................. 141
Overlay DMA Code................................................................................... 141
Controlling the RSP from the CPU.......................................................................... 142
Starting RSP Tasks................................................................................................ 142
RSP Boot Microcode .................................................................................. 142
Hidden OS Functions........................................................................................... 143
__osSpDeviceBusy..................................................................................... 143
__osSpRawStartDma()............................................................................... 143
__osSpRawReadIo()................................................................................... 143
__osSpRawWriteIo().................................................................................. 144
__osSpGetStatus() ...................................................................................... 144
__osSpSetStatus() ....................................................................................... 144
__osSpSetPc().............................................................................................. 144
Microcode Debugging Tips....................................................................................... 145
RSP Yielding ................................................................................................................ 147
Requesting a Yield ..................................................................................... 148
Checking for Yield ..................................................................................... 148
Yielding ....................................................................................................... 148
Saving a Yielded Process .......................................................................... 149
Restarting a Yield Process......................................................................... 149
A. RSP Instruction Set Details.......................................................................................... 151
Instruction Notation Examples........................................................................... 154

10

11
List of Figures
Figure 2-1 Block Diagram of the RCP ..........................................................................................25
Figure 2-2 SU Register Format......................................................................................................32
Figure 2-3 VU Register Format.....................................................................................................34
Figure 2-4 VU Accumulator Format..............................................................................................36
Figure 2-5 VCC Register Format...................................................................................................37
Figure 2-6 VCO Register Format ..................................................................................................37
Figure 2-7 VCE Register Format...................................................................................................38
Figure 2-8 RSP Block Diagram.....................................................................................................42
Figure 2-9 Pipeline Bypassing.......................................................................................................44
Figure 3-1 VU Load and Store Instruction Format........................................................................48
Figure 3-2 Long, Quad, and Rest Loads and Stores ......................................................................51
Figure 3-3 Packed Loads and Stores..............................................................................................53
Figure 3-4 Packed Load and Store Alignment...............................................................................54
Figure 3-5 Transpose Loads and Stores.........................................................................................55
Figure 3-6 VU Coprocessor Moves...............................................................................................56
Figure 3-7 VU Computational Instruction Format ........................................................................57
Figure 3-8 Scalar Half and Scalar Quarter Vector Register Elements...........................................59
Figure 3-9 VU Multiply Opcode Encoding ...................................................................................61
Figure 3-10 Double-precision VU Multiply ....................................................................................64
Figure 3-11 VU Add Opcode Encoding ..........................................................................................67
Figure 3-12 VU Select Opcode Encoding .......................................................................................70
Figure 3-13 VU Logical Opcode Encoding.....................................................................................74
Figure 3-14 VU Divide Opcode Encoding ......................................................................................75
Figure 4-1 DMA Transfer Length Encoding .................................................................................84
Figure 4-2 DMA Read/Write Example..........................................................................................98
Figure 4-3 DMA Wait Example ....................................................................................................99
Figure 4-4 RDP Initialization Using the XBUS ..........................................................................101
Figure 4-5 OutputOpen Function Using the XBUS.....................................................................102
Figure 4-6 OutputClose Function Using the XBUS ....................................................................103
Figure 6-1 Real-time Clock Watching on the RSP......................................................................134

12
Figure 6-2 buildtask Operation....................................................................................................137

13
List of Tables
Table 3-1 VU Load/Store Instruction Summary.......................................................49
Table 3-2 VU Computational Instruction Opcode Encoding....................................57
Table 3-3 VU Computational Instruction Element Encoding...................................58
Table 3-4 VU Multiply Instruction Summary...........................................................61
Table 3-5 VU Add Type Encoding............................................................................67
Table 3-6 VU Select Type Encoding..........................................................................70
Table 3-7 VU Logical Type Encoding.......................................................................74
Table 3-8 VU Divide Type Encoding.........................................................................75
Table 3-9 VU Divide Instruction Summary...............................................................76
Table 4-1 RSP Coprocessor 0 Registers ....................................................................82
Table 4-2 RSP Status Register ...................................................................................85
Table 4-3 RSP Status Write Bits ................................................................................86
Table 4-4 RDP Status Register...................................................................................90
Table 4-5 RSP Status Write Bits (CPU VIEW) .........................................................91
Table 4-6 RSP Coprocessor 0 Registers (CPU VIEW)..............................................94
Table 4-7 Other RSP Addresses (CPU VIEW)..........................................................95
Table 5-1 Expression Operators..............................................................................110
Table 5-2 Expression Operator Precedence ............................................................111
Table A-1 RSP Instruction Operation Notations ......................................................153

14

Revision 1.0
15
Chapter 1
1. Introduction
The RSP (Reality Signal Processor) is a powerful processor which is part of
the RCP (Reality Co-Processor), the heart of the Nintendo Ultra64.
The RSP operates in parallel with the host CPU (MIPS R4300i) and dedicated
graphics hardware on the RCP. Software running on the RSP (microcode)
implements the graphics geometry pipeline (transformations, clipping,
lighting, etc.) and audio processing (wavetable synthesis, sampled sound,
etc.).
TheRSPactsas aslaveprocessor to thehostCPU, andassuch,programming
the RSP requires a conspiracy of RSP microcode, R4300 interfaces, and
mastery of the features of the RCP. This document addresses the first two of
these necessary skills; details of the RDP (Reality Display Processor)
component of the RCP can be found elsewhere.

16
Introduction
Document Description
What It Is
The goal of this document is to enable RSP microcode software
development:
•Explain architectural details of the RSP.
•Explain relevant architectural details of other parts of the RCP.
•Describe the RSP from a microcode programmer’s point-of-view.
•Describe the RSP (and interfaces) from the host CPU’s
point-of-view.
•Explain the RSP microcode assembly language.
•Explain the RSP software development environment.
What It Is Not
In order to present material at a sufficient level of detail without clutter,
allowing the programmer to “see the forest
and the trees”, so to speak, we
have adopted several specific non-goals of this document:
•Basic assembly language programming concepts are not discussed.
The reader is assumed to have a thorough technical background.
•Basic concepts of vector processing architectures are not discussed,
however some specific issues relating to the RSP are discussed
briefly. A good reference for computer architecture which
discusses RISC processors and SIMD (vector) architectures is
“Computer Organization and Design, The Hardware/Software
Interface”
1
, by Patterson and Hennessy.
•Details of the MIPS Microprocessor Instruction Set Architecture
(ISA) are not presented. The design of the RSP instruction set
1 Patterson, D., Hennessy, J.,
“Computer Organization and Design, The Hardware/Software Interface”, Morgan
Kaufmann Publishers, 1994, ISBN 1-55860-281-X.

Revision 1.0 Document Description
17
borrows much from the R4000 ISA; the reader is referred to the
“MIPS R4000 Microprocessor User’s Manual”
1for more
information.
•Application-specific information is not presented. “How to Write
Graphics Microcode for the RSP” or “How to Write Audio
Microcode for the RSP” are topics worthy of a book themselves,
and are not discussed here.
•How to use the programming tools. There are detailed man pages
for each tool used during RSP software development. Although all
of these tools are mentioned in this document (and explained
briefly), the reader is referred to documentation for individual tools
for more information.
•Certain examples and advanced topics refer to higher-level Ultra64
features or RCP operations (operating system, graphics, audio,
etc.). These things are explained in other documents; a thorough
background knowledge of the Ultra64 is assumed in this document.
Information Presentation
Mastery of the information presented in this document will occur slowly, as
the information is both voluminous and of tremendous breadth. Some
concepts, such as the hardware architecture of the RSP and the microcode
assembly language, are of course thoroughly intertwined; discussion of one
is impossible without the other.
In order to present this material clearly, we have divided it up into the
following chapters. Each chapter presents its specific topic in detail, usually
assuming information contained in other chapters as background. We have
attempted to present the information in a logical, top-down fashion, with
liberal cross-references to assist the reader.
•Chapter 1, “Introduction,” is this chapter. It describes the
document itself, and briefly illuminates the RSP development
environment.
1 Heinrich, J.,
“MIPS R4000 Microprocessor User’s Manual”, Prentice Hall Publishing, 1993, ISBN 0-13-1-5925-4.

18
Introduction
•Chapter 2, “RSP Architecture,” describes the architecture of the
RSP in great detail.
•Chapter 3, “Vector Unit Instructions,” explains the vector unit (VU)
instructions, building on the RSP architecture and leading into RSP
programming.
•Chapter 4, “RSP Coprocessor 0,” describes the RSP’s Coprocessor 0.
The RSP Coprocessor 0 controls DMA activity, RDP
synchronization, and host CPU interaction.
•Chapter 5, “RSP Assembly Language,” details the assembly
language of the RSP, including assembler directives and some
programming conventions.
•Chapter 6, “Advanced Information,” builds on information in the
previous chapters in order to address sophisticated issues
including RSP performance, microcode overlays, host CPU
interactions, and additional programming conventions.
•Appendix A, “RSP Instruction Set Details,” contains a concise
description of each RSP instruction, intended to be used as a
reference.

Revision 1.0 RSP Software Development Tools
19
RSP Software Development Tools
A brief introduction to the RSP programming environment will provide a
framework for future discussions.
The following software tools are typically used for developing RSP code.
This section only mentions the critical, RSP-specific tools; other, more
general tools (like make and other UNIX tools) are not discussed.
rspasm
The assembler used to compile RSP microcode is rspasm. It is a simple,
2-pass assembler developed specifically for the RSP.
It interprets a simple assembly language, which is very R4000-like, but is not
MIPS compatible. The source language and assembler directives are unique
to the RSP.
The language, explained in more detail in Chapter 5, “RSP Assembly
Language,” has the following major features:
•Mnemonic opcode syntax for all SU and VU instructions.
•Support for labels in the text section (for branching) and the data
section (for referencing DMEM).
•Simple expression parsing.
The language also includes a rich set of assembler directives, used to instruct
the assembler during compilation:
•Data directives, used to initialize DMEM.
•Symbol naming directives, used to assign meaningful names to
registers, labels, constants, etc.
•Diagnostic directives, used to enforce memory alignment, print
diagnostic messages, etc.
rspasm does not build standard ELF object files, which are required by the
makerom utility in order to include RSP microcode objects into a game. ELF
file creation is decoupled from the assembler and accomplished by the
rsp2elf tool.

20
Introduction
The rspasm assembler outputs several special files. The root filename for
these files can be specified with the -o flag.
•<rootname>, is the binary executable code (text section). This file
can be loaded into the RSP simulator instruction memory (IMEM)
and executed.
•<rootname>.dat, is the binary data section. This is usually
loaded into RSP data memory (DMEM).
•<rootname>.lst, is a text program listing generated by the
assembler.
•<rootname>.sym, is a “symbol file” used by the RSP simulator to
perform source level debugging.
•<rootname>.dbg, is a “symbol file” used by the rsp2elf utility
in order to build an ELF object that can be used with makerom and
the gvd debugger.
The RSP assembler has no provisions for linking separately-compiled
objects. Since IMEM only holds 1024 instructions and assembling is so fast,
the lack of a sophisticated linker is not a problem. Source code can be broken
up into separate files and #include’d to enforce modularity.
Facilities tosupportdynamic linking, suchascode overlays,areprovided by
the buildtask tool.
cpp
By default, rspasm invokes the Cpreprocessor (/usr/bin/cc -E,
actually) before assembly so that source code can use #define,
#include, #ifdef, etc.
Like other MIPS assemblers, rspasm defines _LANGUAGE_ASSEMBLY
(useful for sharing header files with Cprograms).