Intersil CDP1802BCE User manual

3-3
TM
Features
• Maximum Input Clock Maximum Frequency Options
At VDD = 5V
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . .3.2MHz
- CDP1802BC . . . . . . . . . . . . . . . . . . . . . . . . . . .5.0MHz
• Maximum Input Clock Maximum Frequency Options
At VDD = 10V
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . .6.4MHz
• Minimum Instruction Fetch-Execute Times
At VDD = 5V
- CDP1802A, AC . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0µs
- CDP1802BC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2µs
• Any Combination of Standard RAM and ROM Up to
65,536 Bytes
•8
-Bit Parallel Organization With Bidirectional Data Bus
and Multiplexed Address Bus
• 16 x 16 Matrix of Registers for Use as Multiple
Program Counters, Data Pointers, or Data Registers
•On
-Chip DMA, Interrupt, and Flag Inputs
• Programmable Single-Bit Output Port
• 91 Easy-to-Use Instructions
Description
The CDP1802 family of CMOS microprocessors are 8-bit
register oriented central processing units (CPUs) designed
for use as general purpose computing or control elements in
a wide range of stored program systems or products.
The CDP1802 types include all of the circuits required for
fetching, interpreting, and executing instructions which have
been stored in standard types of memories. Extensive
input/output (I/O) control features are also provided to facili-
tate system design.
The 1800 series architecture is designed with emphasis on
the total microcomputer system as an integral entity so that
systems having maximum flexibility and minimum cost can
be realized. The 1800 series CPU also provides a synchro-
nous interface to memories and external controllers for I/O
devices, and minimizes the cost of interface controllers. Fur-
ther, the I/O interface is capable of supporting devices oper-
ating in polled, interrupt driven, or direct memory access
modes.
The CDP1802A and CDP1802AC have a maximum input
clock frequency of 3.2MHz at VDD = 5V. The CDP1802A and
CDP1802AC are functionally identical. They differ in that the
CDP1802A has a recommended operating voltage range of
4V to 10.5V, and the CDP1802AC a recommended operat-
ing voltage range of 4V to 6.5V.
The CDP1802BC is a higher speed version of the
CDP1802AC, having a maximum input clock frequency of
5.0MHz at VDD = 5V, and a recommended operating voltage
range of 4V to 6.5V.
Ordering Information
PART NUMBER
TEMPERATURE RANGE PACKAGE PKG. NO.5V - 3.2MHz 5V - 5MHz
CDP1802ACE CDP1802BCE -40oC to +85oC PDIP E40.6
CDP1802ACEX CDP1802BCEX Burn-In E40.6
CDP1802ACQ CDP1802BCQ -40oC to +85oC PLCC N44.65
CDP1802ACD - -40oC to +85oC SBDIP D40.6
CDP1802ACDX CDP1802BCDX Burn-In D40.6
March 1997
File Number 1305.2
CDP1802A, CDP1802AC,
CDP1802BC
CMOS 8-Bit Microprocessors
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved

3-4
Pinouts
40 LEAD PDIP (PACKAGE SUFFIX E)
40 LEAD SBDIP (PACKAGE SUFFIX D)
TOP VIEW
44 LEAD PLCC
(PACKAGE TYPE Q)
TOP VIEW
FIGURE 1. TYPICAL CDP1802 SMALL MICROPROCESSOR SYSTEM
13
1
2
3
4
5
6
7
8
9
10
11
12
14
15
16
17
18
19
20
CLOCK
WAIT
CLEAR
Q
SC1
SC0
MRD
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0
VCC
N2
N1
N0
VSS
28
40
39
38
37
36
35
34
33
32
31
30
29
27
26
25
24
23
22
21
VDD
XTAL
DMA IN
DMA OUT
INTERRUPT
MWR
TPA
TPB
MA7
MA6
MA5
MA4
MA3
MA2
MA1
MA0
EF1
EF2
EF3
EF4
44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
2827
123456
262524232221201918
7
8
9
10
11
12
13
14
15
16
17
SC0
MRD
BUS 7
BUS 6
BUS 5
NC
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0
SC1 Q CLEAR WAIT CLOCK NC VDD XTAL DMA-IN DMA-OUT INTERRUPT
VCC
N2 N1 N0
VSS
NC
EF4
EF3 EF2 EF1
MA0
MWR
TPA
TPB
MA7
MA6
NC
MA5
MA4
MA3
MA2
MA1
CDP1852
INPUT PORT
DATA CS1
CS2
CDP1852
OUTPUT
PORT CLOCK
CS1
CS2 MA0-7
N0
MRD
MWR
N1
TPB DATA
TPA
CDP1802
8-BIT CPU
MRD
MA0-4
MWR
CS
CDP1824
32 BYTE RAM
MA0-7
DATA
CDP1833
1K-ROM
CEOTPA
MRD
ADDRESS BUS
CDP1802A, CDP1802AC, CDP1802BC

3-5
Block Diagram
FIGURE 2.
MUX
MA7MA5MA3MA1
MA0MA2MA4MA6
MEMORY ADDRESS LINES I/O FLAGS
ALU
B
D
DF INCR/
DECR
A
R(0).1 R(0).0
R(1).0R(1).1
R(2).1 R(2).0
R(9).0
R(A).0R(A).1
R(9).1
R(E).1
R(F).1 R(F).0
R(E).0
REGISTER
ARRAY
8-BIT BIDIRECTIONAL DATA BUS
LATCH
AND
DECODE
R
XTPIN N1
N0
N2
I/O
COMMANDS
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
TO INSTRUCTION
DECODE
CONTROL AND
TIMING LOGIC
CLOCK
LOGIC
I/O REQUESTS
CONTROL
EF1 EF3
EF2 EF4
DMA
OUT
DMA
IN INT CLEAR WAIT
CLOCK
XTAL
SCO
SCI
Q LOGIC
TPA
TPB
MWR
MRD
SYSTEM
STATE
CODES
TIMING
CDP1802A, CDP1802AC, CDP1802BC

3-6
Absolute Maximum Ratings Thermal Information
DC Supply Voltage Range, (VDD)
(All Voltages Referenced to VSS Terminal)
CDP1802A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1802AC, CDP1802BC. . . . . . . . . . . . . . . . . . . . -0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Thermal Resistance (Typical, Note 4) θJA (oC/W) θJC (oC/W)
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . 50 N/A
PLCC. . . . . . . . . . . . . . . . . . . . . . . . . . 46 N/A
SBDIP . . . . . . . . . . . . . . . . . . . . . . . . . 55 15
Device Dissipation Per Output Transistor
TA= Full Package Temperature Range. . . . . . . . . . . . . . . 100mW
Operating Temperature Range (TA)
Package Type D . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Package Type E and Q. . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering)
At distance 1/16 ± 1/32 In. (1.59 ± 0.79mm)
from case for 10s max. . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
Lead Tips Only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions TA= -40oC to +85oC. For maximum reliability, operating conditions should be selected so
that operation is always within the following ranges:
PARAMETER
TEST CONDITIONS CDP1802A CDP1802AC CDP1802BC
UNITS
(NOTE 2)
VCC
(V) VDD (V) MIN MAX MIN MAX MIN MAX
DC Operating Voltage Range - - 4 10.5 4 6.5 4 6.5 V
Input Voltage Range - - VSS VDD VSS VDD VSS VDD V
Maximum Clock Input Rise or
Fall Time 4 to 6.5 4 to 6.5 - - - 1 - 1 µs
4 to 10.5 4 to 10.5 - 1 - - - - µs
Minimum Instruction Time
(Note 3) 5 5 5-5-3.2- µs
5 10 4----- µs
10 10 2.5 - - - - - µs
Maximum DMA Transfer Rate 5 5 - 400 - 400 - 667 KBytes/s
5 10 -500----
10 10 - 800 - - - -
Maximum Clock Input Frequency,
fCL, Load Capacitance
(CL) = 50pF
5 5 DC 3.2 DC 3.2 DC 5 MHz
5 10DC4----MHz
10 10 DC 6.4 - - - - MHz
NOTES:
1. Printed circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
2. VCC must never exceed VDD.
3. Equals 2 machine cycles - one Fetch and one Execute operation for all instructions except Long Branch and Long Skip, which require 3
machine cycles - one Fetch and two Execute operations.
4. θJA is measured with component mounted on an evaluation board in free air.
CDP1802A, CDP1802AC, CDP1802BC

3-7
Static Electrical Specifications at TA= -40oC to +85oC, Except as Noted
PARAMETER SYMBOL
TEST CONDITIONS CDP1802A CDP1802AC, CDP1802BC
UNITS
VOUT
(V) VIN (V)
VCC,
VDD
(V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX
Quiescent Device Current IDD - - 5 - 0.1 50 - 1 200 µA
- - 10 - 1 200 - - - µA
Output Low Drive (Sink)
Current IOL 0.4 0, 5 5 1.1 2.2 - 1.1 2.2 - mA
(Except XTAL) 0.5 0, 10 10 2.2 4.4 - - - - mA
XTAL 0.4 5 5 170 350 - 170 350 - µA
Output High Drive (Source)
Current IOH 4.6 0, 5 5 -0.27 -0.55 - -0.27 -0.55 - mA
(Except XTAL) 9.5 0, 10 10 -0.55 -1.1 - - - - mA
XTAL 4.6 0 5 -125 -250 - -125 -250 - µA
Output Voltage - 0, 5 5 - 0 0.1 - 0 0.1 V
Low Level VOL - 0, 10 10 - 0 0.1 - - - V
Output Voltage - 0, 5 5 4.9 5 - 4.9 5 - V
High Level VOH - 0, 10 10 9.9 10 - - - - V
Input Low Voltage VIL 0.5, 4.5 - 5 - - 1.5 - - 1.5 V
0.5, 4.5 - 5, 10 - - 1 - - - V
1,9-10--3---V
Input High Voltage VIH 0.5, 4.5 - 5 3.5 - - 3.5 - - V
0.5, 4.5 - 5, 10 4 - - - - - V
1,9-107-----V
CLEAR Input Voltage VH- - 5 0.4 0.5 - 0.4 0.5 - V
Schmitt Hysteresis - - 5, 10 0.3 0.4 - - - - V
- - 10 1.5 2 - - - - V
Input Leakage Current IIN Any
Input 0, 5 5 - ±10-4 ±1-±10-4 ±1µA
0, 10 10 - ±10-4 ±1---µA
Three-State Output Leakage IOUT 0, 5 0, 5 5 - ±10-4 ±1-±10-4 ±1µA
Current 0, 10 0, 10 10 - ±10-4 ±1---µA
Operating Current
CDP1802A, AC
at f = 3.2MHz IDDI
(Note 2) --5-24-24mA
CDP1802BC
at f = 5.0MHz --5----36mA
Minimum Data Retention
Voltage VDR VDD = VDR -22.4- 22.4V
Data Retention Current IDR VDD = 2.4V - 0.05 - - 0.5 - µA
CDP1802A, CDP1802AC, CDP1802BC

3-8
Input Capacitance CIN - 5 7.5 - 5 7.5 pF
Output Capacitance COUT - 10 15 - 10 15 pF
NOTES:
1. Typical values are for TA= +25oC and nominal VDD.
2. Idle “00” at M(0000), CL= 50pF.
Dynamic Electrical Specifications TA= -40oC to +85oC, CL= 50pF, VDD ±5%, Except as Noted
PARAMETER SYMBOL
TEST
CONDITIONS CDP1802A, CDP1802AC CDP1802BC
UNITSVCC (V) VDD (V) (NOTE 1)
TYP MAX (NOTE 1) TYP MAX
PROPAGATION DELAY TIMES
Clock to TPA, TPB tPLH, tPHL 5 5 200 300 200 300 ns
5 10 150 250 - - ns
10 10 100 150 - - ns
Clock-to-Memory High-Address Byte tPLH, tPHL 5 5 600 850 475 525 ns
5 10 400 600 - - ns
10 10 300 400 - - ns
Clock-to-Memory Low-Address Byte Valid tPLH, tPHL 5 5 250 350 175 250 ns
5 10 150 250 - - ns
10 10 100 150 - - ns
Clock to MRD tPHL 5 5 200 300 175 275 ns
5 10 150 250 - - ns
10 10 100 150 - - ns
Clock to MRD tPLH 5 5 200 350 175 275 ns
5 10 150 290 - - ns
10 10 100 175 - - ns
Clock to MWR tPLH, tPHL 5 5 200 300 175 225 ns
5 10 150 250 - - ns
10 10 100 150 - - ns
Clock to (CPU DATA to BUS) Valid tPLH, tPHL 5 5 300 450 250 375 ns
5 10 250 350 - - ns
10 10 100 200 - - ns
Static Electrical Specifications at TA= -40oC to +85oC, Except as Noted (Continued)
PARAMETER SYMBOL
TEST CONDITIONS CDP1802A CDP1802AC, CDP1802BC
UNITS
VOUT
(V) VIN (V)
VCC,
VDD
(V) MIN (NOTE 1) TYP MAX MIN (NOTE 1) TYP MAX
CDP1802A, CDP1802AC, CDP1802BC

3-9
Clock to State Code tPLH, tPHL 5 5 300 450 250 400 ns
5 10 250 350 - - ns
10 10 150 250 - - ns
Clock to Q tPLH, tPHL 5 5 250 400 200 300 ns
5 10 150 250 - - ns
10 10 100 150 - - ns
Clock to N (0 - 2) tPLH, tPHL 5 5 300 550 275 350 ns
5 10 200 350 - - ns
10 10 150 250 - - ns
MINIMUM SET UP AND HOLD TIMES
Data Bus Input Set Up tSU 55-2025-20 0ns
5 10 0 50 - - ns
10 10 -10 40 - - ns
Data Bus Input Hold tH
(Note 2) 5 5 150 200 125 150 ns
5 10 100 125 - - ns
10 10 75 100 - - ns
DMA Set Up tSU 55030030ns
5 10 0 20 - - ns
10 10 0 10 - - ns
DMA Hold tH
(Note 2) 5 5 150 250 100 150 ns
5 10 100 200 - - ns
10 10 75 125 - - ns
Interrupt Set Up tSU 5 5 -75 0 -75 0 ns
510-50 0 - - ns
10 10 -25 0 - - ns
Interrupt Hold tH
(Note 2) 5 5 100 150 75 125 ns
5 10 75 100 - - ns
10 10 50 75 - - ns
WAIT Set Up tSU 5 5 10 50 20 40 ns
5 10 -10 15 - - ns
10 10 0 25 - - ns
Dynamic Electrical Specifications TA= -40oC to +85oC, CL= 50pF, VDD ±5%, Except as Noted (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS CDP1802A, CDP1802AC CDP1802BC
UNITSVCC (V) VDD (V) (NOTE 1)
TYP MAX (NOTE 1) TYP MAX
CDP1802A, CDP1802AC, CDP1802BC

3-10
EF1-4 Set Up tSU 55-3020-30 0ns
5 10 -20 30 - - ns
10 10 -10 40 - - ns
EF1-4 Hold tH
(Note 2) 5 5 150 200 100 150 ns
5 10 100 150 - - ns
10 10 75 100 - - ns
Minimum Pulse Width Times
CLEAR Pulse Width tWL
(Note 2) 5 5 150 300 100 150 ns
5 10 100 200 - - ns
10 10 75 150 - - ns
CLOCK Pulse Width tWL 5 5 125 150 90 100 ns
5 10 100 125 - - ns
10 10 60 75 - - ns
NOTES:
1. Typical values are for TA= +25oC and nominal VDD.
2. Maximum limits of minimum characteristics are the values above which all devices function.
Timing Specifications as a function of T(T = 1/fCLOCK) at TA= -40 to +85oC, Except as Noted
PARAMETERS SYMBOL
TEST CONDITIONS CDP1802A, CDP1802AC CDP1802BC
UNITSVCC (V) VDD (V) MIN (NOTE 1)
TYP MIN (NOTE 1) TYP
High-Order Memory-Address Byte
Set Up to TPA Time tSU 5 5 2T-550 2T-400 2T-325 2T-275 ns
5 10 2T-350 2T250 - - ns
10 10 2T-250 2T-200 - - ns
High-Order Memory-Address Byte
Hold After TPA Time tH5 5 t/2-25 T/2-15 T/2-25 T/2-15 ns
5 10 T/2-35 T/2-25 - - ns
10 10 T/2-10 T/2-+0 - - ns
Low-Order Memory-Address Byte
Hold After WR Time tH5 5 T-30 T+0 T-30 T+0 ns
510T-20T+0- -ns
10 10 T-10 T+0 - - ns
CPU Data to Bus Hold After WR
Time tH5 5 T-200 T-150 T-175 T-125 ns
5 10 T-150 T-100 - - ns
10 10 T-100 T-50 - - ns
Dynamic Electrical Specifications TA= -40oC to +85oC, CL= 50pF, VDD ±5%, Except as Noted (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS CDP1802A, CDP1802AC CDP1802BC
UNITSVCC (V) VDD (V) (NOTE 1)
TYP MAX (NOTE 1) TYP MAX
CDP1802A, CDP1802AC, CDP1802BC

3-11
Required Memory Access Time Ad-
dress to Data tACC 5 5 5T-375 5T-250 5T-225 5T-175 ns
5 10 5T-250 5T-150 - - ns
10 10 5T-190 5T-100 - - ns
MRD to TPA tSU 5 5 T/2-25 T/2-18 T/2-20 T/2-15 ns
5 10 T/2-20 T/2-15 - - ns
10 10 T/2-15 T/2-10 - - ns
NOTE:
1. Typical values are for TA= +25oC and nominal VDD.
Timing Specifications as a function of T(T = 1/fCLOCK) at TA= -40 to +85oC, Except as Noted
PARAMETERS SYMBOL
TEST CONDITIONS CDP1802A, CDP1802AC CDP1802BC
UNITSVCC (V) VDD (V) MIN (NOTE 1)
TYP MIN (NOTE 1) TYP
Timing Waveforms
FIGURE 3. BASIC DC TIMING WAVEFORM, ONE INSTRUCTION CYCLE
FETCH (READ) EXECUTE (WRITE)
00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00 01 10 11 20 21 30 31 40 41 50 51 60 61 70 71 00
HI BYTE LOW BYTEHI BYTE LOW BYTE
CLOCK
ADDRESS
TPA
TPB
MRD
MWR
DATA VALID INPUT DATA VALID OUTPUT DATA
CDP1802A, CDP1802AC, CDP1802BC

3-12
NOTES:
1. This timing diagram is used to show signal relationships only and does not represent any specific machine cycle.
2. All measurements are referenced to 50% point of the waveforms.
3. Shaded areas indicate “Don’t Care” or undefined state. Multiple transitions may occur during this period.
FIGURE 4. TIMING WAVEFORM
Timing Waveforms (Continued)
CLOCK
TPA
TPB
MEMORY
MRD
MWR
(I/O EXECUTION
Q
DATA FROM
DMA
INTERRUPT
EF 1-4
WAIT
CLEAR
REQUEST
REQUEST
BUS TO CPU
N0, N1, N2
STATE
DATA FROM
CPU TO BUS
(MEMORY
WRITE CYCLE)
(MEMORY
ADDRESS
READ CYCLE)
CODES
CYCLE)
tW
00 10 20 30 40 50 60 70 0001 11 21 31 41 51 61 71 01
012345670
tPLH tPHL
tPLH tPHL
tPLH, tPHL
tSU
DMA SAMPLED (S1, S2, S3)
tH
ADDRESS BYTE
HIGH ORDER
tPHL tPLH tSU
tPLH, tPHL tPLH, tPHL
tPLH
tH
tPLH
tH
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
ADDRESS BYTE
LOW ORDER
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPLH
DATA
LATCHED IN CPU
tSU tH
tSU tH
tSU tH
INTERRUPT
SAMPLED (S1, S2)
FLAG LINES
SAMPLED (IN S1)
ANY NEGATIVE
TRANSITION
tSU
tW
tSU tH
CDP1802A, CDP1802AC, CDP1802BC