Nintendo Game boy advance Owner's manual

AGB-06-0001-002-B13

Released: May 27, 2005

Programming Manual

Version 1.35



1999-2005 NINTENDO

ii

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AGB-06-0001-002-B13

Released: May 27, 2005

"Confidential"

These coded instructions, statements, and

computer programs contain proprietary

information of Nintendo of America I

nc. and/or Nintendo Company Ltd., and are pro-

tected by Federal copyright law. They may not be disclosed to third

parties or copied

or duplicated in any form,

in whole or in part, without the

prior written consent of Nin-

tendo.



1999-2005 NINTENDO

TM and ®

are trademarks of Nintendo.

All other trademarks and copyrights are pro

perty of their respective owners.

May 25, 2005

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Released: May 27, 2005

Table of Contents

Contents

Revisi

on

History.....................

............

.............

............

............xiii

Introdu

ction

...........

.............

............

..........

.............

....

xxi

Using

This

Manua

l

.............

..........

.............

...xxii

1

The

Game

Boy

Advan

ce

System

.............

..............

.............

..............

...........1

1.1

System

Overv

iew.....................

.............

............

.............

............

.............

..........1

2

System

Configu

ration

............

.............

...........

........3

2.1

CPU

Block

Diagram...............

.............

............

.............

..........3

2.2

Complet

e

Block

Diagra

m

.............

............

....

4

2.3

Memory

Config

uration

and

Acces

s

Widths................

.............

...............

.............

..........5

2.4

Little-E

ndian................

............

.............

............

.............

..........

............5

3

Game

Boy

Advanc

e

Memory..

.............

..............

.............

...........

......7

3.1

Overall

Memory

Map

.............

............

.............

..........7

3.2

Memory

Config

uration

...........

.............

.........8

3.2

.1

Gam

e

Boy

Adv

anc

e

Inte

rna

l

Memo

ry

....

.....

....

.....

....

.....

....

.....

....

.....

....

.....

....8

3.2.2

Game

Pak

Memory

............

.............

............

.............

............

......9

3.3

Game

Pak

Memory

Wait

Control........................

.............

......9

3.3.1

Acces

s

Timing........

.............

............

.............

............

.............

............

...12

3.3.2

Game

Pak

Bus......................

.............

............

.............

...........

.

13

4

LCD

.............

............

.............

............

.............

............

..........

............

............15

4.1

LCD

Status

............

.............

............

.............

............

.............

............

.........

....

16

4.1.1

V

Counter.................

.............

............

..............

...........

.............

..........

....16

4.1.2

Genera

l

LCD

Status..................

.............

............

.............

........16

5

Image

System..

.............

............

.............

..........

.............

....

19

5.1

BG

Modes................

............

.............

............

.............

............

.............

............21

5.1.1

Details

of

BG

Modes

.............

............

.............

............21

5.1.2

VRAM

Memory

Map...............

.............

..............

.........23

6

Rende

ring

Funct

ions

.............

............

.............

...........

.......25

6.1

Charact

er

Mode

BG

(BG

Modes

0-2)

.............

..............

.............

.......25

6.1.1

BG

Control

............

.............

............

.............

...........

.............

............

.....25

6.1.2

Mosaic

Size............

............

.............

............

.............

............

...........

.....29

6.1.3

VRAM

Addres

s

Mappin

g

of

BG

Data........................

.............

..............

............30

6.1.4

Charac

ter

Data

Format

............

.............

............

.........32

6.1

.5

BG

Scr

een

Dat

a

For

mat

....

.....

....

.....

....

.....

....

.....

....

.....

....

.....

....

.....

....

.

33

6.1.

6

BG Scre

en Data Ad

dre

ss Mapp

ing for th

e LCD Scre

en

....

.....

....

.....

....

....35

6.1

.7

BG

Rota

tion

and

Sca

ling

Fea

ture

s

....

.....

....

.....

....

.....

....

.

40

6.1.8

BG

Scroll

ing

...........

.............

............

.............

............

...........

....42

6.2

Bitmap

Mode

BGs

(BG

Modes

3-5)

..............

............

.............

............

...........43

6.2.1

BG

Control

............

.............

............

.............

...........

.............

............

.....43

6.2.2

BG

Rotatio

n/Scal

ing...............

.............

............

.............

...........43

6.2.3

Pixel

Data..............

.............

............

.............

............

..........

.......44

6.2.

4

Pix

el Data Addre

ss Mappi

ng for

the LCD Scree

n

....

.....

....

.....

....

....44

6.3

OBJ

(Object

)

.............

............

.............

............

..........

............47

6.3.1

OBJ

Functi

on

Overvie

w

............

.............

............

.............

............

.........47

6.3.2

Charac

ter

Data

Mappin

g

...........

.............

.......48

6.3.3

OAM

............

.............

............

.............

............

........

.......50

6.3

.4

OBJ

Rot

atio

n/S

cal

ing

Fea

ture

.....

....

.....

....

.....

....

.....

....

.....

..57

6.4

Displa

y

Priorit

y

of

OBJ

and

BG..............

.............

....58

6.4.1

Priority

Among

BGs

............

.............

............

.............

............

.............

..

58

6.4.2

Priority

Among

OBJs.............

.............

............

.............

............58

6.4.3

Priority

Among

BGs

and

OBJs..............

............

.............

............

..............

.........59

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AGB-06-0001-002-B13

Released: May 27, 2005

7

Color

Palette

s

...........

.............

............

.............

...........

............

........61

7.1

Color

Palette

Overvi

ew

.............

...........

......61

7.1.1

16

Colors

x

16

Palette

s

............

.............

........61

7.1.2

256

Colors

x

1

Palette........

.............

.

61

7.1.3

Color

0

Transp

arenc

y

............

.............

..........61

7.2

Color

Palette

RAM

............

.............

............

.............

..............

.............

............

...........

..

62

7.3

Color

Data

Format

...............

............

.............

............

.............

............

..........

..

63

8

Window

Featur

e

............

.............

............

.............

..............

.............

...........

............

..

65

8.1

Window

Positio

n

Setting.......................

............

.............

............

.............

.......65

8.2

Window

Contro

l

............

.............

..............

.............

............

.............

.........

.......65

8.2.1

Control

of

Inside

of

Window

............

.............

............

.............

..

66

8.2

.2

Con

trol of Outs

ide of Wind

ow and Insi

de of OBJ Windo

w

.....

....

.....

....

.....

....

.....

....

.....66

9

Color

Specia

l

Effects

............

.............

............

.............

...........

........67

9.1

Selectio

n

of

Color

Specia

l

Effects.......

.............

............

.............

........67

9.2

Color

Specia

l

Effects

Process

ing...........

.............

............

.............

............

......69

9.2.1

Coeffic

ients

for

Color

Specia

l

Effects............

............

.............

............

.............

..

69

10

Sound

............

.............

............

.............

............

.............

..........

.............

........71

10.1

Sound Bl

ock Diag

ram

............

.............

............

.............

............

..............

.........71

10.2

Direct

Sound

s A a

nd B

............

.............

..............

.............

...........

......71

10.2.1

Sound

FIFO

Input

Registe

rs

............

...............

.............

............

.............

............72

10.3

Sound

1

.............

...........

..............

............

.............

............

.............

............

......73

10.4

Sound

2

.............

............

.............

............

..........

......76

10.5

Sound

3

.............

............

.............

............

..........

......78

10.5.1

Wavefo

rm RA

M.....................

.............

...........

.............

..............

...........

.............

.

81

10.6

Sound

4

.............

............

.............

............

..........

......82

10.7

Sound Control................

............

..............

............

.............

............

..........

........84

10.8

Sound P

WM Con

trol

..............

.............

............

.............

........87

11

Timer

.............

............

..............

.............

............

.............

.........

.............

........89

11.1

Timer

Setting

............

.............

............

.............

...........

..........89

11.2

Timer Co

ntrol

.............

............

.............

............

.............

...........

..........89

12

DMA Transfer

.............

............

..............

.............

..........

............

......91

12.1

DMA 0

............

.............

............

.............

..........

..........91

12.1.1

Source

Address

...........

.............

............

.............

............

.............

.........92

12.1.2

Destin

ation

Addres

s

.............

..............

.............

...........92

12.1.3

Word

Count...................

............

.............

.......92

12.1.4

DMA

Contro

l

.............

............

.............

...........93

12.2

DMA 1 and 2.................

.............

..............

.............

........

.......95

12.2.1

Source

Address

...........

.............

............

.............

............

.............

.........95

12.2.2

Destin

ation

Addres

s

.............

..............

.............

...........95

12.2.3

Word

Count...................

.............

............

.............

.......96

12.2.4

DMA

Contro

l

.............

............

.............

...........97

12.3

DMA 3

............

.............

............

.............

..........

..........99

12.3.1

Source

Address

...........

.............

............

.............

............

.............

.........99

12.3.2

Destin

ation

Addres

s

.............

..............

.............

...........99

12.3.3

Word

Count...................

.............

............

.............

.....100

12.3.4

DMA

Contro

l

.............

............

.............

.........100

12.3.5

Display

Synchr

onizati

on DMA............

..............

............

.............

............

.........103

12.4

DMA Pro

blems:

How to

Avoid

Them

............

.............

............

.........104

12.4.1

When

the D

MA Re

peat F

unctio

n is

not

Used

...........

.............

............104

12.4.2

When

the DM

A Rep

eat F

unction

is Use

d

.............

...........

.............

.....104

13

Commun

ication Functions......................

.............

..............

.............

..........107

13.1

8-Bit/32

-Bit No

rmal S

erial

Commun

ication

.............

..............

.............

.........108

13.1.1

SIO

Timing

Chart

.............

.109

13.1.2

32-Bit

Normal

Serial

Communic

ation

Data R

egister

s

.............

............

............110

May 25, 2005

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Released: May 27, 2005

13.1.3

Control

Regist

er

.............

..............

............

.............

............

.....110

13.2

16-Bit Mult

i-playe

r Communic

ation.....................

............

.............

............

.....113

13.2.1

Connec

tion S

tatus

during

Multi-p

layer

Commun

ication

.............

..............

.......113

13.2.2

Data

Registe

rs

...............

.............

............

.............

............

......115

13.2.3

Data

Transiti

on

Diagram

.............

...........

.............

............

.............

......116

13.2.4

Control

Regist

er

.............

..............

............

.............

............

.....117

13.3

UART

Communi

cation

Functio

ns

.............

..............

............

.............

............

.............120

13.3.1

Data

Registe

r

............

.............

............

.............

............

..........120

13.3.2

Relatio

ns Be

tween

Data

Registe

r, FIF

O, and

Shift

Registe

r

.............

.............120

13.3.3

When

FIFO

is

not

Used

............

..............

............

.............

............

.............

......120

13.3.4

When

FIFO

is

Used

...........

..............

.............

..............

.............

..........121

13.3.5

Control

Regist

er

.............

..............

............

.............

............

.....122

13.4

General-

Purpose

Communic

ation

............

.............

............

.............

..

125

13.5

JOY Bus Communic

ation.........

.............

...126

13.5.1

JOY

Bus

Communi

cation

Control

............

.............

............

.............

.....126

13.5.2

Receiv

e

Data

Register

s

...........

.............

............

.............

............

.........127

13.5.3

Send

Data

Registe

rs

..............

.............

............

.............

............

..........127

13.5.4

Receiv

e

Status

Registe

r

...........

.............

..............

.............

..............

...

127

13.5.5

JOY

Bus

Commun

ication

Operati

ons

..............

.............

............

.............

.........128

13.5.6

[JOY

Bus

Reset]

Comman

d(FFh)

Receiv

ed

.............

............128

13.5.7

[Type/S

tatus

Data

Request

] Comm

and(00h

) Rec

eived...................

.............

..

128

13.5.8

[JOY Bu

s Data

Write] C

ommand

(15h)

Receive

d

.............

.....129

13.5.9

[JOY Bu

s Data

Read]

Command

(14h) R

eceive

d.....................

............

............129

13.6

Game Bo

y Advan

ce Game

Link Ca

ble

...............

............

.............

............

.....131

14

Key Input

............

.............

............

.............

............

..............

...........

.............

............133

14.1

Key

Status

............

.............

............

.............

............

.............

............133

14.2

Key Interrupt Control.....

............

.............

............

.............

..........

......133

14.2.1

Interru

pt Conditi

ons..............

............

.............

............

.............

...........

.

133

15

Interru

pt

Control.

.............

............

.............

...........

............135

15.1

Interrupt Ma

ster Enab

le Registe

r

.............

............

.............

..135

15.2

Interrup

t Enable Regist

er........................

............

.............

............

.............

...........

.....135

15.3

Interrup

t Request Register......

..............

............

.............

............

.....136

15.3.1

About

H-Blank

Interrup

ts..................

.............

............

.............

............136

15.3.2

About

Game

Pak

Interrup

ts

............

.............

............

.............

.............136

15.3.3

Caution

s Re

garding

Clearing

IME a

nd IE

.............

............

.....136

15.3.4

Other

Caution

s

.............

............

.............

......136

15.4

System-A

llocate

d Area

in Work

RAM

..............

.............

............

.............

......137

15.5

Interru

pt Operation..........

............

.............

............

.............

............

.........

.....137

15.5.1

Normal

Interrup

t

.............

............

.............

............

......138

15.5.2

Multiple

Interrup

ts

............

..............

.............

............

.............

..

139

16

Power-D

own Func

tions

............

.............

............

.............

...........

..

141

16.1

Stop

Functi

on............

.............

............

.............

...........

........141

16.1.1

Stop

Funct

ion

Summary

.............

..............

.............

..

141

16.1.2

Impleme

nting

Stop

............

..............

.............

............141

16.1.3

System Wo

rking Sta

tus in Stop

Mode....

.............

............

.............

......141

16.1.4

Stop Fu

nction

Caution

s..................

.............

..............

.............

............142

16.1.5

Guidelin

es fo

r Use

of the

Stop

Functio

n

............

.............

......142

16.2

Halt

Functi

on.............

.............

............

.............

...........

........144

16.2.1

Halt Func

tion Summ

ary.......

.............

...........144

16.2.2

Halt T

ransitio

n Me

thod.........................

.............

............

.............

............

.........144

16.2.3

System Wo

rking Sta

tus in Halt M

ode.....

.............

............

.............

......144

17

Game Boy Advance System Calls...

.............

............

.............

......145

17.1

System Cal

l Operation..............

.............

..........

.....145

17.1.1

Normal

Calls

...............

..............

............

.............

...........

.............

..............

.......145

vi

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5

AGB-06-0001-002-B13

Released: May 27, 2005

17.1.2

Multiple

Calls..........

.............

..............

.............

..........146

18

ROM Regis

tration D

ata

.............

............

.............

..........

..

149

18.1

Start Addr

ess

............

.............

............

.............

...........

........149

18.2

Nintend

o Logo Cha

racter Da

ta

.............

............

.............

............

.............

......149

18.3

Game

Title

.............

............

.............

..........

............149

18.4

Game

Code

.............

............

.............

............

.............

............

.........149

18.5

Maker

Code

.............

............

.............

............

...........

..........149

18.6

96h..................

.............

............

.............

............

...........

......149

18.7

Main Un

it Code

.............

............

.............

..........

.....149

18.8

Device Type................

.............

..........

......150

18.9

Mask R

OM Versi

on No.

............

.............

..

150

18.10

Comple

ment

Check

............

.............

..............

.......150

18.11

Reserv

ed

Area.................

.............

..............

.............

..........150

May 25, 2005

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1

3

Released: May 27, 2005

Tables

Table 1 - Game Boy Advance Memory Configuration and Access Widths................................................5

Table 2

-

Game Pak

Memory Wait

Control Values

...............

.............

...........

.............

....11

Table 3

-

Wait

Contro

l

Values and

Wait Cycles

............

.............

..............

.............

........12

Table

4

-

Game

Pak

Bus

Termina

ls......................

.............

...........

.......13

Table 5

-

Game Boy

Advanc

e Display Screen

Featur

es

.............

..............

.............

.......15

Table 6

- Background Mode Details (Characte

r Format

BG Screen)

............

..............

.............

..............

.

21

Table

7

-

Background

Mode

Details (Bitmap

Format BG

Screen)

...........

............

...

22

Table

8

-

Backgro

und

Mode

Regis

ters

............

.............

..............

.........25

Table

9

-

Screen Size

Setting

s

...........

.............

............

.............

............

............27

Table

10

-

BG

Mode

3..............

.............

...........

..........44

Table 11

-

BG

Mode 4

(Frame 0)

..............

.............

...............

.............

...........

....

45

Table 12

-

BG

Mode 4

(Frame 1)

..............

.............

...............

.............

...........

....

45

Table 13

-

BG

Mode 5

(Frame 0)

..............

.............

...............

.............

...........

....

46

Table 14

-

BG

Mode 5

(Frame 1)

..............

.............

...............

.............

...........

....

46

Table

15

-

OBJ

Functi

on

Featu

res......................

.............

.......47

Table 16

- Rendering

Cycles and

the Corresponding Number

of Displayable Objects

...........

............

....

48

Table 17 - Specifications for the BLDCNT Register.................................................................................68

Table 18

-

EVA, EVB,

and EVY

Values

.............

............

.............

............69

Table 19

-

Sound 1

Freque

ncy

Change Bits

..............

.............

...............

.............

..............

.........73

Table 20

-

Sound 3

Output Level Selections

.............

..............

.............

..............

.........79

Table 21

-

Sound 4

Prescal

ar

Input Clock Selection

............

.............

............

.............

............

....84

Table 22 -

PWM Modulation Amplitu

de Resolutio

n and

Samplin

g Cycle Frequency

..............

..

88

Table

23

-

Timer

Control Prescalar

Selectio

n

............

.............

............

.............

..........

....

90

Table 24 - DMA Transfer Timing Selections (DMA 0)..............................................................................94

Table 25 - DMA Transfer Timing Selections (DMA 1 and 2)....................................................................98

Table 26 - DMA Transfer Timing Selections (DMA 3)............................................................................101

Table

27

-

Communi

cation

Functio

ns

..............

...............

.............

............

.............

........107

Table 28

-

Normal Serial

Communic

ation Baud

Rates

.............

..............

.............

..............

.......118

Table 29

-

UART

Communi

cation Error

Conditi

ons

............

.............

...

123

Table 30

-

UART Communicatio

n

Baud Rates

.............

..............

.............

......124

Table 31

-

The JOY

Bus Reset

Comman

d

............

..............

.............

..............

...........

.

128

Table 32 - The Type/Status Data Request Command...........................................................................128

Table 33

-

The JOY

Bus Data

Write Command........................

.............

............

.............

..........129

Table 34 - The JOY Bus Data Read Command.....................................................................................129

Table 35

-

System Status while in

Stop Mode

.............

..............

.............

..............

.............

......141

Table 36 - Terminology for Entering Sleep Mode from the Menu Screen..............................................142

Table 37 -

Terminol

ogy for Entering Sleep Mode Using a

Buttons Shortc

ut

.............

..............

..............143

Table 38 - Terminology for Automatically Entering Sleep Mode............................................................143

Table 39

-

System Status while in

Halt Mode

............

.............

..............

.............

.........144

viii

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AGB-06-0001-002-B13

Released: May 27, 2005

Figures

Figure 1

-

Bit

Operati

on

Attribute Symbols

..............

............

.............

............

...........

......xxii

Figure 1 - Game Boy Advance CPU Block Diagram..................................................................................3

Figure 2

-

Complete Game Boy

Advanc

e

System Block Diagram....................

..............

.............

.

4

Figure 3 - Game Boy Advance CPU Memory Addresses (Little-Endian)...................................................5

Figure 4 - Game Boy Advance System Memory Map................................................................................7

Figure

5

-

The

WAITCNT

Registe

r...................

..............

.............

..............

...........

.........10

Figure 6

-

Sequen

tial Access

Timing Chart

..............

............

.............

............

..........

.......12

Figure 7

-

Random Access

Timing Chart

...............

.............

............

.............

...........

.......12

Figure 8 - Display Screen Horizontal and Vertical Blanking Intervals......................................................15

Figure

9

-

The

VCOUNT

Regist

er.........................

.............

..............

.............

..............

.........

.......16

Figure 10

-

The

DISPSTA

T

Registe

r

...........

.............

..............

.............

..............

.............

..........

..

16

Figure 11

-

The

DISPCNT Register

.............

............

..

19

Figure 12 - Background Mode Memory Maps..........................................................................................23

Figure 13

-

Backgro

und

Screen Control

Registe

rs

.............

............

.............

...........

.......26

Figure 14 - Text Background and Rotation/Scaling Background Screen Control Registers....................26

Figure 15

-

Text

Backg

round Screen

Sizes

............

.............

............

......27

Figure 16

-

Rotation

/Scaling Background Screen

Sizes

...........

.............

............

.............

............28

Figure

17

-

The

MOSAIC

Registe

r

.............

..............

.............

..............

.............

..........

....

29

Figure

18

-

Mosaic

Schema

tic

...........

.............

............

..............

............

..

29

Figure 19

-

VRAM Base

Blocks for

Backgr

ound Data

............

.............

..............

.............

............31

Figure 20 - 16-Color x 16-Palette Character Data Format.......................................................................32

Figure 21

-

256-Col

or

x

1-Palet

te

Charac

ter Data

Format.................

.............

..

33

Figure 22 - Text Background Screen Format...........................................................................................34

Figure 23

-

Rotatio

n/Scali

ng

Backgr

ound Screen

Format

...........

..............

.............

...............

.............

.....34

Figure 24

- Virtual Screen

Size of

256 x

256 Pixels (Text

Background)

...........

......

35

Figure 25

- Virtual Screen

Size of

512 x

256 Pixels (Text

Background)

...........

......

36

Figure 26

- Virtual Screen

Size of

256 x

512 Pixels (Text

Background)

...........

......

36

Figure 27

- Virtual Screen

Size of

512 x

512 Pixels (Text

Background)

...........

......

37

Figure 28 - Virtual Screen Size of 128 x 128 Pixels (Rotation/Scaling Background)...............................37

Figure 29 - Virtual Screen Size of 256 x 256 Pixels (Rotation/Scaling Background)...............................38

Figure 30 - Virtual Screen Size of 512 x 512 Pixels (Rotation/Scaling Background)...............................38

Figure 31 - Virtual Screen Size of 1024 x 1024 Pixels (Rotation/Scaling Background)...........................39

Figure 32 - Referencing Rotated Background Data.................................................................................40

Figure 33 - Registers for Setting the Starting Point of BG Data...............................................................41

Figure 34 -

Register

s for

Setting the Direction Para

meters of BG

Data

.............

..............

.............

..........41

Figure

35

-

Offset

Setting

s

Registe

rs........................

............

.............

............

..........

.......42

Figure

36

-

Offset

Illustra

tion...........

.............

............

.............

............

...........

............

......43

Figure 37

-

The

BG2CNT Register

............

..............

.............

...........

....

43

Figure 38 - 32,768-Color Simultaneous Display Format..........................................................................44

Figure

39

-

256-Col

or

Display

Format.......

.............

............

.............

..........

........44

Figure 40 - VRAM 2-Dimensional Mapping for OBJ Characters..............................................................49

Figure 41 - VRAM 1-Dimensional Mapping for OBJ Characters..............................................................49

Figure 42

-

Writing Rotation/Sc

aling Parameters to OAM

.............

......51

Figure

43

-

OBJ

Attribute 0

...........

.............

............

.............

............

......52

Figure 44 - Cropping when Displaying a Scaled or Rotated Object.........................................................53

Figure 45

-

Croppin

g

when Displaying a

Magnifi

ed Character

.............

..............

.............

...........54

Figure

46

-

OBJ

Attribute 1

...........

.............

............

.............

............

......55

Figure

47

-

Object

Sizes

...........

.............

............

.............

...........

..........55

Figure

48

-

OBJ

Attribute 2

...........

.............

............

.............

............

......56

Figure 49

-

OBJ Character Data

Referen

ced with

Rotation................

.............

............

.............

............

...

57

Figure 50

-

Object

Rotation

/Scaling Parameters

.............

............

.............

........58

Figure 51

-

Backgro

und

and

Object

Priority...............

.............

............

.............

..........

....

59

Figure 52

-

Color Palette

RAM

Memory Map

.............

............

.............

..........

....62

May 25, 2005

ix

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-

0

1

-

0

2

-

B

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Released: May 27, 2005

Figure 53 - Referencing Palette RAM for OBJ and BG Modes................................................................62

Figure

54

-

Color

Data

Format

............

...............

.............

............

.............

...........

............63

Figure 55 - Window Position Setting Registers........................................................................................65

Figure 56

-

Window Display

Priority Example.........................

.............

............

.............

..........

....65

Figure 57

-

The

WININ

Registe

r

.............

..............

.............

..........

........66

Figure 58

-

The

WINOUT

Registe

r

.............

..............

.............

..........

....

66

Figure 59 - The BLDCNT Register...........................................................................................................67

Figure 60 -

The

BLDALP

HA

and

BLDY

Regist

ers

.............

..............

.............

....

69

Figure 61 -

α

Blendi

ng

betwee

n

OBJ

and

BG

.............

............

.............

............70

Figure 62 - Game Boy Advance Sound System Block Diagram..............................................................71

Figure 63

-

Sound FIFO

Input

Regist

ers......................

.............

..............

.............

..............

.........72

Figure 64 - The SOUND1CNT_L Register...............................................................................................73

Figure

65

-

The

SOUND1

CNT_H

Registe

r

.............

..............

.............

..............

.............

...........

...74

Figure 66 - Waveform Amplitude Peak Proportions.................................................................................75

Figure 67

-

The

SOUND1

CNT_X

Registe

r

............

.............

..............

.............

...75

Figure 68 - The SOUND2CNT_L Register...............................................................................................76

Figure

69

-

The

SOUND2

CNT_H

Registe

r

.............

..............

.............

..............

.............

...........

...77

Figure 70 - The SOUND3CNT_L Register...............................................................................................78

Figure

71

-

The

SOUND3

CNT_H

Registe

r

.............

..............

.............

..............

.............

...........

...79

Figure 72

-

The

SOUND3

CNT_X

Registe

r

............

.............

..............

.............

...79

Figure

73

-

Wavefo

rm

RAM

Registe

rs

.............

...............

.............

........81

Figure 74 - The SOUND4CNT_L Register...............................................................................................82

Figure

75

-

The

SOUND4

CNT_H

Registe

r

.............

..............

.............

..............

.............

...........

...83

Figure 76 - The SOUNDCNT_L Register.................................................................................................84

Figure 77

-

The

SOUNDCNT

_X

Registe

r

.............

..............

............

.............

............

.......85

Figure

78

-

The

SOUNDCN

T_H

Regist

er

...........

.............

.......86

Figure

79

-

The

SOUNDBI

AS

Regist

er

............

.............

............

.............

...........87

Figure

80

-

PWM

Conver

sion

Image..........

............

.............

............

.............

..........

........88

Figure

81

-

Timer

Setting

Regist

ers

..............

.............

............

.............

..........

....

89

Figure

82

-

Timer

Control

Register

s................

............

.............

..............

.............

............

...........

..

89

Figure 83

-

DMA

0

Source Address

Regist

ers......................

.............

...........

....92

Figure 84

-

DMA 0

Destina

tion Address Registers

............

.............

.....92

Figure

85

-

The

DMA0CNT

_L

Registe

r.....................

............

.............

...........

.............

..........

.......92

Figure

86

-

The

DMA0CNT

_H

Regist

er

.............

...............

............

.............

............

.............

........93

Figure 87

-

DMA 1

and 2

Source Address Registers..............

.............

...............

.............

...........95

Figure 88

-

DMA 1

and 2

Destinat

ion Address Registers

............

.............

........95

Figure 89 -

DMA 1

and 2

Word Count Registers

..............

............

.............

............

.............

........96

Figure 90

-

DMA 1

and 2

Control Register

s

.............

..............

.............

..............97

Figure 91

-

DMA

3

Source Address

Regist

ers......................

.............

...........

....99

Figure 92

-

DMA 3

Destina

tion Address Registers

............

.............

.....99

Figure 93 - The DMA3CNT_L Register..................................................................................................100

Figure

94

-

The

DMA3CNT

_H

Regist

er

.............

...............

............

.............

............

.............

......100

Figure 95 - Connecting during Normal Serial Communication:..............................................................108

Figure 96

-

SIO Timing

Chart (8-bit Communication

)

.............

............

.............

............

.............109

Figure 97

-

The

SIODATA

8

Regist

er

.............

..........109

Figure 98 - 32-Bit Normal Serial Communication Data Registers..........................................................110

Figure 99

-

The

SIOCNT Register

(32-Bits

)

............

.............

............

.............

...............110

Figure 100 - Normal Serial Communication Flow (Example).................................................................112

Figure 101

-

Multi-Pl

ayer

Communi

cation Connection Status

..............

...............

......113

Figure 102

-

Multi-pla

yer

Communi

cation Timing

Chart

............

.............

..............

.............

.......114

Figure 103 - Multi

Player Game Boy Advance Game Link Cable Connectin

g Diagram

..............

..........115

Figure 104 - The SIOMLT_SEND Register............................................................................................115

Figure

105

-

Multi-Pl

ayer

Data

Registe

rs

..............

............

.............

............

...........

........115

Figure 106

-

Multi-Pl

ayer

Data

Transit

ions

..............

............

.............

............

...........

.....116

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AGB-06-0001-002-B13

Released: May 27, 2005

Figure

107

-

The

SIOCNT

Registe

r

(16-Bit)........

..............

............

.............

............

.............

......117

Figure 108

-

Multi-pla

yer

Communi

cation Flow

(Examp

le)

............

.............

....119

Figure

109

-

UART

Commun

ication..............

.............

..............

.............

..............

.........120

Figure 110

-

The

SIODATA8 Register

...............

.............

............

.............

........120

Figure 111

-

Serial Communicatio

n

withou

t

FIFO.....................

.............

..............

.............

..............

.......120

Figure 112

-

Serial Communicatio

n

with

FIFO......................

..............

.............

..............

..........121

Figure 113 - Example: Writing Data Registers.......................................................................................121

Figure 114

-

The SIOCNT

Regist

er

(UART)

.............

..............

.............

..............

.........122

Figure 115

-

The RCNT

Registe

r

(Genera

l-Purpos

e

Commun

ication

)

..............

.............

..........125

Figure 116 -

The RCNT Register (JOY

Bus Communicat

ion)

............

.............

............

.............

.............126

Figure 117 - The JOYCNT Register.......................................................................................................126

Figure 118 - JOY Bus Receive Data Registers......................................................................................127

Figure 119

-

JOY Bus

Send Data

Registe

rs

..............

.............

............

.............

..........

..

127

Figure

120

-

The

JOYSTA

T

Registe

r

............

..............

.............

.........127

Figure 121 - Game Boy Advance Game Link Cable Connection Types................................................131

Figure

122

-

The

KEYINPUT Register

...............

.............

............

.............

........133

Figure 123

-

The

KEYCNT

Registe

r

...............

..............

............

.............

............

.............

..........133

Figure

124

-

The

IME

Registe

r.................

.............

..............

.............

..........

.....135

Figure

125

-

The

IE

Regist

er...............

.............

..............

.............

...........

........135

Figure

126

-

The

IF

Registe

r

...........

..............

.............

..............

.............

...........

............136

Figure 127

-

System-

Allocate

d

Area

in

Work RAM

.............

............

.............

...........

.....137

Figure 128 -

Game Boy Advance ROM

Registra

tion Data

...........

.............

............

.............

......149

Figure

129

-

Device

Type

Bits............

..............

.............

............

.............

............

...........

............150

May 25, 2005

xi

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O

A

G

B

-

0

6

-

0

1

-

0

2

-

B

1

3

Released: May 27, 2005

Equations

Equatio

n

1

-

Backgro

und

Rotation and

Scaling

..............

.............

............

.............

..........41

Equatio

n

2

-

Determin

ing

Single-S

hift

Freque

ncy

Data

.............

..........74

Equation 3 - Determining the Length of 1 Step (steptime).......................................................................74

Equatio

n

4

-

Determin

ing the

Length of the

Output Sound

.............

..............

.............

...............

.............

..

75

Equatio

n

5

-

Determin

ing

the

Output Frequency

..............

............

.............

............

.............

........75

Equation 6 - Determining the Length of 1 Step (steptime).......................................................................77

Equatio

n

7

-

Determin

ing the

Length of the

Output Sound

.............

..............

.............

...............

.............

..

77

Equatio

n

8

-

Determin

ing

the

Output Frequency

..............

............

.............

............

.............

........77

Equatio

n

9

-

Determin

ing the

Length of the

Output Sound

.............

..............

.............

...............

.............

..

79

Equatio

n

10

-

Determin

ing

the

Output Frequenc

y

.............

.....80

Equatio

n

11 -

Determin

ing the

Length of

1

Step (steptime)...................

.............

...........82

Equatio

n

12 -

Determin

ing the

Length of

the Output Sound

............

.............

....

82

Equation 13 - Selecting the Shift Clock Frequency..................................................................................83

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,

2

0

5

AGB-06-0001-002-B13

Released: May 27, 2005

May 25, 2005

xiii

©

1

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-

2

0

5

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D

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A

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0

6

-

0

1

-

0

2

-

B

1

3

Released: May 27, 2005

Revision History

Revision

No.

Date

Revised

Description

1

.

3

5

3

/

7

/

2

0

5

•

A

d

e

d

"

P

r

e

c

a

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t

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o

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a

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d

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e

m

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m

a

p

"

t

o

"

3.1 Overall Memory Map

"

on page 7

.

1

.

3

4

a

1

/

2

6

/

2

0

4

•

C

o

r

e

c

t

e

d

n

o

t

e

i

n

"

10.8 Sound PWM Control

" on page 87

.

1

.

3

4

1

0

/

6

/

2

0

3

•

S

p

e

c

i

f

i

e

d

t

h

a

t

f

o

r

c

o

l

o

r

s

p

e

c

i

a

l

e

f

e

c

t

s

,

α

blending cannot be performed

between OBJs.

•

Cor

rect

ed an e

rron

eou

s ent

ry for t

he br

igh

tnes

s adj

ustm

ent c

alc

ulat

ion

method (G) in color special effects.

•

Cor

rect

ed an

erro

neo

us e

ntry

in th

e nor

mal s

eri

al co

mmun

ica

tion

s flo

w

diagram.

•

Add

ed th

at the

IF re

gis

ter’s

H-Bl

ank i

nte

rrup

t req

ues

t can a

lso o

ccu

r dur

-

ing V-Blank.

1

.

3

2

1

/

3

0

/

2

0

3

•

C

h

a

n

g

e

d

e

x

p

l

a

n

a

t

i

o

n

o

f t

h

e

s

t

a

r

t b

i

t a

n

d

b

u

s

y f

l

a

g

i

n

t

h

e

SIOCNT

register

under

"

13.2 16-Bit Multi-player Communication

" on page 113

.

•

Ch

an

ge

d t

he

ex

pl

an

at

io

n o

f t

he

JOYSTAT

register under

"

13.5 JOY Bus

Communication

" on page 126

.

•

Ad

de

d re

co

mm

en

de

d te

xt s

tr

in

gs t

o

"

16.1.5 Guidelines for Use of the

Stop Function

" on page 142

.

•

In T

abl

es 24

, 25, a

nd 26

, add

ed th

at the

H-Bl

ank i

nte

rval s

tar

tup f

or DMA

can only occur during the H-Blank for the display interval.

1

.

3

0

3

/

1

8

/

2

0

2

•

A

d

e

d

a

J

O

Y

B

u

s

c

o

m

u

n

i

c

a

t

i

o

n

c

a

u

t

i

o

n

•

Cor

rect

ed th

e se

ctio

n abo

ut no

rmal

ser

ial c

ommu

nica

tion

s to r

ead t

hat

the state of the master's SD terminal “outputs a LO” instead of “pull-up

input.”

•

Add

ed

gui

del

ine

s o

n u

se

of

the

St

op

(Sle

ep)

fea

ture

.

1.

25

10

/2

6/

20

0

1

•

Fi

xe

d

th

e

bi

t

co

nt

en

t

s

of

ge

ne

ra

l-

pu

rp

o

se

co

mm

un

ic

at

io

n

re

gi

st

er

R.

•

Spe

cifi

ed th

e nu

mbe

r of lo

st cy

cle o

f OBJ

out

side

of re

nde

ring

line

in

“OBJ Function Overview”.

•

Ch

an

ge

d the c

omm

an

d nam

es o

f “JO

Y Bus C

omm

un

ica

tio

n.

(Device Reset -> JOY Bus Reset, GBA Data Write -> JOY Bus Data

Write, GBA Data Read -> JOY Bus Data Read

）

•

Mo

dif

ie

d co

nd

iti

on

s fo

r ca

nc

el

ing

S

to

p Mo

de

.

•

Ad

de

d to [

S

to

p Fu

nc

ti

on C

au

ti

on

s]

.

•

Cha

nge

d the

exp

lana

tion

of De

vice

T

ype

and a

dde

d a di

agra

m of R

OM

registration data.

xiv

G

a

m

e

B

o

y

A

d

v

a

n

c

e

P

r

o

g

r

a

m

i

n

g

M

a

n

u

a

l

M

a

y

2

5

,

2

0

5

AGB-06-0001-002-B13

Released: May 27, 2005

1

.2

2

8

/

1

0

/2

0

1

•

F

i

x

ed

s

e

c

ti

o

n e

x

p

l

a

in

i

n

g G

a

me

Pa

k i

n

te

r

ru

p

t

s i

n t

h

e “

In

t

e

rr

u

p

t C

o

n

tr

o

l

”

chapter.

•

Add

ed ad

diti

ona

l info

rmat

ion to

exp

lan

atio

ns ab

out t

he DIS

PCNT

regi

s-

ter’s Individual Screens Display Flag and Forced Blank.

1

.2

0

7

/

2

4

/2

0

1

•

M

o

d

i

fi

e

d

t

h

e

C

o

m

p

l

e

te

Bl

o

c

k

Di

a

gr

a

m

f

o

r t

h

e

s

y

s

te

m

a

r

ch

it

e

ct

u

re

.

•

Mod

ifie

d the

cau

tion

s for

prio

rity

in th

e “Di

spl

ay Pr

iori

ty o

f OBJ a

nd BG

”

section.

•

Fix

ed th

e exp

lan

atio

n at th

e beg

inn

ing o

f the “D

MA T

ran

sfer

” cha

pte

r.

•

Add

ed se

ctio

n exp

lain

ing Ga

me Pak

int

erru

pts t

o the “

Inte

rrup

t Con

trol

”

chapter.

•

Add

ed

cau

tion

s t

o t

he

“Int

erru

pt

Con

trol

” c

hap

ter

.

•

Fi

xed

th

e Mu

lti

-Pl

ay c

om

mu

nic

at

ion

flo

wc

ha

rt.

•

Fix

ed th

e BLD

ALP

HA re

gis

ter s

o tha

t rea

din

g and

writ

ing a

re bo

th po

ssi-

ble.

1

.

1

5

/

7

/

2

0

1

•

A

d

e

d

c

a

u

t

i

o

n

s

t

o

“

C

o

m

u

n

i

c

a

t

i

o

n

F

u

n

c

t

i

o

n

”

c

h

a

p

t

e

r

.

•

Ad

de

d c

au

tio

ns

to

“K

ey

In

pu

t”

ch

ap

ter

.

•

Ad

de

d ca

ut

io

ns t

o “S

to

p Fu

nc

tio

n” c

ha

pte

r

.

•

Add

ed to

exp

lana

tion

of fu

nct

ions

at th

e be

ginn

ing

of “D

MA T

ran

sfer

”

chapter.

•

Mod

ifie

d

the

flow

cha

rt

for

Mult

i-Pl

ay

com

mun

ica

tion

.

Revision

No.

Date

Revised

Description

May 25, 2005

xv

©

1

9

-

2

0

5

N

I

N

T

E

N

D

O

A

G

B

-

0

6

-

0

1

-

0

2

-

B

1

3

Released: May 27, 2005

1

.

1

4

/

2

/

2

0

1

•

C

h

a

n

g

e

d

t

h

e

p

i

c

t

u

r

e i

n t

h

e G

a

m

e B

o

y A

d

v

a

n

c

e i

n

t

r

o

d

u

c

t

i

o

n i

n

t

h

e

b

e

g

i

n

-

ning paragraph.

•

Add

ed a c

auti

on re

gar

din

g cle

arin

g of IM

E and

IE in

the c

hap

ter “

Inte

r-

rupt Control”.

•

Add

ed a

ddit

iona

l des

cri

ptio

n of a

n err

or fl

ag a

nd ID

flag

for m

ulti

-pl

ay

communication.

•

Add

ed ad

diti

ona

l des

cri

ptio

n of co

mmun

ica

tion

erro

r fla

g of mu

lti-

pla

y

communication control register.

•

Mod

ifie

d the

hos

t sid

e ex

ampl

e in th

e des

cri

ptio

n of J

OY bu

s co

mmu

ni-

cation from NUS to DOL. Added DOL to the abbreviation in “Using This

Manual”.

•

Mod

ifie

d the

SIO t

imin

g ch

art f

or n

orma

l se

rial

comm

unic

atio

n.

•

Rev

ise

d the

numb

er of c

olo

rs fr

om 25

6 to 3

2,76

8 in t

he d

esc

ript

ion o

f

Display Synchronization DMA of DMA3.

•

Mod

ifie

d the

des

cri

ptio

n of g

ene

ral-

pur

pos

e com

mun

icat

ion m

ode

.

•

Re

vi

se

d the ca

uti

on fo

r nor

ma

l ser

ial c

omm

un

ic

ati

on.

•

Re

vi

sed

the

ca

uti

on f

or c

omm

un

ic

ati

on f

un

cti

on

.

•

Rev

ise

d the

summ

ary o

f nor

mal s

eria

l com

muni

cati

on in

the c

ommu

nica

-

tion function chapter, and added additional description.

•

Add

ed ad

diti

ona

l des

crip

tion i

n the c

aut

ion fo

r the s

elec

tion

of co

mmu

ni-

cation function in the communication function chapter.

•

Emp

has

ized

that u

nle

ss ge

nera

l-pu

rpo

se co

mmu

nica

tion

mode

, the c

an-

cellation condition SIO for System Call Stop will not work.

•

Cha

nge

d LP

U to L

CD co

ntro

ller

in s

yste

m ca

lls H

alt

and

St

op.

•

De

le

ted

the

fir

st i

tem

in S

ou

nd 3

Us

ag

e No

te.

Revision

No.

Date

Revised

Description

xvi

G

a

m

e

B

o

y

A

d

v

a

n

c

e

P

r

o

g

r

a

m

i

n

g

M

a

n

u

a

l

M

a

y

2

5

,

2

0

5

AGB-06-0001-002-B13

Released: May 27, 2005

1.1

(Cont.)

4/

2/

20

01

•

Ch

an

ge

d th

e na

me

s of f

ol

lo

wi

ng r

eg

is

te

rs a

cc

or

di

ng t

o he

ad

er f

il

es p

ro

-

vided by Nintendo.

--Wait Control--

204h

WSCNT

_

WAITCNT

--Color Special Effects--

050h

BLDMOD

_

BLDCNT

052h

COLEV

_

BLDALPHA

054h

COLY

_

BLDY

--Sound Related--

080h~

SGCNT0_(L

H)

_

SOUNDCNT_(L H)

**

Combined multiple

names

084h

SGCNT1

_

SOUNDCNT_X

088h

SG_BIAS

_

SOUNDBIAS

060h~

SG10_(L

H)

_

SOUND1CNT_(L

H)

**

064h

SG11

_

SOUND1CNT_X

068h

SG20

_

SOUND2CNT_L

06Ch

SG21

_

SOUND2CNT_H

070h~

SG30_(L

H)

_

SOUND3CNT_(L

H)

**

074h

SG31

_

SOUND3CNT_X

078h

SG40

_

SOUND4CNT_L

07Ch

SG41

_

SOUND4CNT_H

090h~

SGWR(0-3)_L

_

WAVE_RAM(0-3)_

L

**

092h~

SGWR(0-3)_H

_

WAVE_RAM(0-3)_

H

**

0A0h~

SG_FIFOA_(L

H)

_

FIFO_A_(L

H)

**

0A4h~

SG_FIFOB_(L

H)

_

FIFO_B_(L

H)

**

--DMA Related--

0B0h~

DM(0-3)SAD_L

_

DMA(0-3)SAD_L

**

0B2h~

DM(0-3)SAD_H

_

DMA(0-3)SAD_H

**

0B4h~

DM(0-3)DAD_L

_

DMA(0-3)DAD_L

**

0B6h~

DM(0-3)DAD_H

_

DMA(0-3)DAD_H

**

0B8h~

DM(0-3)CNT_L

_

DMA(0-3)CNT_L

**

0Bah~

DM(0-3)CNT_H

_

DMA(0-3)CNT_H

**

--Timer Related--

100h~

TM(0-3)D

_

TM(0-3)CNT_L

**

102h~

TM(0-3)CNT

_

TM(0-3)CNT_H

**

--Communication Related--

134h

R

_

RCNT

128h

SCCNT_L

_

SIOCNT

12Ah

SCCNT_H

_

SIODATA8

(Normal

serial,

UART

communication)

SIOMLT_SEND

(Multi-play

communication

)

120h

SCD0

_

SIODATA32_L

(Normal

serial

communication

)

SIOMULTI0

(Multi-play

communication

)

122h

SCD1

_

SIODATA32_H

(Normal

serial

communication

)

SIOMULTI1

(Multi-play

communication

)

124h~

SCD(2

3)

_

SIOMULTI(2

3)

**

140h

HS_CTRL

_

JOYCNT

158h

JSTAT

_

JOYSTAT

150h~

JOYRE_(L

H)

_

JOY_RECV_(L

H)

**

154h~

JOYTR_(L

H)

_

JOYTRANS_(L

H)

**

--Key Related--

130h

P1

_

KEYINPUT

132h

P1CNT

_

KEYCNT

Revision

No.

Date

Revised

Description

May 25, 2005

xvii

©

1

9

-

2

0

5

N

I

N

T

E

N

D

O

A

G

B

-

0

6

-

0

1

-

0

2

-

B

1

3

Released: May 27, 2005

1

.

0

4

3

/

1

/

2

0

1

•

S

p

e

c

i

f

i

e

d

t

h

e

m

e

t

h

o

d

t

o

c

o

n

t

r

o

l

t

h

e

O

B

J

d

i

s

p

l

a

y

i

n

d

i

v

i

d

u

a

l

y

i

n

t

h

e

description of the double size flag and the rotation/scaling flag for OAM

attribute 0.

•

Add

ed t

he d

esc

ript

ion

of d

ispl

ay s

ync

hron

iza

tion

DMA

to DM

A3.

•

Add

ed th

e de

scri

ptio

n of th

e DMA

pro

ble

m and

how t

o avo

id it a

t the e

nd

of the chapter on DMA.

•

Add

ed th

e res

tric

tion

s to t

he d

esc

rip

tion

of th

e rep

eat f

lag i

n DMA

3.

•

Upd

ate

d the

timin

g cha

rt an

d the

cabl

e co

nne

ctio

n dia

gram

for t

he

multi-play communication.

•

Rev

ise

d the d

esc

ript

ion o

f the n

orma

l seri

al co

mmu

nica

tion

cau

tion

s.

1

.0

2

/

1

3

/2

0

1

•

M

o

d

if

ie

d t

h

e d

es

c

ri

p

ti

o

n o

f “

8

-

B

it

/3

2

-

Bi

t N

o

rm

a

l C

o

m

mu

n

ic

a

ti

o

n F

u

nc

-

tion” summary in “Communication” chapter.

•

Add

ed a p

ara

grap

h to “

Sele

ctin

g Com

mun

ica

tion

Fun

ctio

n” in

“Com

mun

i-

cation” chapter.

1

.

0

1

2

/

0

1

/

2

0

1

•

M

o

d

i

f

i

e

d

t

h

e

d

e

s

c

r

i

p

t

i

o

n

o

f

p

i

n

3

1

i

n

t

h

e

G

a

m

e

P

a

k

b

u

s

.

•

Rev

ise

d the c

anc

el co

ndit

ions

for th

e S

top fu

nct

ion in

the p

ower

-dow

n

mode.

•

Add

ed ad

diti

ona

l des

crip

tion

s and c

aut

ion

s for th

e ini

tial

iza

tion f

lag o

f

Sound 1.

1

.

0

1

2

/0

1

/

2

00

0

•

D

e

l

e

te

d

th

e

c

h

e

c

k

s

u

m

o

f

R

OM

re

g

is

t

ra

ti

o

n

d

a

t

a

n

d

re

v

i

s

e

d

t

h

e

•

d

i

a

g

r

a

m

.

•

Rev

ised

the d

iagr

am fo

r “Co

mmu

nica

tio

n Cab

le” i

n the

“Com

muni

cati

on

Function”.

•

Rev

ise

d the

num

ber o

f DMG

sol

d fro

m ten

s of m

illi

ons

to a h

und

red m

il-

lion in the Game Boy Advance introduction.

•

Rev

ise

d the

hou

rs yo

u ca

n pla

y co

ntin

uou

sly f

rom “

abo

ut 20

hou

rs” t

o

“about 15 hours”.

•

Rev

ise

d the

illu

stra

tion

s of t

he Ga

me B

oy Ad

van

ce h

ardw

are a

nd th

e

Multi Player Communication Cable in the multi play communication dia-

gram.

•

Add

ed th

e de

scri

ptio

n of th

e tim

ing c

hart

for n

orma

l SIO c

ommu

nic

atio

n.

•

Add

ed a c

aut

ion i

n the

DMA v

ali

d fla

g of a

ll th

e DMA

con

trol r

egi

ster

s.

•

Add

ed a ca

utio

n in th

e mas

ter s

tar

t bit of t

he mu

lti-

pla

y con

trol r

egi

ster

.

•

Re

vi

se

d th

e mu

lt

i-

pl

ay t

im

in

g ch

ar

t.

•

Rev

ise

d th

e me

mory

map

for s

yst

em re

ser

ve a

rea

in t

he w

ork R

AM.

•

Ad

de

d a c

au

tio

n to

“Co

mmu

ni

ca

tio

n Fu

nc

tio

n”.

•

Rev

ise

d the

firs

t sen

tenc

e in “

UAR

T Com

muni

cat

ion”

. Add

ed “R

ela

tion

between Data register, FIFO and Shift register”.

Revision

No.

Date

Revised

Description

xviii

G

a

m

e

B

o

y

A

d

v

a

n

c

e

P

r

o

g

r

a

m

i

n

g

M

a

n

u

a

l

M

a

y

2

5

,

2

0

5

AGB-06-0001-002-B13

Released: May 27, 2005

1.0

(Cont.)

12

/01

/2

00

0

•

Re

vi

se

d th

e ex

pr

es

si

on o

f [C

au

tio

ns

] to a

mo

re s

pe

cif

ic e

xp

res

si

on [

Ca

u-

tions for ~~].

•

Add

ed a d

esc

ript

ion o

f X co

ordi

nate

and

Y coo

rdin

ate f

or OA

M. Ad

ded

the diagram to Y coordinate.

•

Rev

ise

d the

des

crip

tion

of th

e pre

-fet

ch bu

ffe

r fla

g in t

he Ga

me Pa

k

memory wait control register.

•

Add

ed ca

utio

ns to t

he de

scr

ipti

on of th

e inp

ut/o

utpu

t sel

ect fl

ag in t

he R

register of general communication.

•

Del

eted

the c

hec

ksu

m of RO

M reg

istr

atio

n dat

a and r

evis

ed th

e dia

gram

.

•

Rev

ised

the

diag

ram

for “

Game

Boy

Adva

nce

Game

Lin

k Ca

ble”

in t

he

“Communication Function”.

•

Rev

ise

d the

num

ber o

f DMG

sol

d fro

m ten

s of m

illi

ons

to a h

und

red m

il-

lion in the Game boy Advance introduction.

•

Rev

ise

d the

hou

rs yo

u ca

n pla

y co

ntin

uou

sly f

rom “

abo

ut 20

hou

rs” t

o

“about 15 hours”.

•

Rev

ise

d the

illu

stra

tion

s of t

he Ga

me B

oy Ad

van

ce h

ardw

are a

nd th

e

Multi Player Game Boy Advance Game Link cable in the multi-play com-

munication diagram.

•

Add

ed th

e de

scri

ptio

n of th

e tim

ing c

hart

for n

orma

l SIO c

ommu

nic

atio

n.

•

Add

ed a c

aut

ion i

n the

DMA v

ali

d fla

g of a

ll th

e DMA

con

trol r

egi

ster

s.

•

Add

ed a ca

utio

n in th

e mas

ter s

tar

t bit of t

he mu

lti-

pla

y con

trol r

egi

ster

.

•

Re

vi

se

d th

e mu

lt

i-

pl

ay t

im

in

g ch

ar

t.

•

Rev

ise

d th

e me

mory

map

for s

yst

em re

ser

ve a

rea

in t

he w

ork R

AM.

•

Ad

de

d a c

au

tio

n to

“Co

mmu

ni

ca

tio

n Fu

nc

tio

n”.

•

Rev

ise

d the

firs

t sen

tenc

e in “

UAR

T Com

muni

cat

ion”

. Add

ed “R

ela

tion

between Data register, FIFO and Shift register”.

•

Rev

ise

d the e

xpr

ess

ion o

f [Cau

tion

s] to a m

ore s

pec

ific e

xpre

ssi

on [Ca

u-

tions for ~~].

•

Add

ed a d

esc

ript

ion o

f X co

ordi

nate

and

Y coo

rdin

ate f

or OA

M. Ad

ded

the diagram to Y coordinate.

•

Rev

ise

d the

des

crip

tion

of th

e pre

-fet

ch bu

ffe

r fla

g in t

he Ga

me Pa

k

memory wait control register.

•

Add

ed ca

utio

ns to t

he de

scr

ipti

on of th

e inp

ut/o

utpu

t sel

ect fl

ag in t

he R

register of general communication.

Revision

No.

Date

Revised

Description

May 25, 2005

xix

©

1

9

-

2

0

5

N

I

N

T

E

N

D

O

A

G

B

-

0

6

-

0

1

-

0

2

-

B

1

3

Released: May 27, 2005

0

.4

.

1

.8

1

0

/1

6

/

2

00

0

•

A

d

e

d

c

a

u

ti

o

n

s

to

th

e

p

ri

o

ri

ty

s

e

t

ti

n

g

o

f

OB

J

.

•

Add

ed

a de

scr

ipti

on

and

cau

tion

s to

Sou

nd 1

,2,3

, an

d 4.

•

Ad

de

d the d

esc

rip

tio

n to “M

ap

g of ch

ara

ct

er da

ta

”.

•

Rev

ise

d the

des

crip

tion

in SC

CNT_

L[d1

4] an

d [06

] of UA

RT c

ommu

nica

-

tion register.

•

Rev

ise

d the

con

nec

tion

dia

gra

m of 1

6 bit

mult

i-pl

ay co

mmun

icat

ion.

•

Add

ed a d

esc

ript

ion t

o al

l sou

nd op

erat

ion m

ode

s of t

he so

und c

ontr

ol

register.

•

Rev

ise

d t

he

item

ized

des

crip

tion

of

Chap

ter

10

“Sou

nd”

.

0.

4.

1.

7

08

/1

0/

20

00

•

Mo

di

fi

ed

th

e d

es

cr

ip

ti

on

of

an

er

ro

r f

la

g f

or

th

e m

ul

ti

-p

la

y c

on

tr

ol

re

gi

st

er

.

•

Mod

ifie

d the d

esc

ript

ion o

f a val

id fla

g for a

ll the D

MA co

ntro

l reg

iste

rs.

•

Add

ed th

e num

ber o

f tra

nsfe

r whe

n 0 is

set f

or th

e DMA

word

cou

nt re

g-

ister.

0.

4.

1.

6

06

/2

6/

20

0

•

Mo

di

fi

ed

th

e

co

nn

ec

ti

on

di

ag

ra

m

of

th

e

mu

lt

i-

pl

ay

ca

bl

e.

•

Add

ed th

e tra

nsi

tion

dia

gram

of th

e mu

lti-

play

comm

uni

cat

ion d

ata

.

•

Mod

ifie

d the

des

crip

tion

of “1

6-Bi

t Mul

ti-p

lay

Comm

uni

cati

on”.

0.

4.

1.

3

05

/2

5/

20

0

•

Ch

an

ge

d t

h

e d

ia

gr

am

in

Sy

st

em

-A

ll

oc

at

ed

Ar

e

a i

n W

or

ki

ng

RA

M,

an

d

deleted “

(T

entative)”.

•

Re

vi

se

d R

OM

re

gi

st

ra

ti

on

da

ta

.

•

Cor

rect

ed the

des

cri

ptio

n of in

tern

al sh

ift cl

ock o

f norm

al SIO

con

trol r

eg-

ister.

•

New

ly ad

ded t

he de

scri

ptio

n of “C

omm

unic

atio

n Cab

le” in

the c

hap

ter of

Communication Functions.

•

Cor

rect

ed Ov

erv

iew of S

cre

en Si

zes fo

r T

ext B

G Scr

een

s in “R

end

erin

g

Functions”.

05

/16

/2

00

0

•

Ad

de

d t

he

di

ag

ra

m o

f Mu

lti

Pl

ay

er

Co

mmu

nic

at

ion

Ca

bl

e c

onn

ec

tio

n.

05

/0

8/

20

0

•

Co

rr

ec

te

d

[S

ou

nd

1

Us

ag

e

No

te

s]

.

•

In 1)

Norm

al Co

mmun

ica

tion

of Co

mmun

icat

ion F

unc

tion

s, me

ntio

ned

not to use a cable.

0.

4.

1.

2

04

/0

6/

20

0

•

Ad

de

d

th

e

d

es

cr

ip

ti

o

n

of

UA

R

T

sy

st

em

c

om

mu

ni

ca

ti

on

.

0.

4.

1.

1

03

/1

0/

20

00

•

Im

pr

ov

ed

th

e

de

sc

ri

pt

io

n

of

in

te

rr

up

t

an

d

mu

lt

ip

le

in

te

rr

up

t

pr

oc

es

s.

•

Impr

ove

d the d

esc

ript

ion o

f sys

tem ca

ll an

d mul

tipl

e sys

tem ca

ll pro

ces

s.

03

/0

8/

20

00

•

Ad

de

d t

he

de

sc

ri

pt

io

n o

f R

OM

re

gi

st

ra

ti

on

da

ta

.

Revision

No.

Date

Revised

Description

xx

G

a

m

e

B

o

y

A

d

v

a

n

c

e

P

r

o

g

r

a

m

i

n

g

M

a

n

u

a

l

M

a

y

2

5

,

2

0

5

AGB-06-0001-002-B13

Released: May 27, 2005

0

.

4

.

1

0

2

/

2

5

/

2

0

•

C

h

a

n

g

e

d t

h

e m

e

t

h

o

d t

o s

p

e

c

i

f

y O

B

J s

i

z

e

.

•

Cor

rect

ed m

isp

rint

s in

the

com

mun

ica

tion

con

trol

reg

iste

r

.

02

/2

4/

20

00

•

Ad

de

d t

he

PW

M s

am

pl

in

g c

yc

le

co

nt

ro

l f

un

ct

io

n.

02

/22

/2

00

0

•

Mo

dif

ied

the

de

sc

rip

tio

n of D

ire

ct S

ou

nd

s, a

nd c

or

re

cte

d re

gi

ste

r R b

it

structure.

0

.

4

.

0

2

/

0

9

/

2

0

•

A

d

e

d

t

h

e

C

o

m

p

l

e

t

e

B

l

o

c

k

D

i

a

g

r

a

m

.

01

/25

/2

00

0

•

Ch

an

ge

d CP

U in

ter

na

l wo

rk

ing

RAM

mem

ory

ca

pa

ci

ty

, an

d c

rea

te

d CP

U

external working RAM.

•

Ch

an

ge

d th

e bit s

tru

ct

ure

s of DM

A con

tro

l reg

is

ter

s.

•

De

le

ted

Inf

rar

ed

Co

mmu

ni

ca

tio

n fu

nc

tio

ns

.

•

Cre

ated t

he in

terr

upt I

ME reg

iste

r

, and c

han

ged t

he bi

t stru

ctur

es of IE

and IF registers.

•

Cha

nge

d th

e nu

mbe

r of

colo

rs t

hat

can

be d

ispl

aye

d to

32,7

68.

•

Cha

nge

d the s

pec

ific

ati

ons o

f Nor

mal Se

rial C

ommu

nic

atio

n (bit w

idt

h,

communication speed)

•

Cha

nge

d th

e spe

cifi

cat

ion

s of M

ulti

SIO C

ommu

nica

tion

(UAR

T sy

stem

).

•

Cha

nge

d the

cen

ter c

oor

dina

te of

OBJ R

ota

tion

to d

ot bo

und

ary

.

•

Ad

de

d UA

RT

sy

ste

m co

mm

un

ica

tio

n fu

nc

tio

n.

0

.

3

.

6

.

3

0

1

/

0

5

/

2

0

•

M

i

n

o

r m

o

d

i

f

i

c

a

t

i

o

n

.

•

Co

rre

ct

ed

BG

Of

fs

et

Re

gis

ter

s

dia

gr

ams

•

Cor

rect

ed the

diag

rams

of Reg

iste

rs for S

etti

ng th

e Dire

ctio

n Par

ame

ters

of BG data.

•

Co

rre

ct

ed d

ia

gra

m of

the

So

un

d 1 D

uty

Cyc

le

.

•

Cor

rect

ed t

he n

ame

of d

05 b

it f

or t

he D

ISPC

NT R

egi

ster

.

•

Ad

de

d t

he

de

sc

rip

tio

n o

f Bi

t ma

p B

G m

od

e.

•

Cor

rect

ed t

he S

IO T

imin

g Ch

art o

f No

rmal

Ser

ial C

ommu

nic

atio

n.

•

Cha

nge

d th

e dia

gram

s and

des

crip

tion

s of th

e So

und C

ontr

ol Re

gis

ters

.

•

Add

ed th

e for

mul

a for

calc

ula

ting

the n

umbe

r of OB

Js th

at ca

n be d

is-

played on 1 line.

0.

3.

6.

2

12

/2

1/

19

99

•

Mi

no

r

mo

di

fi

ca

ti

on

.

(N

um

be

ri

ng

fo

r

it

em

s

P8

1,

P8

2,

P1

49

;

re

fe

re

nc

e

to

chapter removed)

•

D

e

l

e

t

e

d

1

4

.

3

.

Revision

No.

Date

Revised

Description

Nintendo Game Boy Advance Owner's manual

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