NS LP3931 User manual

LP3931
Dual RGB LED Driver with High Current Boost DC-DC
Converter
General Description
The LP3931 is a RGB LED driver with high current boost
DC-DC converter designed for portable wireless applica-
tions. It contains 2 sets of RGB LED drivers that are PWM-
driven with programmable color, intensity and blinking pat-
terns. They additionally feature a FLASH function to support
picture taking with camera-enabled cellular phones.
An efficient magnetic boost DC/DC converter provides the
required bias, operating from a single Li-Ion battery. The
DC/DC converter output voltage is user programmable for
adapting to different LED types and for efficiency optimiza-
tion.
All functions are software controllable through the SPI inter-
face and internal registers.
Features
nHigh Efficiency Programmable 300 mA Magnetic Boost
DC-DC converter
n2 separately controlled PWM RGB LED drivers with
programmable color, brightness, turn on/off slopes and
blinking patterns
nFLASH function with up to 6 outputs, each up to
120 mA
nFunctions software controlled through SPI interface
nAdditional LED on/off and dimming hardware control
nProgrammable low current Standby mode
nLow voltage digital interface down to 1.8V
nSpace efficient 24-pin LLP package
Applications
nGSM Cellular Phones
nWCDMA, CDMA and CDMA2000 Phones
nPHS and PDC Cellular Phone
Typical Application
20117301
August 2004
LP3931 Dual RGB LED Driver with High Current Boost DC-DC Converter
© 2004 National Semiconductor Corporation DS201173 www.national.com

Connection Diagrams and Package Mark Information
24-Lead LLP Package,4x4x0.8mm
NS Package Number NSQAL024
20117303
Bottom View
20117302
Top View
20117304
Package Mark — Top View
Note: The actual physical placement of the package marking will vary from part to part. The package marking “XY” designates
the date code. “UZ” and “TT” are NSC internal codes for die manufacturing and assembly traceability. Both will vary considerably.
Ordering Information
Order Number Package Marking Supplied As
LP3931ISQ LP3931ISQ 1000 units, Tape-and-Reel
LP3931ISQX LP3931ISQ 2500 units, Tape-and-Reel
LP3931
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Pin Description
Pin # Name Type Description
1 G2 Output Open Drain, Green LED2
2 R2 Output Open Drain, Red LED2
3 GND_RGB Ground RGB Driver Ground
4 R1 Output Open Drain, Red LED1
5 G1 Output Open Drain, Green LED1
6 B1 Output Open Drain, Blue LED1
7 GND_BOOST Ground Power Switch Ground
8 SW Output Open Drain, Boost Converter Power Switch
9V
DD2
Power Supply Voltage for Internal Digital Circuits
10 GND2 Ground Ground
11 FB Input Boost Converter Feedback
12 V
REF
Output Internal Reference Bypass Capacitor
13 SO Logic Output SPI Serial Data Out
14 SI Logic Input SPI Serial Data Input
15 SS Logic Input SPI Slave Select
16 SCK Logic Input SPI Clock
17 PWM_LED Input LED Control for On/Off or PWM Dimming
18 NRST Logic Input Low Active Reset Input
19 V
DDIO
Power Supply Voltage for Logic IO Signals
20 RT Input Oscillator Resistor
21 GND3 Ground Ground
22 V
DD1
Power Supply Voltage for Internal Analog Circuits
23 GND1 Ground Ground
24 B2 Output Open Drain, Blue LED2
LP3931
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Absolute Maximum Ratings (Notes 1,
2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
V (SW, FB, R1- 2, G1-2,
B1-2) pins:
Voltage to GND (Notes 3, 4) −0.3V to +7.2V
V
DD1
,V
DD2
,V
DD_IO
−0.3V to +6.0V
Voltage on Logic Pins –0.3V to V
DD_IO
+0.3V, with 6.0V max
I (R1, G1, B1, R2, G2, B2)
(Note 5) 150 mA
I(V
REF
)10µA
Continuous Power Dissipation
(Note 6) Internally Limited
Junction Temperature (T
J-MAX
) 125˚C
Storage Temperature Range −65˚C to +150˚C
Maximum Lead Temperature
(Reflow soldering, 3 times)
(Note 7) 240˚C
ESD Rating (Note 8)
Human Body Model: 2 kV
Machine Model: 200V
Operating Ratings (Notes 1, 2)
V (SW, FB, R1-2, G1-2, B1-2) 3.0V to 6.0V
V
DD1
,V
DD2
(Note 4) 2.65V to 2.9V
V
DD_IO
1.8V to V
DD1,2
Recommended Load Current 0 mA to 300 mA
Junction Temperature (T
J
) Range −40˚C to +125˚C
Ambient Temperature (T
A
) Range
(Note 9) −40˚C to +85˚C
Thermal Properties
Junction-to-Ambient Thermal Resistance (θ
JA
),
SQA24A Package (Note 10) 39˚C/W
Electrical Characteristics (Notes 2, 11)
Limits in standard typeface are for T
J
= 25˚C. Limits in boldface type apply over the operating ambient temperature range
(−40˚C ≤T
J
≤+85˚C). Unless otherwise noted, specifications apply to the LP3931 Typical Application Circuit (pg. 1) with: V
DD1
=V
DD2
=V
DDIO
= 2.775V, C
VDD1
=C
VDD2
=C
VDDIO
= 0.1 µF, C
OUT
=C
IN
= 10 µF, C
VREF
= 0.1 µF, L
1
= 10 µH, R
T
= 82k
(Note 12).
Symbol Parameter Condition Min Typ Max Units
I
DD
Standby Supply Current
(V
DD1
and V
DD2
current)
NSTBY = L (register)
SCK, SS, SI, NRST = H 15µA
No-Load Supply Current
(V
DD1
and V
DD2
current, boost off)
NSTBY = H (reg.)
EN_BOOST = L (reg.)
SCK, SS, SI, NRST = H
170 250 µA
Full Load Supply Current
(V
DD1
and V
DD2
current, boost on)
NSTBY = H (reg.)
EN_BOOST = H (reg.)
SCK, SS, SI, NRST = H
All Outputs Active
1mA
I
DD_IO
V
DD_IO
Standby Supply Current NSTBY = L (reg.)
SCK, SS, SI, NRST = H 1µA
V
DD_IO
Supply Current 1 MHz SCK Frequency
C
L
=50pFatSOPin 20 µA
V
REF
Reference Voltage (Note 13) I (V
REF
)≤1 nA,
Test Purposes Only
1.205
−2
1.23 1.255
+2
V
%
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins (GND1-3, GND_BOOST, GND_RGB).
Note 3: Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.
Note 4: Voltage tolerance of LP3931 above 6.0V relies on fact that VDD1 and VDD2 (2.775V) are available (ON) at all conditions. If VDD1 and VDD2 are not available
(ON) at all conditions, National Semiconductor does not guarantee any parameters or reliability for this device.
Note 5: The total load current of the boost converter should be limited to 300 mA.
Note 6: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ= 160˚C (typ.) and disengages at TJ=
140˚C (typ.).
Note 7: For detailed package and soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe
Package (LLP).
Note 8: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩresistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7.
LP3931
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Electrical Characteristics (Notes 2, 11) (Continued)
Note 9: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 125˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX =T
J-MAX-OP −(θJA xP D-MAX).
Note 10: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 11: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 12: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) are used in setting electrical characteristics.
Note 13: VREF pin (Bandgap reference output) is for internal use only. A capacitor should always be placed between VREF and GND1.
Block Diagram
20117305
LP3931 Block Diagram
LP3931
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Modes of Operation
RESET: In the RESET mode all the internal registers are reset to the default values (Boost output register 3Fh
(5.0V), all other registers 00h). Reset is entered always if input NRST is LOW or internal Power On Reset
is active.
STANDBY: The STANDBY mode is entered if the register bit NSTBY is LOW and Reset is not active. This is the low
power consumption mode, when all circuit functions are disabled. Registers can be written in this mode and
the control bits are effective immediately after power up.
STARTUP: INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (V
REF
, Bias, Oscillator etc.).
To ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine.
Thermal shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal
shutdown event is present.
BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the boost output is
raised in PFM mode during the 10 ms delay generated by the state-machine. The Boost startup is entered
from Internal Startup Sequence if EN_BOOST is HIGH or from Normal mode when EN_BOOST is written
HIGH.
NORMAL: During NORMAL mode the user controls the chip using the Control Registers. The registers can be written
in any sequence and any number of bits can be altered in a register in one write.
20117306
LP3931
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Logic Interface Characteristics
(1.8V ≤V
DD_IO
≤V
DD1,2
)
Symbol Parameter Conditions Min Typ Max Units
LOGIC INPUTS SS, SI, SCK, PWM_LED
V
IL
Input Low Level 0.5 V
V
IH
Input High Level V
DD_IO
− 0.5 V
I
I
Logic Input Current −1.0 1.0 µA
f
SCK
Clock Frequency V
DD_IO
= 2.775V 13 MHz
LOGIC INPUT NRST
V
IL
Input Low Level 0.5 V
V
IH
Input High Level 1.5 V
I
I
Logic Input Current −1.0 1.0 µA
t
NRST
Reset Pulse Width 10 µs
LOGIC OUTPUT SO
V
OL
Output Low Level I
SO
=3mA 0.3 0.5 V
V
OH
Output High Level I
SO
=−3mA V
DD_IO
− 0.5 V
DD_IO
− 0.3 V
SPI Interface
LP3931 is compatible with the SPI serial bus specification
and it operates as a slave. The transmission consists of
16-bit Write and Read Cycles. One cycle consists of 7 Ad-
dress bits, 1 Read/Write (R/W) bit and 8 Data bits. R/W bit
high state defines a Write Cycle and low defines a Read
Cycle. SO output is normally in high-impedance state and it
is active only when Data is sent out during a Read Cycle. A
pull-up or pull-down resistor may be needed in SO line if a
floating logic signal can cause unintended current consump-
tion in the input where SO is connected. The Address and
Data are transmitted MSB first. The Slave Select signal SS
must be low during the Cycle transmission. SS resets the
interface when high and it has to be taken high between
successive Cycles. Data is clocked in on the rising edge of
the SCK clock signal, while data is clocked out on the falling
edge of SCK.
20117307
SPI Write Cycle
20117308
SPI Read Cycle
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SPI Interface (Continued)
20117309
SPI Timing Diagram
SPI Timing Parameters
V
DD1,2
=V
DD_IO
= 2.775V
Symbol Parameter Limit Units
Min Max
1 Cycle Time 70 ns
2 Enable Lead Time 35 ns
3 Enable Lag Time 35 ns
4 Clock High Time 35 ns
5 Clock Low Time 35 ns
6 Data Setup Time 0 ns
7 Data Hold Time 20 ns
8 Data Access Time 0 20 ns
9 Disable Time 10 ns
10 Data Valid 20 ns
11 Data Hold Time 0 ns
12 SS Inactive Time 10 ns
Note: Data guaranteed by simulation.
Magnetic Boost DC/DC Converter
The LP3931 Boost DC/DC Converter generates a 4.1V–5.3V supply voltage for the LEDs from single Li-Ion battery (3V…4.5V).
The output voltage is controlled with an 8-bit register in 9 steps. The converter is a magnetic switching PWM mode DC/DC
converter with a current limit. The converter switching frequency is 1 MHz when timing resistor RT is 82 kΩ.
The topology of the magnetic boost converter is called CPM control, current programmed mode, where the inductor current is
measured and controlled with the feedback. The user can program the output voltage of the boost converter. The control changes
the resistor divider in the feedback loop.
The following figure shows the boost topology with the protection circuitry. Three different protection schemes are implemented:
1. Over voltage protection, limits the maximum output voltage
— Keeps the output below breakdown voltage.
— Prevents boost operation if battery voltage is much higher than desired output.
2. Over current protection, limits the maximum inductor current
— Voltage over switching NMOS is monitored; too high voltages turn the switch off.
3. Duty cycle limiting, done with digital control.
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Magnetic Boost DC/DC Converter (Continued)
Boost Converter Topology
20117310
Magnetic Boost DC/DC Converter Electrical Characteristics
Symbol Parameter Conditions Min Typ Max Units
I
LOAD
Load Current 3.0V ≤V
IN
≤4.5V
V
OUT
(FB) = 5V 0 300 mA
V
FB
Voltage Accuracy at FB Pin
(Boost Converter Output
Voltage Accuracy)
1mA≤I
SW
≤300 mA
3.0V ≤V
IN
≤V (FB) – 0.5
V(FB)=5V
−5 +5 %
Voltage at FB Pin
(Boost Converter Output
Voltage)
1mA≤I
SW
≤300 mA
3.0V <V
IN
<5V +
V
(SCHOTTKY)
5V
1mA≤I
SW
≤300 mA
V
IN
>5V+V
(SCHOTTKY)
V
IN
–V
(SCHOTTKY)
V
RDS
ON
Switch ON Resistance V
DD1,2
= 2.775V, I
SW
=
0.5A 0.4 0.7 Ω
f
PWF
PWM Mode Switching
Frequency
RT=82kΩ1 MHz
Frequency Accuracy 2.65 ≤V
DD1,2
≤2.9 −6 ±3+6
%
RT=82kΩ−9 +9
t
STARTUP
Startup Time From NSTBY and
EN_BOOST
0-
>1 transition
25 ms
I
CL_OUT
SW Pin Current Limit 670 800 915 mA
530 995
Boost Standby Mode
User can set the Boost Converter to STANDBY mode by writing the register bit EN_BOOST low. When EN_BOOST is written
high, the converter waits for 10 ms for the internal voltages and currents to stabilize and then starts for 10 ms in PFM mode and
then goes to PWM mode.
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Boost Output Voltage Control
User can control the boost output voltage by 8-bit boost
output register as follows:
Register 0DH
Boost Output [7:0]
BOOST Output Voltage
(typical)
0000 0000 4.15
0000 0001 4.30
0000 0011 4.40
0000 0111 4.55
0000 1111 4.70
0001 1111 4.85
0011 1111 5.00 Default
0111 1111 5.15
1111 1111 5.30
Boost Output Voltage Control
20117311
Boost Converter Typical Performance Characteristics V
IN
= 3.6V, V
OUT
= 5.0V if not
otherwise stated.
20117312
Boost Converter Efficiency
20117313
Boost Frequency vs RT Resistor
20117314
Battery Current vs Voltage
20117320
Battery Current vs Voltage
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