nvent Schroff 14579-040 User manual

18 slot PXIe System
User‘s Manual
Product Number:
14579-040
Doc-No. 63972-381_R1.5 January 2021

Impressum:
Schroff GmbH

Langenalber Str. 96 - 100
75334 Straubenhardt, Germany
The details in this manual have been carefully compiled and
checked - supported by certified Quality Management System
to EN ISO 9001/2000
The company cannot accept any liability for errors or misprints.
The company reserves the right to amendments of technical
specifications due to further development and improvement of
products.
Copyright2021
All rights and technical modifications reserved.
R1.0 July 2019 Preliminary release
R1.1 February 2020 Manual supplemented
R1.2 March 2020 Minor corrections
R1.3 April 2020 Front panel added
R1.4 October 2020 Updated
R1.5 January 2021 Clock specifications added

14579-040 (PXIe System)
R1.5, January 2021 I
1 Safety ....................................................................................................................... 1
1.1 Safety Symbols used in this document.............................................................................. 1
1.2 General Safety Precautions ............................................................................................... 1
1.3 References and Architecture Specifications...................................................................... 2
2 Product Overview ..................................................................................................... 3
2.1 Key features ...................................................................................................................... 3
2.2 System Overview............................................................................................................... 4
3 18 Slot PXIe Backplane (23007-518) .......................................................................... 5
3.1 Backplane Topology .......................................................................................................... 6
3.2 PCIe-to-PCI bridge ............................................................................................................. 7
3.3 PCIe Switch........................................................................................................................ 7
3.4 System Synchronisation Clocks ......................................................................................... 8
3.4.1 Clock specifications............................................................................................ 9
3.5 Schroff PXIe Chassis Management Module (CMM) ........................................................ 10
3.5.1 Chassis status LED............................................................................................ 11
3.6 PXI Trigger Bus ................................................................................................................ 12
3.7 Power Supply................................................................................................................... 13
3.7.1 Available electrical power................................................................................ 14
3.7.2 Per slot power.................................................................................................. 15
3.7.3 Grounding/Earthing ......................................................................................... 15
3.8 Power-on behaviour........................................................................................................ 16
3.9 Voltage monitoring ......................................................................................................... 16
4 Cooling ................................................................................................................... 17
4.1 Temperature Settings...................................................................................................... 18
4.1.1 Maximum cooling ............................................................................................ 18
5 System Controller ................................................................................................... 19
5.1 Fan Speed and Trigger Bridge settings ............................................................................ 20
5.2 General Installation Guidelines ....................................................................................... 21
5.2.1 Unpacking ........................................................................................................ 21
5.2.2 Ensuring Proper Airflow................................................................................... 21
5.3 Initial Operation .............................................................................................................. 21
6 Service.................................................................................................................... 22
6.1 Technical support and Return for Service Assistance ..................................................... 22
6.2 Scope of Delivery............................................................................................................. 23
6.3 Accessories...................................................................................................................... 23
6.4 Spare Parts ...................................................................................................................... 23
7 Technical Data ........................................................................................................ 24
8 Dimensions............................................................................................................. 25

14579-040 (PXIe System)
II R1.5, January 2021

14579-040 (PXIe System)
R1.5, January 2021 Safety 1
1 Safety
The intended audience of this User’s Manual is system integrators and hardware/software
engineers.
1.1 Safety Symbols used in this document
1.2 General Safety Precautions
• Service personnel must know the necessary electrical safety, wiring and connection
practices for installing this equipment.
• Install this equipment only in compliance with local and national electrical codes.
Hazardous voltage!
This is the electrical hazard symbol. It indicates that there are dangerous voltages inside the
Shelf.
Caution!
This is the user caution symbol. It indicates a condition where damage of the equipment or
injury of the service personnel could occur. To reduce the risk of damage or injury, follow all
steps or procedures as instructed.
Danger of electrostatic discharge!
Static electricity can damage sensitive components in a system. To avoid damage, wear ESD
wrist straps or at regular intervals touch blank enclosure parts.
Warning!
Voltages over 60 VDC can be present in this equipment. This equipment is intended to be 
accessed, to be installed and maintained by qualified and trained service personnel only.
This equipment is designed in accordance with protection class 1!
It must therefore be operated only with protective GND/earth connection!

14579-040 (PXIe System)
2Safety R1.5, January 2021
1.3 References and Architecture Specifications
• PXI-5 (PCI EXPRESS eXtensions for Instrumentation)
• User Manual Schroff embedded Controller, Ord.-No: 63972-389
• User Manual PXIe Chassis Management (CMM), Ord.-No: 63972-391

14579-040 (PXIe System)
R1.5, January 2021 Product Overview 3
2 Product Overview
2.1 Key features
• Shielded 4 U Schroff ratiopacPRO-air case with mounting brackets for 19“ rack mounting
and front handles and tip-up feet for desktop use
• 84 HP / 18 slot front card cage for 3 U boards
• 18 slot 3 U backplane with:
- 1 PXIe system slot 4 - 12 HP
- 1 PXIe timing slot 4 HP
- 16 PXI Express Hybrid slots 4 HP accepting PXIe modules according to the PXI Express
(PXI-5) standard as well as PXI, CompactPCI, CompactPCI Express modules
• BNC connectors for 10 MHz clock input/output at the rear side
• Integrated power supply (1200 W) with wide range input
• Power input module with IEC 60320-C14 connector, mains/line switch, mains/line filter
and fuses
• 3x 120 mm Fans for the active cooling of the boards and the power supply, controlled and
monitored by the Chassis Monitoring Module (CMM)
• Power switch with chassis status LEDs at the front side
The system 14579-040
is described as an example below in this manual.
The system can be modified with various backplane configurations.
All pictures in this manual may differ from the latest series.

14579-040 (PXIe System)
4Product Overview R1.5, January 2021
2.2 System Overview
The 4 U case is based on the Schroff ratiopacPRO-air system with EMC shielding. The 3 U card
cage provides 1 system slot (4 - 12 HP), 1 timing slot (4 HP) and 16 peripheral slots (4 HP).
The lower guide rails of the card cage are equipped with ESD clips.
Figure 1: Front and Rear View
1PS-ON Switch with Chassis Status LEDs 7DSUB-9 Connector, female, Inhibit and voltage
monitoring
2Filler Panels 4/8 HP System Slot Extension 8BNC Connectors 10 MHz REF clock in/out
3PXIe Backplane 9Fans/Air Outlet
4Air Intake 10 Fan Speed Selector
5Power Input Module 11 Inhibit Mode Selector
6Ground stud (M5)

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R1.5, January 2021 18 Slot PXIe Backplane (23007-518) 5
3 18 Slot PXIe Backplane (23007-518)
The PXIe backplane provides:
•1PXIesystemslot
•1PXIetimingslot
• 16 PXIe Hybrid slots
- accepting CompactPCI, PXI, CompactPCI Express, and PXIe modules
• 2 PCIe-to-PCI high performance bridges
- utilize a single PCI segment for the hybrid slots
- designed to the PCI Express-to-PCI Bridge Specification 1.0 that enables applications to
migrate legacy parallel PCI bus interfaces to the advanced serial PCI Express
- each bridge is equipped with a single lane PCI Express port and a parallel bus segment
supporting the conventional PCI operation for up to eight PCI peripheral devices con-
currently.
- Primary Bus: x1 PCI Express Base Specification R1.1 compliant
- Secondary Bus: 33 MHz/32 bit PCI Local Bus Specification R3.0 compliant
• All PXIe hybrid slots with 32 bit 33 MHz PCI interface.
• 1 PXIe clock module
- generates and controls PXI specific high accuracy clocks and trigger signals.
• 4 ultra-high performance PCIe switches that operates with up to Gen 3 speeds.
• All PXIe hybrid and the timing slots have an x4 PCIe link providing a maximum data band-
width of 4 GB/s each.

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618 Slot PXIe Backplane (23007-518) R1.5, January 2021
3.1 Backplane Topology
Figure 2: Backplane Topology

14579-040 (PXIe System)
R1.5, January 2021 18 Slot PXIe Backplane (23007-518) 7
3.2 PCIe-to-PCI bridge
The Schroff PCIe-to-PCI Bridge is a high performance bridge designed to the PCI Express-to-
PCI Bridge Specification 1.0 that enables applications to migrate legacy parallel PCI bus
interfaces to the advanced serial PCI Express.
The bridge module is equipped with a single lane PCI Express port and a parallel bus segment
supporting the conventional PCI operation for up to eight PCI peripheral devices concurrently.
Primary Bus: x1 PCI Express Base Specification R1.1 compliant
Secondary Bus: 33 MHz/32 bit PCI Local Bus Specification R3.0 compliant
3.3 PCIe Switch
The Schroff PCIe Switch is a 24-lane, 6-port, PCIe Gen 3 switch device that enables users to
connect a PCIe host to respective endpoints via a fully transparent, high-bandwidth, non-
blocking peer-to-peer interface. The default configuration with a x4 upstream port to the
host supports up to five independent x4 down-stream clients.
Port Configuration: 1 x4 upstream port, 5 x4 downstream ports
Compatibility: PCI Express Base Specification R3.0, PCI Express Base Specification R2.0, PCI
Express Base Specification R1.0a/1.1

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3.4 System Synchronisation Clocks
Acc. to the PXI specifications, the Schroff PXIe system routes the PXI_CLK10 to slot 1-18 and
PXIe_CLK100 and PXIe_SYNC100 to the peripheral slots 2-18.
PXI_CLK10 is also routed to the external BNC connector 10 MHz REF OUT at the chassis rear
side.
All clocks/timing signals are generated by the PXI-5 compliant Schroff PXIe Clock Module.
When a 10 MHz reference clock signal is present at the System Timing Slot or the rear panel
connector 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are phase-locked to
this reference clock signal according to the following table:
The source for the reference signal is selected automatically, if a 10 MHz reference clock is
present at the System Timing Slot and the external clock input, the signal from the System
Timing Slot is selected.
Mode System Timing Slot Ext. 10 MHz REF In Backplane Clock Module
110 MHz clock present 10 MHz clock present 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are
phase-locked to reference clock signal from System Timing Slot
110 MHz clock present -10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are
phase-locked to reference clock signal from System Timing Slot
2-10 MHz clock present 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are
aphase-locked to reference clock signal from Ext. 10 MHz REF In
3- - 10 MHz REF IN, PXI_CLK10, PXIe_CLK100 and PXIe_SYNC100 are
generated by the Clock Module
PXI_CLK10
PXIe_CLK100
PXIe_SYNC100
XO
10 MHz
10 MHz
REF IN
PLL Buffer
Buffer
Buffer
Auto-mode:
1->2
2
I2C-Control
10 MHz
REF OUT
Slot 1 Slot 2 Slot n
Schroff PXIe Clock Module
3
1
Timing Slot
-> 3

14579-040 (PXIe System)
R1.5, January 2021 18 Slot PXIe Backplane (23007-518) 9
3.4.1 Clock specifications
For all specifications not mentioned in the tables below refer to the PXI-1 und PXI-5 PXIe
Hardware specifications
PXI_CLK10
Maximum slot to slot time skew 500 ps
Note: PXI-5 spec specifies 1 ns
Frequency accuracy ±25 ppm max (guaranteed over the operating temperature range) 
Note: PXI-5 spec specifies ±100 ppm
Maximum jitter 5 ps RMS phase jitter (10 Hz – 10 MHz range)
Duty factor 45 % to 55 %
Unloaded signal swing 3.3 V ±0.3 V
Values above valid for PXI standard products. Optimized parameters are possible on
request (Jitter ≤2 ps, Accuracy 2 ppm, slot-to-slot skew 100 ps)
PXIe_CLK100 and PXIe_SYNC100
Maximum slot to slot time skew 80 ps
Note: PXI-5 spec specifies 200 ps
Frequency accuracy ±25 ppm max (guaranteed over the operating temperature range) 
Note: PXI-5 spec specifies ±100 ppm
Maximum jitter 5 ps RMS phase jitter (10 Hz – 20 MHz range)
Duty factor 45 % to 55 %
Absolute differential voltage when each line pair is ter-
minated with a 50 load to 1.30 V (or Thevenin equiva-
lent)
500 mV to 950 mV
Values above valid for PXI standard products. Optimized parameters are possible on
request (Jitter ≤2 ps, Accuracy 2 ppm)
External 10 MHz Reference In
Frequency 10 MHz ±50 ppm
Input amplitude 200 mV to 5 V, square wave or sine wave
Maximum jitter introduced by backplane 1 ps RMS phase jitter (10 Hz – 10 MHz range)
Rear panel BNC connector input impedance 50 ±5 
External 10 MHz Reference Out
Frequency accuracy ±25 ppm max.
(guaranteed over the operating temperature range)
Maximum jitter 5 ps RMS phase jitter (10 Hz – 10 MHz range)
Output amplitude min. 1.2 Vpp square wave into 50 
min. 2.9V unloaded
Output impedance 50 ±5 

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10 18 Slot PXIe Backplane (23007-518) R1.5, January 2021
3.5 Schroff PXIe Chassis Management Module (CMM)
The Schroff PXIe Chassis Management Module (CMM) allows access from the operating
system to all important chassis functions. The CMM provides an I2C interface which is
connected to backplane SMB (system slot pins XP3-a3, -b3).
The CMM:
• Monitors all chassis voltage levels
• Monitors and control the power supply
• Monitors and control the fans
• Monitors the chassis temperatures (inlet and outlet)
• Controls SYNC100 frequency from clock module
• Controls the PXI trigger bridges
• Controls the chassis status LEDs
I2C interface
(to SMB on backplane
pins XP3-a3, -b3)
Backplane voltages
(5 V aux, 5 V, 3,3 V, +12 V,-12 V)
Temperature Sensors (4x)
Select “PS_ON” source
“PS_ON” from system slot source
“PS_ON” external source
4x “PS_ON” output
(for different PSU modules)
FAN PWM (fan speed control)
6x FAN Tacho
“AC_OK” from PSU
Chassis status LEDs
I2C
Trigger Bridge1
Clock Module
CMM module
μC
Default I2C
address 0x58h
Trigger Bridge2
Trigger Bridge3
Trigger Bridge4
To use the CMM‘s full capabilities, you have to access the CMM‘s I²C register with the
Schroff Embedded Controller or another appropriately configured and programmed third
party system controller.
For further information see CMM User Guide, Ord--No: 63972-391

14579-040 (PXIe System)
R1.5, January 2021 18 Slot PXIe Backplane (23007-518) 11
3.5.1 Chassis status LED
The power switch on the front of the chassis has two LEDs (red and white).
The table below shows the chassis states and corresponding LED behavior.
Chassis state Notification LED behavior
Chassis is off Both LED OFF
Chassis powered and operating properly Solid white
Air intake temperature is above 55°C Flashing white
Power supply DC outputs not within
acceptable voltage range
Flashing red
One of the chassis fans failed Solid red

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3.6 PXI Trigger Bus
The PXIe chassis trigger bus is divided into 3 isolated trigger bus segments with 8 trigger lines
each.
• Trigger segment 1 covers slot 1 through 6
• Trigger segment 2 covers slot 7 through 12
• Trigger segment 3 covers slot 13 through 18
Through the PXI trigger bridge, each trigger line of a segment can be individually routed in
either direction to the other segment.
The trigger bridges are controlled by the CMM.
1234678
5
HH
10 11 12
9
HH
Trigger Segment IBus
PXI Trigger Bridge
Trigger Segment IBus I
CMM
Chassis Manager
I²C
HHH
16 17 18
HH
PXI Trigger Bridge
Trigger Segment IBus II
H
13 14 15
HHH
I²C
HHHH
By default the 3 trigger bus segments are isolated, the trigger bridges are disabled. To
enable the trigger bridges and set the direction of the routing, you have to access the
CMM‘s I²C register with the Schroff Embedded Controller or another appropriately
configured and programmed system controller.
For further information see CMM User Guide 63972-391

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3.7 Power Supply
The PXIe system is powered by a 1200 W power supply with wide range input (100 - 240 VAC).
The power input is provided by an AC mains/line module with IEC 60320-C14 connector,
integrated mains/line fuses and line filter.
The fuse rating is 10 A slow blow (T10AH250V).
Figure 3: AC mains/line module
Table 1: Data AC Power Supply
e
Hazardous voltage!
Parts of the power supply may be exposed with hazardous voltage. Always remove mains/
line connector before carry out any assembly work.
Caution!
Your system has not been provided with a AC power cable. Purchase an AC power cable that
is approved for use in your country. The AC power cable must be rated for the product and
for the voltage and current marked on the product's electrical ratings label. The voltage and
current rating of the cable should be greater than the ratings marked on the product.
12309010
1Fuse holder 3AC Connector (IEC60320-C14)
2Mains/line switch
Input voltage nominal 100 - 240 VAC
Mains Frequency 50 / 60 Hz
Power (max.) 1200 W
Output Voltage
+3.3 V
+5.0 V
+5.0 V Aux
+12.0 V
-12.0 V
Current
80 A
36 A
2 A
40 A
20 A
Load Regulation
±2 %
±2 %
-
±2 %
±2 %
Ripple
±50 mV
±50 mV
±50 mV
±100 mV
±100 mV


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3.7.1 Available electrical power
The input current of the chassis is limited to 10 A. This results in an available PSU output
power at the following nominal AC input voltages:
• 100 V --> 720 W
• 115 V --> 840 W
• 230 V --> 1060 W
The power for the fans and system modules is already deducted in the calculation and the
diagram below.
400
500
600
700
800
900
1000
1100
1200
240 230 220 210 200 190 180 170 160 150 140 130 120 110 100 90
Output Power PSU [W]
Input Voltage [VAC]
Derang Output Power PSU

14579-040 (PXIe System)
R1.5, January 2021 18 Slot PXIe Backplane (23007-518) 15
3.7.2 Per slot power
The table below shows the maximum available electrical power per slot.
Please note:
• All current carrying backplane pins must be used by the boards
• The average cooling capacity of the PXIe chassis is 50 W per slot
•Max.PSUpower
3.7.3 Grounding/Earthing
The PXIe system provides an additional ground terminal at the rear side. If required, an
additional protective connector can be connected to the bolt.
5 V 3.3 V +12 V -12 V 5 Vaux max power per
slot
PXI Express System
Controller Slot
10.5 A 10.5 A 21 A 0 A 1.5 A 320 W
PXI Express Peripheral Slot 0 A 4.5 A 3 A 0 A 1.5 A 61 W
Hybrid Slot 12 A 19.5 A 4.5 A 1.5 A 1.5 A 312 W
PXI-1 Peripheral Slot 12 A 19.5 A 4.5 A 1.5 A 1.5 A 312 W
Max PSU current per
voltage
36 A 80 A 40 A 20 A 2 A
Caution!
The unit is designed in accordance with protection class 1! It must therefore be operated
with protective earth/GND connection. Use only a three conductor AC power cable with a
protective earth conductor that meets the IEC safety standards!

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16 18 Slot PXIe Backplane (23007-518) R1.5, January 2021
3.8 Power-on behaviour
The power-on behaviour depends on the setting of the inhibit mode switch at the rear panel.
When the inhibit mode switch is set to "DEF", the CMM controls the power supply inhibit, the
chassis can be powered by pushing the power button at the left front side.
When the inhibit mode switch is set to 'MAN', the chassis boots when AC-power is applied,
as long as Pin 5 at the DSUB connector is not connected to GND.
3.9 Voltage monitoring
The female DSUB-9 connector allows remote monitoring of the system voltages.
INHIBIT MODE
DEF MAN
FAN SPEED
AUTO MAX
1 GND
2 +5 V
3 not used
4 +3.3 V
5 Inhibit
6 +12 V
7 not used
8 -12 V
9 GND
1
59
6
VOLTAGE MON
Please note the following:
In order to ensure a proper function of the DEF and MAN settings, the BIOS settings in the
embedded controller must be adjusted.
DEF Mode:
- Set BIOS Power Loss Control to "Remain Off".
MAN Mode:
- Set BIOS Power Loss Control to "Turn On".
For further information see the embedded Controller User Guide, Ord.-No: 63672-389