NXP Semiconductors Layerscape FRWY-LS1046A User manual

Layerscape FRWY-LS1046A Board Reference
Manual
Supports FRWY-LS1046A Board Revision B
NXP Semiconductors Document identifier: FRWY-LS1046ARM
Reference Manual Rev. 1, 05/2020

Contents
Chapter 1 FRWY-LS1046A Overview....................................................................3
1.1 Acronyms and abbreviations..................................................................................................... 3
1.2 Related documentation..............................................................................................................4
1.3 Block diagram............................................................................................................................5
1.4 Board features...........................................................................................................................6
1.5 Board top/bottom views.............................................................................................................9
Chapter 2 FRWY-LS1046A Functional Description............................................. 12
2.1 Power supplies........................................................................................................................ 12
2.1.1 Primary power supply................................................................................................................13
2.1.2 Secondary power supplies........................................................................................................ 14
2.1.3 Power supply sequence............................................................................................................ 16
2.1.4 VDD current/power measurement.............................................................................................17
2.2 Clocks......................................................................................................................................18
2.3 DDR interface..........................................................................................................................19
2.4 SerDes interface......................................................................................................................21
2.4.1 Ethernet interface......................................................................................................................22
2.4.2 M.2 PCIe slots...........................................................................................................................23
2.5 USB interface ......................................................................................................................... 23
2.6 IFC interface............................................................................................................................25
2.6.1 QSPI NOR flash memory.......................................................................................................... 25
2.6.2 NAND flash memory..................................................................................................................26
2.7 SDHC interface........................................................................................................................26
2.8 UART interface........................................................................................................................27
2.9 Serial peripheral interface........................................................................................................28
2.10 MikroBUS socket...................................................................................................................30
2.11 I2C interface.......................................................................................................................... 31
2.12 JTAG header......................................................................................................................... 33
2.13 GPIOs....................................................................................................................................34
2.14 Interrupt handling...................................................................................................................36
2.15 Temperature measurement...................................................................................................37
2.16 DIP switch..............................................................................................................................38
2.17 LEDs......................................................................................................................................39
2.18 System reset..........................................................................................................................39
Appendix A Revision History................................................................................41
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Chapter 1
FRWY-LS1046A Overview
The Layerscape® LS1046A Freeway (FRWY-LS1046A) board is a high-performance development platform that supports the
QorIQ® LS1046A architecture processor capable of supporting more than 32000 CoreMark® performance. The FRWY-LS1046A
board supports the QorIQ LS1046A processor, onboard DDR4 memories, multiple Gigabit Ethernet ports, USB 3.0 ports, M.2
Key-E slots for Wi-Fi, and expansion board options via a mikroBUS™ socket.
The FRWY-LS1046A board comes preloaded with Layerscape software development kit (LSDK) image. The board is lead-free
and RoHS-compliant.
Following are orderable part numbers for the board:
• FRWY-LS1046A-TP
• FRWY-LS1046A-AC
• FRWY-LS1046A-PA
This document provides detailed information about FRWY-LS1046A board interfaces, power supplies, clocks, DIP switch, and
LEDs.
1.1 Acronyms and abbreviations
The table below lists and explains the acronyms and abbreviations used in this document.
Table 1. Acronyms and abbreviations
Term Description
CD Card detect
CTS Clear to send
DDR Double data rate
DIP Dual inline package
DQS Data strobe
DUT Device under test
ECC Error correcting code
EMI Ethernet management interface
eSDHC Enhanced secure digital host controller
GIC Generic interrupt controller
GPIO General purpose input/output
I2C Inter-integrated circuit
IFC Integrated flash controller
JTAG Joint Test Action Group (IEEE® Standard 1149.1™)
MAC Media access control
MT/s MegaTransfers/second
NFC Near field communication
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Table 1. Acronyms and abbreviations (continued)
Term Description
PBL Pre-boot loader
PLL Phase-locked loop
PMIC Power management integrated circuit
POR Power-on reset
PWM Pulse width modulation
QSGMII Quad serial gigabit media independent interface
QSPI Quad serial peripheral interface
RCW Reset configuration word
RTC Real-time clock
RTS Request to send
SDHC Secure digital host controller
SDRAM Synchronous dynamic random-access memory
SerDes Serializer/deserializer
SPD Serial presence detect
SPI Serial peripheral interface
UART Universal asynchronous receiver/transmitter
USB Universal serial bus
WP Write protect
1.2 Related documentation
The table below lists and explains the additional documents and resources that you can refer to for more information on the
FRWY-LS1046A. Some of the documents listed below may be available only under a non-disclosure agreement (NDA). To
request access to these documents, contact your local field applications engineer (FAE) or sales representative.
Table 2. Related documentation
Document Description Link / how to access
Layerscape FRWY-
LS1046A Board Getting
Started Guide
Describes the FRWY-LS1046A board settings and explains
steps to set up and boot the board
FRWY-LS1046AGSG.pdf
Layerscape FRWY-
LS1046A Board Errata
Describes known errata and workarounds for the FRWY-
LS1046A board
Contact FAE / sales
representative
QorIQ LS1046A Product
Brief
Provides a brief overview of the LS1046A processor LS1046APB.pdf
QorIQ LS1046A Data Sheet Provides information about LS1046A electrical characteristics,
hardware design considerations, and ordering information
LS1046A.pdf
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Table 2. Related documentation (continued)
Document Description Link / how to access
QorIQ LS1046A Reference
Manual
Provides a detailed description about the QorIQ LS1046A
multicore processor and its features, such as memory map,
serial interfaces, power supply, chip features, and clock
information
LS1046ARM.pdf
QorIQ LS1046A Chip Errata Lists the details of all known silicon errata for the LS1046A Contact FAE / sales
representative
QorIQ LS1046A Design
Checklist (AN5252)
This document provides recommendations for new designs
based on the LS1046A. This document can also be used to
debug newly designed systems by highlighting those aspects of
a design that merit special attention during initial system startup.
AN5252.pdf
Layerscape Software
Development Kit User
Guide
This document describes how to work with LSDK, which is a
complete Linux kit for NXP QorIQ Arm-based SoCs and the
reference and evaluation boards available for them.
LSDKUG.pdf
CodeWarrior Development
Studio for QorIQ LS series -
ARM V8 ISA, Targeting
Manual
This manual explains how to use the CodeWarrior Development
Studio for QorIQ LS series - ARM V8 ISA product.
CWARMv8TM.pdf
CodeWarrior TAP Probe
User Guide
Provides details of CodeWarrior® TAP, which enables target
system debugging through a standard debug port (usually JTAG)
while connected to a developer workstation through Ethernet or
USB
CWTAPUG.pdf
1.3 Block diagram
The figure below shows the FRWY-LS1046A block diagram.
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Figure 1. FRWY-LS1046A block diagram
1.4 Board features
The table below describes the features of the FRWY-LS1046A.
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Table 3. FRWY-LS1046A features
Board feature Processor feature used Description
Processor QorIQ LS1046A processor
For details on the LS1046A processor,
see QorIQ LS1046A Reference Manual .
NOTE
DDR One 32-/64-bit DDR4 SDRAM
memory controller with ECC
• Supports data rates of up to 2133 MT/s
• Supports 64-bit data bus
• Supports five onboard 512 Mbit x16 discrete memory
modules (eight data byte lanes + ECC)
• Supports double-bit error detection and single-bit error
correction ECC (8-bit check word across 64-bit data)
• Supports single chip select
SerDes Two SerDes modules (SerDes1 and
SerDes2), each having four lanes
with speeds of up to 10 Gbit/s
SerDes1:
• Lane 2: Supports a QSGMII PHY, provides four 1.25
GbE ports
SerDes2:
• Lane 1: Supports a PCIe x1 (Gen 1/2/3) M.2 Key-E slot
for 1630/2230 Wi-Fi module
• Lane 3: Supports a PCIe x1 (Gen 1/2/3) M.2 Key-E slot
for 1630/2230 Wi-Fi module
Ethernet QSGMII interface • Supports four 1G/100M/10BaseT Ethernet ports through
two 1x2 RJ45 connectors with link and activity status
USB 3.0 Two USB 3.0 controllers (USB1 and
USB2) with integrated PHYs
• Supports super-speed (5 Gbit/s), high-speed (480
Mbit/s), full-speed (12 Mbit/s), and low-speed (1.5 Mbit/s)
operations
• Two USB 3.0 ports are configured as host with a 1x2
USB Type A connector
IFC 2.0 Integrated flash controller (NOR,
NAND)
• 64 MB onboard QSPI NOR flash memory (1.8 V) - as
boot source
• 4 Gbit (512 Mbit x 8) SLC NAND flash memory (1.8 V)
with ECC support
SDHC One enhanced secure digital host
controller (eSDHC)
• Supports a micro-SDHC connector for connecting an
external micro-SD 3.0 card
• Operates at 3.3 V
UART Two DUART modules (DUART1 and
DUART2), each containing two
UARTs
DUART1:
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Table 3. FRWY-LS1046A features (continued)
Board feature Processor feature used Description
• UART1 is routed to USB-UART bridge and supports USB
port to access the serial port as console, requires a
jumper to be placed on a header
• UART1 can be used without flow control on an
expansion header, requires the jumper to be removed
from the header
• UART3 can be used to interface with a click board
plugged-in into mikroBUS socket
DUART2:
• UART2 can be used with/without flow control on an
expansion header
• UART4 can be used on the same expansion header
SPI One serial peripheral interface (SPI) • Connects to a click board plugged-in into mikroBUS
socket using PCS0 (3.3 V)
• Supports SPI expansion header using PCS[1:3] (3.3 V)
I2C Three I2C controllers (I2C1, I2C3,
and I2C4)
• I2C1: Controls all system devices and can be accessed
remotely through an I2C expansion header (I2C1)
• I2C3: Can be accessed remotely through an I2C
expansion header (I2C3)
• I2C4: Can be accessed remotely through an I2C
expansion header (I2C4)
Power supply • 12 V input power from DC input adapter
• 1/0.9 V for core VDD, USB_SVDD, USB_SDVDD, and
SVDD
• 1.2 V for DDR4 G1VDD
• 0.6 V for DDR4 VTT/VREF
• 2.5 V for DDR4 VPP
• 3.3 V for DVDD
• 3.3 V for EVDD
• 3.3 V for USB_HVDD
• 1.8 V for OVDD and LVDD
• 1.35 V for XVDD
• 2.5 V for TVDD
• 1.8 V / GND for TA_PROG_SFP (GPIO-controlled)
• 1/0.9 V for TA_BB_VDD
• 2.5 V for QSGMII PHY VDD25, VDD25A
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Table 3. FRWY-LS1046A features (continued)
Board feature Processor feature used Description
• 2.1 V for QSGMII PHY core
• 3.3 V for M.2 Key-E slots
• 5 V for USB port
• 5 V and 3.3 V for mikroBUS socket
Clock SYSCLK:
• Supports single-ended SYSCLK and DDRCLK clock
input = 100 MHz (fixed)
• Supports single-source differential DIFF_SYCLK = 100
MHz (fixed)
SerDes:
• Provides clocks to all SerDes blocks and slots
• 100 MHz for SD1_REF_CLK2
• 100 MHz for SD2_REF_CLK1 and SD2_REF_CLK2
• 100 MHz for M.2 Key-E slots M2_1_REFCLK and
M2_2_REFCLK
RTC:
• Supports 32.768 kHz for LS1046A RTC
Ethernet:
• Supports differential 125 MHz for F104S8A QSGMII PHY
Debug • Supports Arm Cortex 10-pin JTAG connector
• Supports micro-USB port to access serial port as console
for debug
GPIO • Supports a 2x10 GPIO header (1.8 V)
• Supports bi-directional (configurable) inputs/outputs
1.5 Board top/bottom views
The figure below shows the top-side view of the FRWY-LS1046A.
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Figure 2. FRWY-LS1046A top view
The figure below shows the bottom-side view of the FRWY-LS1046A.
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Figure 3. FRWY-LS1046A bottom view
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Chapter 2
FRWY-LS1046A Functional Description
This chapter describes the features and functions of the FRWY-LS1046A. For details of the LS1046A processor features, see
QorIQ LS1046A Reference Manual .
The chapter is divided into the following sections:
•Power supplies
•Clocks
•DDR interface
•SerDes interface
•USB interface
•IFC interface
•SDHC interface
•UART interface
•Serial peripheral interface
•MikroBUS socket
•I2C interface
•JTAG header
•GPIOs
•Interrupt handling
•Temperature measurement
•DIP switch
•LEDs
•System reset
2.1 Power supplies
The FRWY-LS1046A gets 12 V input power from an external DC power supply. The power supply devices on the board use the
12 V power to generate required power supplies for the LS1046A processor, DDR4 SDRAMs, PHY, and numerous other
peripherals. The figure below shows the FRWY-LS1046A power supply block diagram.
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12V0
GND_IN
12V_IN
Synchronous
step-down
regulator
LT8609SEV#PBF
5V0
PLT10HH401100PNB
12V_PS
LTC7150SEY#PBF
LT8642SEV#PBF
3V3
PC33PF8100A0ES
VDD_EN
2V5
OVDD
V/A/P
INA220A
1mOHm/3W
LEGEND:
Switchable
Regulator
LDO Regulator
Power Switch
CPU_VDD
PS_XVDD
AC 110/220V@50/60Hz
1V
DDR_VTT
CPU_VDD
CPU_USB_SVDD
CPU_USB_SDVDD
3V3 CPU_USB_HVDD
XVDD
PS_XVDD
On Board
Peripherals
CPU_VDD,
USB_SVDD,
USB_SDVDD
CPU_SVDD
USB3.0 Ports x2
GST60A12-P1J
12V-5A (60W)
DC power adapter
For QSGMII PHY
SVDD
CPU_VDD
For QSGMII PHY, TVDD
CPU_OVDD & other Peripheral
NU
PJ-
063AH
GVDD
Power
adapter
5V@2A
Step-down
regulator
1/0.9V@20A
Synchronous
step-down
silent switcher
3.3V@10A
Multi-output
DC-DC
regulator
(LX1) 1V@1A
(LX2) 1.8V@2A
(LX3) [email protected]
(LX5) 1.2V@3A
(LX6) 0.6V@1A
(LX7) 2.5V@1A
LDO1, LDO2, LDO3
(LDO4) [email protected]
LPF
LPF
LPF
LPF
LPF
Figure 4. Power supply block diagram
Note that several power supplies have onboard low-pass filters to prevent board switching noise from coupling into sensitive
analog supplies. The figure below shows the filters used.
Figure 5. Low-pass filters
2.1.1 Primary power supply
The FRWY-LS1046A is powered up using an external 12 V DC power adapter. The table below describes the 12 V power adapter.
Table 4. 12 V power adpater
Part number Input power specifications Output power specifications
GST60A12-P1J (MEAN
WELL)
• Input: 110 - 230 VAC, 50 - 60 Hz
• 3-pole AC inlet (IEC 320 C14)
• Output: 12 V, 0 - 5 A DC power supply adapter
(160 W) - standard
• DC jack (2-pin, 2.1 mm x 5.5 mm x 11 mm)
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The table below shows the details of the power jack on the board to connect external 12 V power adapter.
Table 5. Power jack
Part identifier Part number Description
J1 PJ-063AH Plug/mating plug specifications:
• Inside diameter: 2.1 mm
• Outside diameter: 5.5 mm
• Rating: 8 A
2.1.2 Secondary power supplies
The table below describes the FRWY-LS1046A power supply devices that generate secondary power supplies for the board.
Table 6. FRWY-LS1046A power supply devices
Reference
designator
Device Power supply voltage Description
(From 12 V power
adapter)
12V0 (12 V at 5 A) Supply for LTC7150S, LT8609SEV, and
LT8642SEV power supply devices
U557 LTC7150S (Linear
Technology)
CPU_VDD (1/0.9 V ±3%
at 20 A)
• Supply for processor cores and platform (VDD)
• Filtered VDD also powers USB (USB_SDVDD
and USB_SVDD) and SerDes (SVDD) power
supplies of the LS1046A processor
• Jumper-enabled VDD also powers TA_BB_VDD
and FA_VL supplies of the LS1046A processor
• VDD is 1 V or 0.9 V depending on the jumper
setting on header J8
U1 LT8609SEV (Linear
Technology)
5V0 (5 V at 2 A) • Supply for dual-port USB 3.0 connector
• Supply for mikroBUS socket connector J57
U560 LT8642SEV (Linear
Technology)
3V3 (3.3 V at 10 A) • Supply for processor DVDD and EVDD
• Filtered 3V3 power for USB (USB_HVDD)
power supply of the LS1046A processor
• Supply for the following board components:
— Si5332FD10253-GM2 clock generator
— M.2 Key-E slots
— Micro-SDHC connector
— RTC
— I2C EEPROM
— Current monitor (INA220A)
— Temperature sensor (SA56004ED)
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Table 6. FRWY-LS1046A power supply devices (continued)
Reference
designator
Device Power supply voltage Description
— UART and SPI expansion headers
— MikroBUS socket connector J56
— CP2102N UART-USB bridge
— Misc. components (buffers and
translators)
• Supply for PC33PF8100EAES PMIC
U561 PC33PF8100EAES
(NXP Semiconductors)1
Multi-output DC-DC regulator with six switched outputs, one LDO output (VDD
enable), and one reset control output to the LS1046A processor. Six switched
outputs are given below:
SW1LX: 1V0_F104 (1 V
at 1 A)
Supply for the QSGMII PHY VDD and VDDA
SW2LX: OVDD (1.8 V at
2 A)
• Supply for processor OVDD, LVDD, and
TH_VDD
• Filtered OVDD powers for processor
AVDD_CGA[1:2], AVDD_PLAT, and AVDD_D1
• Supply for GPIO3_24 controlled processor
power TA_PROG_SFP (for fuse programming)
• Jumper-enabled OVDD also powers
PROG_MTR
• OVDD for board components:
— SLC NAND and QSPI memories
— Si5332FD10253-GM2 clock generator
VDDO5
— Misc. components (buffers and
translators)
SW3LX: 1V35 (1.35 V at
400 mA)
Filtered 1.35 V is supplied to processor XVDD,
AVDD_SD[1:2]_PLL1, and AVDD_SD[1:2]_PLL2
SW5LX: GVDD (1.2 V 3
A)
• Supply for DDR controller input/output (GVDD)
• Supply for DDR4 SDRAM memory chips
SW6LX: DDR_VTT (0.6
V at 1 A)
Supply for DDR address and control bus termination
(VTT)
VTT_Mode is enabled (sink
current is up to 700 mA
(typical)).
NOTE
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Table 6. FRWY-LS1046A power supply devices (continued)
Reference
designator
Device Power supply voltage Description
SW7LX: 2V5 (2.5 V at 1
A)
• Supply for processor TVDD
• Supply for QSGMII PHY VDD25, VDD25A, and
DDR4 memory VPP
1. The PC33PF8100EAES is a programmable PMIC that generates most of the LS1046A power. Power configurations are
stored in its one-time programmable (OTP) memory. The configuration in volatile memory can be changed through the
I2C1_CH0 interface. The device is accessible at 0x08 I2C 7-bit address.
2.1.3 Power supply sequence
The FRWY-LS1046A is configured to switch ON automatically when the 12 V power adapter (12 V power supply source) is
switched ON and is connected to power jack (J1) on the board. When the 12 V supply is available to power regulators on the
board, the power good signals of these regulators enable all board power supplies in correct sequence.
The board does not have a power ON/OFF switch. To power ON/OFF the board, plug/unplug the 12 V power
adapter to/from the board.
NOTE
The figure below shows the FRWY-LS1046A power supply sequence.
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12V
3.3V
soft-start from 12V
5V
soft-start from 3.3V PG
2.5V
PF8100 SEQ8 internally programmed
PF8100 SEQ8 internally programmed
1.8V
PF8100 SW2
VIN
LT8642SEV 3V3
LT8609SEV 3V3
PF8100 SW7
PF8100 SEQ8 internally programmed
1.35V
PF8100 SW3
5ms PF8100 SEQ18 internally programmed
1.0V, LDO[1:4]
LTC7150S VDD
VDD (0.9/1V)
PF8100 SW1, LDO[1:4]
soft-start after LDO4 (PS_VDD_EN)
tss
PF8100 SW6 VTT
mode
DDR4 (VTT)
PF8100 SEQ42 internally
programmed
PF8100 SW5
DDR4 (1.2V)
PG
From DC jack
PGOOD (to Rst_ctrl)
PF8100 PGOOD
PF8100 PGOOD_SEQ46 internally
programmed.
tvin_rise+tstest_done+ tfirst+Soft_start
2.5V,OVDD,
XVDD
Power
Tier1
PF8100 SEQ42 internally
programmed
RST_OUT (to LS1046_Rst_ctrl)
PF8100 RST_OUT
PF8100 PGOOD_SEQ52 internally
programmed.
3.87ms
31.4ms
2ms
12ms
2ms
1.5ms+1.4ms+0.1ms+4ms=7ms
5ms
Figure 6. Power supply sequence
The FRWY-LS1046A follows the power supply sequencing requirements mentioned in QorIQ LS1046A Data
Sheet .
NOTE
2.1.4 VDD current/power measurement
The FRWY-LS1046A facilitates onboard measurement of current and power for its VDD power supply. Current/power
measurement facility is not available for other power supplies as they are considered as low-current/incidental supplies. The table
below provides details of VDD current/power measurement.
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Table 7. VDD current/power measurement
Measurement device Shunt resistor value Notes
INA220AIDGST 0.001 The VDD supply powers the LS1046A core (1/0.9 V), USB
(USB_SDVDD and USB_SVDD), and SerDes (SVDD) power
supplies
2.2 Clocks
The FRWY-LS1046A has a clock generator (Si5332FD10253-GM2), which generates most of the clocks required for the
functioning of the LS1046A processor and different board peripherals. The figure below shows the clock diagram of the FRWY-
LS1046A.
LS1046A
DIFF_SYSCLK_P/N
SYSCLK
100 MHz (LVDS33)
100 MHz HCSL
Internal Ter mination REFCLK_P0
SD1_REFCLK2_P/N
Differential
Singl e-ended
M2_1_REFCLK_EN_B CLKREQ0
VDD_DIG/VDD_XTAL/VDDA
3V3
100 MHz LVCMO S (in-phase) 1.8 V
F104S8A
(QSGMII PHY)
125 MHz LVDS
VDDO[0:4] VDDO[5]
3V3 OVDD
Si5332FD10253-GM2
Silicon Labs
Internal Crystal
No External Cr ystal/OSC required
OUT0
OUT1
100 MHz HCSL 3.3 V 50 Ohms - Internal Ter mination
OUT2
SD2_REFCLK2_P/N
100 MHz HCSL 3.3 V 50 Ohms - Internal Ter mination
SD2_REFCLK1_P/N
100 MHz HCSL 3.3 V 50 Ohms -
Internal Ter mination
DDRCLK
OUT7
OUT7B 100 MHz LVCMOS (in-phase) 1.8 V
OUT6
SerDes2
OUT4
OUT3
100 MHz HCS L
Internal Ter mination REFCLK_P0
M2_2_REFCLK_EN_B
CLKREQ0
INPUT2
INPUT3
7-B it Ad dress = 0x6A
OUT5
M.2 Key-E slot 1
M.2 Key-E slot 2
Figure 7. FRWY-LS1046A clock diagram
Si5332FD10253-GM2 uses an internal 50 MHz crystal oscillator to generate different frequencies.
NOTE
The table below provides details of different clocks of the FRWY-LS1046A.
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Table 8. FRWY-LS1046A clocks
Clock generator Clocks Specifications Destination
U50: Si5332FD10253-GM2 OUT0:
QSGPHY_REFCLK_125M_[P,N]
• Frequency: 125 MHz
• Output type: LVDS
• Operating voltage: 3.3 V
QSGMII PHY
OUT1:
DIFF_SYSCLK_[P, N]
• Frequency: 100 MHz
• Output type: LVDS
• Operating voltage: 3.3 V
DIFF_SYSCLK
OUT2:
SD1_REFCLK2_[P, N]
• Frequency: 100 MHz
• Output type: HCSL
• Operating voltage: 3.3 V
SerDes1 controller
(PLL 2)
OUT3,51:
M2_1_REFCLK_[P,N]
M2_2_REFCLK_[P,N]
• Frequency: 100 MHz
• Output type: HCSL
• Operating voltage: 3.3 V
M.2 PCIe x1 slot 1
and slot 2
OUT4,6:
SD2_REFCLK2_[P, N]
SD2_REFCLK1_[P, N]
• Frequency: 100 MHz
• Output type: HCSL
• Operating voltage: 3.3 V
SerDes2 controller
(PLL 2 and PLL 1)
OUT7:
SYS_CLK_100MHz_LVCMOS
DDR_CLK_100MHz_LVCMOS
• Frequency: 100 MHz
• Output type: LVCMOS
• Operating voltage: 1.8 V
SYSCLK
DDRCLK
U523: PCF2129AT CLK_32KHZ • Frequency: 32.768 kHz
• Operating voltage: 3.3 V
LS1046A RTC
1. The clock generator also controls the enable/disable for 100 MHz clocks to M.2 PCIe x1 slots. When the clock generator
detects a card in any of the M.2 slots, it enables clocks to the slots. Clocks are enabled for both slots even if only one slot
is populated with a card.
2.3 DDR interface
The FRWY-LS1046A has five onboard x16 DDR4 SDRAM memory chips with four chips supporting data transfer and one chip
supporting ECC. The figure below shows the DDR diagram of the FRWY-LS1046A.
NXP Semiconductors
FRWY-LS1046A Functional Description
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 1, 05/2020
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1V2
}
VTT
0.6V
D1_MDQS[7:0],8
D1_MDQ[63:0]
D1_MDM[7:0],8
D1_MRAS / MCAS / MWE / MACT
D1_MA[13:0]
D1_MBA[1:0]
3V3
PC33PF8100EAES
D1_MAPAR / MBG[1:0]
D1_MDIC1
D1_MDIC0
162E
G1VDD
I2C1_CH0
Addr.= 0x52/0x53
D1_MCK[1:0] / MODT[1:0]
D1_MCS[1:0]
162E
LS1046A
RST_MEM_B
CPU_HRESET_B
VREFCA
0V6
DDR4 SDRAM
MT40A512M16JY-083E:B
8Gb 512Mbit x16
discreet chip (5 nos)
+ ECC
SPD
EEPROM
(optional)
D1_MCKE[1:0]
DQ[15:0]
DQ[16:31]
DQ[32:47]
DQ[48:63]
ECC[7:0]
D1_MECC[7:0]
T
E
R
M
I
N
A
T
I
O
N
VDD
1V2
VPP
2V5
GVDD
1V2
Fly-by
Topology
GVDD
3V3
0V6 DDR_VTT
D1_MALERT
1.0K
1V2
3V3
GVDD
source/sink
74AUP1G07GW
SW5
SW6
VTT
Figure 8. DDR diagram
The part number of the SDRAM memory chips is MT40A512M16JY-083E:B (from Micron Technology). Following are the
characteristics of the FRWY-LS1046A DDR interface:
• Supports data rates of up to 2133 MT/s
• Supports 64-bit data bus
• Supports x16 discrete memory modules (eight data byte lanes + ECC)
• Supports double-bit error detection and single-bit error correction ECC (8- bit check word across 64-bit data)
• Supports single chip select (D1_MCS0_B)
The address and control signals to the DDR4 SDRAM memory chips are routed as per Fly-by topology and are terminated at
VTT (0.6 V). The data bus and associated signals, such as MDM and MDQS have one-to-one connections with individual x16
DDR4 memories. The ECC nibble goes to the fifth DDR4 memory.
The different components of the FRWY-LS1046A DDR interface are powered by the following power supplies generated by the
PF8100 power management integrated circuit (PMIC):
• 1.2 V (GVDD) for DDR controller input/output
• 1.2 V and 2.5 V (VPP) for DDR4 SDRAM memory chips
• 0.6 V (VTT) for DDR address and control bus termination
NXP Semiconductors
FRWY-LS1046A Functional Description
Layerscape FRWY-LS1046A Board Reference Manual, Rev. 1, 05/2020
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