NXP Semiconductors SLN-VIZNAS-IOT Instruction Manual

1 SLN-VIZNAS-IOT Developer’s Guide, Rev. 1.2, 11/2020 NXP Semiconductors
NXPSemiconductors
Document Number: SLN-VIZNAS-IOT-DG
Developer’sGuide
Rev 1.2, 11/2020
MCU VIZNAS Solution Developer’s Guide
TABLE OF CONTENTS
1INTRODUCTION ............................................................................................................................................5
1.1 RT106F VISION CROSSOVER PROCESSOR OVERVIEW ......................................................................................5
2GETTING TO KNOW THE SLN-VIZNAS-IOT .....................................................................................................7
2.1 HARDWARE OVERVIEW .........................................................................................................................................7
2.2 SOFTWARE OVERVIEW ..........................................................................................................................................8
2.3 DEVICE MEMORY MAP .........................................................................................................................................9
2.4SECURITY ARCHITECTURE .....................................................................................................................................10
2.4.1 Application Chain of Trust....................................................................................................................10
2.4.2 Flash Image Configuration Area (FICA) and Image Verification ..........................................................11
2.4.3 Image Certificate Authority (CA) and Application Certificates.............................................................11
3GET STARTED WITH MCUXPRESSO TOOL SUITE ..........................................................................................13
3.1 MCUXPRESSO IDE.............................................................................................................................................13
3.2 INSTALL THE SDK ...............................................................................................................................................14
3.3 IMPORT A SLN-VIZNAS-IOT PROJECT ..................................................................................................................17
3.4 (OPTIONAL)INCREASE CLOCK DRIVE STRENGTH .......................................................................................................19
4BUILDING AND PROGRAMMING................................................................................................................. 21
4.1 BUILD A SLN-VIZNAS-IOT PROJECT.....................................................................................................................21
4.2 FLASH AND DEBUG SLN-VIZNAS-IOT PROJECT ......................................................................................................23
5BOOTLOADER ............................................................................................................................................. 26
5.1 APPLICATION FLOW ............................................................................................................................................26
5.2 OVER-THE-AIR (OTA)/OVER-THE-WIRE (OTW) UPDATES........................................................................................27
5.2.1 Transfers ..............................................................................................................................................27
5.2.2 Testing OTA/OTW Updates..................................................................................................................28
5.3 MASS STORAGE DEVICE (MSD) UPDATE ................................................................................................................30
5.4 GENERATE BANK BBINARY ..................................................................................................................................32
6AUTOMATED MANUFACTURING TOOLS .....................................................................................................33
6.1 ABOUT IVALDI....................................................................................................................................................33

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6.2 REQUIREMENTS .................................................................................................................................................33
6.3 CREATING A SIGNING ENTITY ................................................................................................................................34
6.3.1 Using Ivaldi to Generate Signing Artifacts ...........................................................................................34
6.4 MOVE BOOT JUMPER..........................................................................................................................................35
6.5 OPEN BOOT PROGRAMMING................................................................................................................................36
6.6 (OPTIONAL)ENABLING ENCRYPTED EXECUTE-IN-PLACE (EXIP) AND HIGH ASSURANCE BOOT (HAB) .................................37
6.6.1 Preparing the Environment..................................................................................................................38
6.6.2 Generating the PKI and Signed Flashloader.........................................................................................38
6.6.3 (Optional) Enabling Encrypted Execute in Place (eXIP) ........................................................................40
6.6.4 Enabling High Assurance Boot (HAB)...................................................................................................41
6.6.5 Preparing Bootstrap, Bootloader, and Main Application Images ........................................................42
6.6.6 Generating Secure Binary ....................................................................................................................44
6.6.7 Preparing for Programming the Device ...............................................................................................45
6.6.8 Enabling and Programming the Signed and Encrypted Binaries..........................................................46
7FILESYSTEM ................................................................................................................................................ 48
8DOCUMENT DETAILS................................................................................................................................... 49
8.1 REFERENCES......................................................................................................................................................49
8.2 ACRONYMS,ABBREVIATIONS,&DEFINITIONS..........................................................................................................49
8.3 REVISION HISTORY..............................................................................................................................................50
TABLE OF FIGURES
FIGURE 1: SLN-VIZNAS-IOT BASE BOARD +EXPANSION BOARD PERIPHERALS.............................................................................7
FIGURE 2: DUAL CAMERA ADAPTER KIT CONFIGURATION...........................................................................................................7
FIGURE 3: VIZNAS HW BLOCK DIAGRAM ..............................................................................................................................8
FIGURE 4: VIZNAS SW BLOCK DIAGRAM...............................................................................................................................8
FIGURE 5: DEVICE MEMORY MAP .........................................................................................................................................9
FIGURE 6: BOOT SECURITY FLOW CHART ..............................................................................................................................10
FIGURE 7: SIGNING ENTITIES...............................................................................................................................................11
FIGURE 8: MCUXPRESSO IDE WORKSPACE ..........................................................................................................................13
FIGURE 9: SELECT DEVELOPMENT BOARD..............................................................................................................................14
FIGURE 10: CHOOSE EMBEDDED REAL-TIME OPERATING SYSTEM ...............................................................................................14
FIGURE 11: SELECT ALL SDK COMPONENTS ...........................................................................................................................15
FIGURE 12: DOWNLOAD SDK.............................................................................................................................................15
FIGURE 13: DRAG AND DROP SDK ......................................................................................................................................16
FIGURE 14: IMPORT SDK CONFIRMATION WINDOW...............................................................................................................16
FIGURE 15: SDK IMPORT SUCCESSFUL .................................................................................................................................16
FIGURE 16: IMPORT SDK EXAMPLES....................................................................................................................................17
FIGURE 17: IMPORT SLN-VIZNAS-IOT EXAMPLES WIZARD ....................................................................................................17
FIGURE 18: IMPORT EXAMPLES...........................................................................................................................................18
FIGURE 19: PROJECTS SUCCESSFULLY IMPORTED ....................................................................................................................18
FIGURE 20: RIGHT-CLICK PROJECT.......................................................................................................................................19
FIGURE 21: “PROPERTIES”OPTION......................................................................................................................................19
FIGURE 22: PROPERTIES WINDOW ......................................................................................................................................20
FIGURE 23: PROJECT EXPLORER -HIGHLIGHT PROJECT ............................................................................................................21
FIGURE 24: BUILD PROJECT................................................................................................................................................21

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FIGURE 25: CONSOLE 'BUILD'OUTPUT.................................................................................................................................22
FIGURE 26: .AXF TO .BIN....................................................................................................................................................22
FIGURE 27: J-LINK PLUS AND 9-PIN CORTEX-M ADAPTER........................................................................................................23
FIGURE 28: SLN-VIZNAS-IOT JTAG HEADER ......................................................................................................................23
FIGURE 29: QUICKSTART PANEL -DEBUG..............................................................................................................................24
FIGURE 30: PROBE DISCOVERY WINDOW..............................................................................................................................24
FIGURE 31: FLASH DOWNLOAD IN PROGRESS ........................................................................................................................25
FIGURE 32: DEBUG BEGIN .................................................................................................................................................25
FIGURE 33: DEBUG TOOLBAR -RUN BUTTON ........................................................................................................................25
FIGURE 34: BOOTLOADER FLOW .........................................................................................................................................26
FIGURE 35: TRANSFER FORMAT ..........................................................................................................................................27
FIGURE 36: REQUEST/RESPONSE FLOW................................................................................................................................27
FIGURE 37: SERIAL HEADER CONNECTIONS ...........................................................................................................................29
FIGURE 38: "FWUPDATE_CLIENT.PY"W/O ARGS....................................................................................................................29
FIGURE 39: "FWUPDATE_CLIENT.PY"W/ARGS ......................................................................................................................30
FIGURE 40: MSD ENABLEMENT BUTTON..............................................................................................................................30
FIGURE 41: MSD MODE LIGHTS.........................................................................................................................................31
FIGURE 42: MSD USB DRIVE ENUMERATION .......................................................................................................................31
FIGURE 43: DRAGGING-AND-DROPPING NEW BINARY ............................................................................................................31
FIGURE 44: "VERSION"COMMAND OUTPUT .........................................................................................................................32
FIGURE 45: CREATE FLASH BANK BBINARY...........................................................................................................................32
FIGURE 46: VIRTUAL ENV PROMPT......................................................................................................................................34
FIGURE 47: GENERATE_SIGNING_ARTIFACTS.PY USAGE ...........................................................................................................34
FIGURE 48: GENERATE_SIGNING_ARTIFACTS.PY EXAMPLE ........................................................................................................35
FIGURE 49: SLN-VIZNAS-IOT BOOT JUMPER ......................................................................................................................35
FIGURE 50: REQUIRED OPEN_PROG_FULL BINARIES................................................................................................................36
FIGURE 51: OPEN_PROG_FULL.PY OUTPUT..........................................................................................................................37
FIGURE 52: "VIRTUALENV”PROMPT....................................................................................................................................38
FIGURE 53: SETUP_HAB.PY SCRIPT.......................................................................................................................................39
FIGURE 54: CHECKING THE SIGNED FLASHLOADER ..................................................................................................................40
FIGURE 55: ENABLING EXIP AND LOCKING BOOT MODE..........................................................................................................41
FIGURE 56: ENABLING HABUSING ENABLE_HAB.PY................................................................................................................42
FIGURE 57: IMPORTING THE APPLICATIONS FOR HAB AND EXIP................................................................................................42
FIGURE 58: UNSETTING THE XIP BOOT HEADER.....................................................................................................................43
FIGURE 59: GENERATING THE SREC......................................................................................................................................43
FIGURE 60: CHANGING FILE TYPE TO SREC.............................................................................................................................44
FIGURE 61: "IMAGE_BINARIES"EXPECTED FOLDER CONTENTS .................................................................................................44
FIGURE 62: SECURE APP FILE NAMES...................................................................................................................................44
FIGURE 63: SECURE.PY OUTPUT FOR SECURING IMAGES............................................................................................................45
FIGURE 64: "IMAGE_BINARIES"CONTENT ............................................................................................................................46
FIGURE 65: USING "CUST_PROG_SEC_APP.PY"......................................................................................................................47
FIGURE 66: FILE_FORMAT.PY USAGE....................................................................................................................................48
TABLE OF TABLES
TABLE 1: SUPPORTED COMPUTER CONFIGURATIONS .................................................................................................................6
TABLE 2: WI-FI FREQUENCY &POWER...................................................................................................................................6

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TABLE 3: REFERENCE DOCUMENTS ......................................................................................................................................49
TABLE 4: ABBREVIATIONS AND DEFINITIONS ..........................................................................................................................49
TABLE 5: REVISION HISTORY...............................................................................................................................................50

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1 Introduction
NXP’s MCU-based SLN-VIZNAS-IOT development kit provides OEMs with a fully
integrated, self-contained, software and hardware solution. This includes the i.MX
RT106F run-time library and pre-integrated machine learning face recognition algorithms,
as well as all required drivers for peripherals, such as camera and memories.
This cost-effective, easy-to-use face recognition implementation facilitates the demand
for a face-based Friction Free Interface that can be embedded in a variety of products
across home, commercial and industrial applications, thus eliminating the need to use
hard to learn and time-consuming mechanisms to identify users.
TARGET APPLICATIONS
•Safety/Security/Alarm devices: E-locks, Alarm panels, remote sensors, and
automated access
•Smart appliances: Washing machines, dryers, ovens, refrigerators, stoves, and
dishwashers
•Home comfort devices: Thermostats, remote temperature sensors, and lighting
•Counter-top appliances: Microwaves, coffee machines, rice cookers, and
blenders
•Smart industrial devices: Power tools, ergonomic stations, machine access and
authorization
1.1 RT106F VISION CROSSOVER PROCESSOR OVERVIEW
The i.MX RT106F is an EdgeReady member of the i.MX RT1060 family of crossover
processors, targeting low cost embedded face recognition applications. It features NXPs
advanced implementation of the Arm® Cortex®-M7 core, which operates at speeds up to
600 MHz to provide high CPU performance and best real-time responses. This i.MX
RT106F based solution enables system designers to easily and inexpensively add face
recognition capabilities to a wide variety of smart appliances, smart homes, FRICTION
FREE INTERFACE VISION HARDWAREand smart industrial devices. The i.MX RT106F
processor is licensed to run NXPs i.MX RT run-time library for face recognition which may
include:
•Camera drivers
•Image capture
•Image pre-processing
•Face alignment
•Face detection
•Face recognition
•Liveness Detection
•Emotion recognition

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Once you’re ready to begin development, you will need to download MCUXpresso IDE.
The current SDK is tested with version 11.2.1 of MCUXpresso IDE and Segger J-Link
v6.6x.
https://www.nxp.com/support/developer-resources/software-development-
tools/mcuxpresso-software-and-tools/mcuxpresso-integrated-development-
environment-ide:MCUXpresso-IDE
Table 1: Supported Computer Configurations
Usage Condition
The following information is provided per Article 10.8 of the Radio Equipment Directive
2014/53/EU:
(a) Frequency bands in which the equipment operates.
(b) The maximum RF power transmitted.
PN
RF Technology
(a) Freq Range
(b) Max Transmitted Power
SLN-VIZNAS-IOT
Wi-Fi
2412MHz-2472MHz
17.9dBm
Table 2: Wi-Fi Frequency & Power
EUROPEAN DECLARATION OF CONFORMITY (Simplified DoC per Article 10.9 of the
Radio Equipment Directive 2014/53/EU)
This apparatus, namely SLN-VIZNAS-IOT, conforms to the Radio Equipment Directive
2014/53/EU. The full EU Declaration of Conformity for this apparatus can be found at this
location: https://www.nxp.com/
**NOTE: See Preparing Bootstrap, Bootloader, and Main Application Images for an example of
changing preprocessor macros
Computer type
OS version
Terminal
Apple
Mac OS
PuTTY
PC
Windows 10
PuTTY/Tera Term
PC
Linux
PuTTY
To maintain EMC Compliance, the CLOCK_DRIVE_STRENGTH_LOW
preprocessor macro* must remain set to 1
System Requirements and Prerequisites

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2 Getting to Know the SLN-VIZNAS-IOT
2.1 Hardware Overview
The SLN-VIZNAS-IOT kit is intended to provide a reference for a real product design. The
kit is designed using a small form factor which takes into account many of the design
considerations a hardware engineer would make when creating a product. With that said,
NXP has also fashioned the hardware to have some of the key hallmarks of a traditional
development kit.
Figure 1: SLN-VIZNAS-IOT Base Board + Expansion Board Peripherals
Additionally, the SLN-VIZNAS-IOT kit comes with an IR+RGB Dual Camera Adapter like
that shown below for use in secure applications.
Figure 2: Dual Camera Adapter Kit Configuration

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Figure 3: VIZNAS HW Block Diagram
2.2 Software Overview
The SLN-VIZNAS-IOT kit has been built and designed in such a way that enables best
security practices while keeping a development kit feel. The main security mechanism
that has been implemented is a series of image verification stages that are required for
every image programmed onto the device. The sections below guide you through the
overall software and security architectures and the implications they have during the
development and production phases of your product development.
Figure 4: VIZNAS SW Block Diagram

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2.3 Device Memory Map
To understand the various pieces of the system, it helps to see the memory map that NXP
has developed for this application. There are many components required in the system
to successfully boot and execute an application. A few of these sectors will be described
in greater detail below.
Figure 5: Device Memory Map
0x60000000
Bootloader
Bootstrap
0x60D00000
BankA
ApplicationA
BankB
ApplicationB
0x60300000
0x60040000
0x61700000
File System:
0x60000000
Bootloader
Bootstrap
0x60D00000
BankA
ApplicationA
BankB
ApplicationB
0x60300000
0x60040000
AppB Certificate
AppA Certificate
0x61700000
File System:
ROOT_CA_CERT
AppA SIGN CERT
AppB SIGN CERT
Btld SIGN CERT
0x61CC0000
0x61D00000
0x61D40000
0x61D80000
0x61FC0000
FICA Table:
DESCRIPTOR
AppType, BootType, ComBits
RECORDS (x3)
ImgType, AppAddr
Signatures
RegisteredUsers DataBase 0x60800000 RegisteredUsers DataBase 0x60800000
DevCfg Data 0x61B00000
DevCfg Data 0x61B00000
Bootloader Certificate
DISABLE_IMAGE_VERIFICATION = 1 DISABLE_IMAGE_VERIFICATION = 0
0x61FC0000
FICA Table:
DESCRIPTOR
AppType, BootType, ComBits
RECORDS (x3)
ImgType, AppAddr

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2.4 Security Architecture
The following figure shows the series of checks that occur at boot time. Configuration
options in the various applications (ROM bootloader, bootstrap, bootloader) will determine
which sequence is followed. The state of the board from factory is with all security
checks disabled.
Figure 6: Boot Security Flow Chart
If at any point a signature check fails (in the case where HAB or image verification is
enabled), the boot process stops.
2.4.1 Application Chain of Trust
The basis of the security architecture implemented in the SLN-VIZNAS-IOT is signed
application images. Signing requires the use of a Certificate Authority (CA). NXP has
its own CA for signing applications at the factory, but the CA is not something that is
shared with customers.
The CA is used to create signing entities for the bootloader and application. A certificate
from the CA is stored in the SLN-VIZNAS-IOT’s filesystem and is used to verify the
signatures of the signing entity certificates. In addition, locally stored certificates from the
signing entities are used to verify the signature of firmware images coming in over the
OTA/OTW bootloader interface.

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Figure 7: Signing Entities
2.4.2 Flash Image Configuration Area (FICA) and Image Verification
The FICA table is a section inside the filesystem that is responsible for describing the
images that will be booted. It contains information about the image and signatures of the
applications that will be used to ensure that only verified firmware is executed. This
ensures malicious images cannot be executed without first being signed by the certificate
authority and certificate that is programmed into the filesystem. Before any image is
jumped to, it is first verified using the signature from its associated FICA entry.
For example, in the standard boot flow shown in Figure 6:
•The bootstrap will use the bootloader FICA entry to validate the bootloader
•The bootloader will use the AppA FICA entry to validate the AppA image
•The bootloader will use the AppB FICA entry to validate the AppB image
For final production, the solution provides programming scripts to enable i.MX RT High
Assurance Boot (HAB) to verify and protect the bootstrap component. It is recommended
that users enable HAB for their end product.
The downside of having this security protection enabled is that programming new images
can be a little more complex as it requires signature generation. Taking in consideration
that this flow may be time consuming and not required for basic development tasks, NXP
introduced some bypasses to make the job easier for developers. These bypasses
should not be deployed in production.
Again, the default configuration of the SLN-VIZNAS-IOT is to have HAB disabled and
signature verifications bypassed. This is to ensure a smooth development experience.
2.4.3 Image Certificate Authority (CA) and Application Certificates
The SLN-VIZNAS-IOT kit comes pre-programmed with signed images (though signature
verification is bypassed by default) as indicated in the Flash Image Configuration Area
(FICA) and Image Verification section. The bootloader_4343W and elock_oobe
application are signed using NXP’s test CA and can be used to ensure the authenticity of
all images which are intended to be booted.

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The application signing certificates are located at the following locations in the filesystem:
•Address 0x61D00000 for Application Bank A
•Address 0x61D40000 for Application Bank B
•Address 0x61D80000 for the Bootloader
The certificate for the CA (used to verify the application signing certificates) is located at
address 0x61CC0000 in the filesystem. For more detail, see Figure 5: Device Memory
Map.
These certificates are used when Image Verification (see section Enabling Image
Verification) is enabled to validate the signature provided when performing a secure
update.

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3 Get Started with MCUXpresso Tool Suite
The following section describes the steps required to setup the environment and prepare
it for development.
3.1 MCUXpresso IDE
MCUXpresso IDE brings developers an easy-to-use Eclipse-based development
environment for NXPs microcontrollers based on Arm® Cortex®-M cores. It offers
advanced editing, compiling and debugging features with the addition of MCU-specific
debugging views, code trace and profiling, multicore debugging, and integrated
configuration tools. Its debug connections support every NXP evaluation boards with
industry-leading open-source and commercial debug probes from ARM®, P&E Micro®
and SEGGER®.
NOTE: The SLN-VIZNAS-IOT requires MCUXpresso IDE version 11.2.1 or greater.
1. To download NXP MCUXpresso IDE for free go online to: www.nxp.com/MCUXpresso
2. Select MCUXpresso IDE from the PRODUCTS tab.
3. Go to DOWNLOADS tab and select the LATEST VERSION of the tool.
If you do not already have one, you will be asked to sign-in/up with a free NXP user-
account.
4. When MCUXpresso installer download completes, double click on the executable,
follow the install instructions and keep the default options.
5. Launch MCUXpresso IDE and define the Workspace location where you will copy and
store your projects (default C:\MCUXpresso.Workspace) and press OK.
Figure 8: MCUXpresso IDE Workspace

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3.2 Install the SDK
MCUXpresso SDK is a comprehensive software enablement package designed to
simplify and accelerate application development with NXPs microcontrollers based on
Arm® Cortex®-M cores. The MCUXpresso SDK includes production-grade software with
integrated RTOS (optional), integrated stacks and middleware, reference software, and
more. It is available in custom downloads based on user selections of MCU, evaluation
board, and optional software components.
Before building the SLN-VIZNAS-IOT SDK example projects, the target SDK needs to be
imported into MCUXpresso IDE.
The MCUXpresso SDK for the SLN-VIZNAS-IOT can be downloaded from NXP’s SDK
Builder by clicking Select Development Board and searching for “SLN-VIZNAS-IOT” in
the search box.
Figure 9: Select Development Board
When building the SDK, be sure to select FreeRTOS under Embedded real-time
operating system.
Figure 10: Choose Embedded real-time operating system

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After updating the operating system, be sure to click Select All to make sure all required
components get added.
Figure 11: Select all SDK components
With these options selected, press the Download SDK button at the bottom of the page.
Figure 12: Download SDK

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Once the SDK is downloaded, import the SDK into MCUXpresso IDE by dragging the
SDK zip folder into the Installed SDKs window in MCUXpresso IDE.
Figure 13: Drag and Drop SDK
For each package, a confirmation window will pop-up. Select OK to validate.
Figure 14: Import SDK Confirmation Window
Once the package has been imported, it will be displayed in the Installed SDKs window
in MCUXpresso.
Figure 15: SDK Import Successful

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3.3 Import a SLN-VIZNAS-IOT Project
The SLN-VIZNAS-IOT SDK allows you to import existing application examples as a
development starting point. The following steps will show you how to import one of these
example projects into MCUXpresso IDE.
From the Quickstart Panel, select Import SDK example(s).
Figure 16: Import SDK Examples
For each SDK you have installed into MCUXpresso, a corresponding image will be
shown. Select the SLN-VIZNAS-IOT image and proceed by selecting the Next button.
Figure 17: Import SLN-VIZNAS-IOT Examples Wizard

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The import wizard will then display all the example applications that are available to
import. For this guide we will be focused primarily on the sln_viznas_iot_elock_oobe
application. This is the application that comes flashed by default on your SLN-VIZNAS-
IOT kit.
Figure 18: Import Examples
NOTE: If your kit’s flash has been completely erased, you will also need the
“sln_viznas_iot_bootloader_4343W”and “sln_viznas_iot_bootstrap”projects found under sln_boot_apps as
well in order for the sln_viznas_iot_elock_oobe application to work.
Once the projects have successfully been imported, they will be listed in the project
explorer ready to be built and run.
Figure 19: Projects Successfully Imported

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3.4 (Optional) Increase Clock Drive Strength
By default, the sln_viznas_iot_elock_oobe application uses a lower clock rate and clock
drive strength for the cameras than the 106F is capable of in order to maintain EMC
compliance (see RT106F VISION CROSSOVER PROCESSOR OVERVIEW). This lower
clock rate results in a lower FPS and overall recognition performance.
To make it easy for developers to utilize the full performance capabilities of the camera,
the sln_viznas_iot_elock_oobe project provides a convenient preprocessor macro which
can be configured to increase or decrease the camera clock’s drive strength and clock
rate. To configure this preprocessor macro, right click on the sln_viznas_iot_elock_oobe
project in the Project Explorer pane as shown in the figure below and select Properties,
found near the bottom of the context menu:
Figure 20: Right-Click Project
Figure 21: “Properties” Option

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Clicking the Properties option will open up a new window which looks like the one shown
in Figure 22: Properties Window. From there:
1. Click Settings
2. Click MCU C++ Compiler -> Preprocessor
3. Double click the CAMERA_DRIVE_STRENGTH_LOW macro
4. Change the value from 1 to 0 and click OK.
Repeat the previous steps for the CAMERA_DRIVE_STRENGTH_LOW preprocessor
macro found under MCU C COMPILER -> Preprocessor, then003A
5. Click Apply and Close.
Figure 22: Properties Window