NXP Semiconductors MPC8349E-mITX-GP User manual

© Freescale Semiconductor, Inc., 2006. All rights reserved.
Preliminary—Subject to Change Without Notice
Freescale Semiconductor
User’s Guide
The MPC8349E-mITX-GP reference design platform is a
system featuring the powerful PowerQUICC™ II Pro
processor, which includes a built-in security accelerator.
This low-cost, high-performance system solution consists of
a printed circuit board (PCB) assembly known as the
MPC8349E-mITX-GP Board, plus a board support package
(BSP), distributed in a CD image. This BSP enables fastest
possible time-to-market for development or integration of
applications including media servers, network attached
storage devices, and next-generation small office home
office/small medium business gateways.
Section 1, “MPC8349E-mITX-GP Board,” describes the
board in terms of its hardware: the features, specifications,
block diagram, connectors, interface specification, and
hardware straps.
Section 2, “GettingStarted,”describes theboardsettingsand
physical connections needed to boot the
MPC8349E-mITX-GP board.
Section 3, “MPC8349E-mITX-GP Software,” describes the
software that is shipped with the platform.
Use this manual in conjunction with the following
documents:
•MPC8349E PowerQUICC™ II Pro Integrated Host
Processor Family Reference Manual
(MPC8349ERM)
Document Number: MPC8349EMITXGPUG
Rev. 0, 10/2006
Contents
1. MPC8349E-mITX-GP Board . . . . . . . . . . . . . . . . . . . 2
2. Getting Started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3. MPC8349E-mITX-GP Software . . . . . . . . . . . . . . . . 34
4. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MPC8349E-mITX-GP Reference
Design Platform User’s Guide
WARNING
This is a class A product. In a domestic
environment this product may cause radio
interference in which case the user may be
required to take adequate measures.
NOTE
This equipment has been tested and found to
comply with the limits for a Class A digital
device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide
reasonable protection against harmful
interference when the equipment is operated
in a commercial environment. This
equipment generates, uses, and can radiate
radio frequency energy and, if not installed
and used in accordance with the instruction
manual, may cause harmful interference to
radio communications. Operation of this
equipment in a residential area is likely to
cause harmful interference in which case the
user will be required to correct the
interference at his own expense.

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•MPC8349E PowerQUICC II Pro Integrated Host Processor Hardware Specifications
(MPC8349EEC)
•Hardware and Layout Design Considerations for DDR Memory Interfaces (AN2582)
1 MPC8349E-mITX-GP Board
This section presents the features and block diagram, specifications, and mechanical data for the
MPC8349E-mITX-GP board.
1.1 Features
This section presents the features, specification, and block diagram of the MPC8349E-mITX-GP board.
The features are as follows:
• CPU: Freescale MPC8349E running at 533/266 MHz (CPU/CSB (Coherent System Bus))
• Memory subsystem:
— 128 MByte unbuffered DIMM SDRAM that is expandable to 1 Gbyte
— 8 MByte Flash memory (one Macronix™MX29LV640M Flash memory bankorone ESSI
EN29LV640 Flash memory bank)
• Interfaces:
— 10/100/1000 BaseT Ethernet ports:
– TSEC1,GMIIinterface: one 10/100/1000 BaseT RJ-45 with RJ-45 interface using Vitesse™
VSC8201 single port 10/100/1000 BaseT PHY
— USB 2.0 host and OTG:
– USB2, ULPI interface: one USB2.0 type mini-AB receptacle connector, with SMSC™
USB3300 Hi-Speed USB host/device/OTG PHY
— PCI2: 32-bit PCI interface running at up to 66 MHz
– One 32-bit 3.3 V PCI slot connected to PCI-2
— ST M24256 Serial EEPROM
— Dallas™DS1339 RTC with battery holder
• Board connectors:
—2×10 ATX power supply connector
— RS-232 connectors
–1×9 pin DB9 receptacle
– JTAG/COP for debugging
— Form factor: Mini-ITX form factor (170 mm ×170 mm, or 6692 mils ×6692 mils)
• 6-layer Printed Circuit Board (4-layer signals, 2-layer power and ground)

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Figure 1 shows the MPC8349E-mITX-GP board block diagram.
Figure 1. MPC8349E-mITX-GP Board Block Diagram
1.2 Board-Level Functions
The board-level functions discussed in this section are reset, interrupts, and clock distribution.
1.2.1 Reset and Reset Configurations
The MPC8349E-mITX-GP reset module generates a single reset to reset the MPC8349E and other
peripherals on the board. The reset unit provides power-on reset, hard reset, and soft reset signals in
compliance with the MPC8349E hardware specification.
GbE PHY
RTC EEPROM RS-232 x 2 Power
33/66 MHz
PCI
GMII
I2C
DDR Bus
1 x GbE
Power
Local Bus
32-Bit PCI Slot
ULPI1
JTAG/COP
64 Mbyte ~ 1 Gbyte DDR
8 Mbyte Flash
USB PHY
MPC8349E

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Figure 2 shows the reset circuitry.
Figure 2. Reset Circuitry of the MPC8349E
• Hard reset is generated either by the COP/JTAG port or the MPC8349E.
• Power-on reset is generated by the Maxim MAX811 device. When MR is deasserted and 3.3 V is
ready, the MAX811 internal timeout guarantees a minimum reset active time of 150 ms before
PORESET is deasserted. This circuitry guarantees a 150 ms PORESET pulse width after 3.3 V
reaches the right voltage level, and this meets the specification of the PORESET input of
MPC834x.
• COP/JTAG port reset provides convenient hard-reset capability for a COP/JTAG controller. The
RESET line is available at the COP/JTAG port connector. The COP/JTAG controller can directly
generate the hard-reset signal by asserting this line low.
• Push button reset interfaces the MR signal with a debounce capability to produce a manual master
reset of the processor card.
• Soft reset is generated by the COP/JTAG port. Assertion of SRESET causes the MPC8349E to
abort all current internal and external transactions and set most registers to their default values.
MAX811
3.3 V
MR
Push Button
GND
HRESET from COP
SRESET from COP
TRST from COP
SRESET to MPC8349E
TRST to MPC8349E
PORESET to MPC8349E
FLASH
10/100/1000 PHY
MPC8349E
USB PHYs

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1.2.2 External Interrupts
Figure 3 shows the external interrupt circuitry to the MPC8349E.
Figure 3. MPC8349E Interrupt Circuitry
Following are descriptions of the interrupt signals shown in Figure 3:
• PHY interrupt (GBE1_IRQ) and RTC interrupt (RTC_IRQ).The VSC8201 GBE PHY interrupt is
ORed with the DS1339 RTC interrupt and connected to IRQ2 of the MPC8349E. Therefore, the
system software can detect the status of the Ethernet link, the PHY internal status, and the RTC
status.
• PCI interrupt (PCI_INTA, PCI_INTB). The 32-bit PCI slot INTA and INTB are connected to the
IRQ4 and IRQ5 of the MPC8349E, respectively.
• USB over current (USB2_IRQ). The USB2 power supply has an over current detection circuit and
generate an interrupt when the current limit reaches (2A) or a thermal shutdown or under voltage
lockout (UVLO) condition occurs. This interrupt pin generates an interrupt to IRQ3 of the
MPC8349E.
GBE1_IRQ
RTC_IRQ
USB2_IRQ
PCI_INTA
PCI_INTB
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
MPC8349E
External Logic

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1.2.3 Clock Distribution
Figure 4 and Table 1 show the clock distribution on the MPC8349E-mITX-GP board.
Figure 4. MPC8349E-mITX-GP Clock Scheme
MPC8349E
Local Bus CLK
DDR SDRAM
CLK
LCLKx
MCKx
DS1339
GND GND
32.768 KHz
Crystal
MCKx
125 MHz 133 MHz
33 MHz to 133 MHz
TSEC
local bus
DLL
DDR
DLL
PCI
DIV
66.666 MHz
OSC
CLKIN
33/66 MHz 32-bit PCI Slot
OCCR
2
GPL5 PCI_SYNC_OUT
PCI_SYNC_IN
System
PLL
CFG_CLKIN_DIV
USB3300
GND GND
24 MHz
Crystal
VSC8201
25 MHz
OSC

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1.2.4 DDR SDRAM Controller
MPC8349E uses DDR SDRAM asthe systemmemory. The DDR interface uses the SSTL2 driver/receiver
and 2.5 V power. A Vref 2.5V/2 is needed for all SSTL2 receivers in the DDR interface. For details on
DDR timing design and termination, refer to the Freescale application note entitled Hardware and Layout
Design Considerations for DDR Memory Interfaces (AN2582). The termination scheme uses one series
resistor (RS) from the MPC8349E to the memory and one termination resistor (RT) attached to the
termination rail (VTT). This approach is used in commodity PC motherboard designs.
The MPC8349E reads the DIMM SPD data using the DIMM SCL (clock) and the SDA (data) signals
through the I2C2 interface. Figure 5 shows the DDR SDRAM controller connection.
Table 1. Clock Distribution
Clock Frequency Module Generated by Description
66.666 MHz MPC8349E CLKIN 66.666 MHz oscillator The MPC834x uses CLKIN to generate the
PCI_SYNC_OUT clock signal, which is fed back
on the board through the PCI_SYNC_IN signal
to the internal system PLL. From the power-on
reset configuration, the CSB clock is generated
by the internal PLL and is fed to the e300 core
PLL for generating the e300 core clock. The
GPL5 (CFG_CLKIN_DIV) configuration input
selects whether CLKIN or CLKIN/2 is driven on
the PCI_SYNC_OUT signal. The GPL5 is tied to
jumper J22.D.
125 MHz MPC8349E TSEC VSC8201 For TSEC operation, a 125 MHz clock is
provided by the gigabit Ethernet PHY
(VSC8201) on the board.
133/166 MHz DDR SDRAM MPC8349E The DDR memory controller is configured to use
the 1:1 mode CSB to DDR clock for the DDR
interface. The local bus clock uses CCB/n clock,
where n is configured from the LCRR register.
25 MHz GBE PHY (VSC8201) 125 MHz oscillator The 25 MHz oscillator generates the clock for
the VSC8201
33/66 MHz PCI 32-bit slot MPC8349E The PCI module uses the PCI_SYNC_IN as its
clock source. The trace of the PCI_SYNC_IN/
PCI_SYNC_OUT signal is synchronized with all
the PCI signals of the PCI slots. The trace length
of the PCI_SYNC_IN/PCI_SYNC_OUT clock is
2.5 inches from the pin of the PowerQUICC II
Pro device to the PCI sockets.
24 MHz USB PHY2 (USB3300) 24 MHz crystal
32.768 KHz RTC (DS1339) 32.768 KHz crystal

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Figure 5. DDR SDRAM Connection
1.2.5 Local Bus Controller
The MPC8349E local bus controller has a 32-bit LAD[0–31] address that consists of data multiplex bus
and control signals. The local bus speed is up to 133 MHz. To interface with the standard memory device,
an address latch must provide the address signals. The LALE is used as the latching signal. To reduce the
load of the high speed 32-bit local bus interface, there is a data buffer for all low-speed devices attached
to the memory controller. The on-board single bank 8-Mbyte Flash memory module is connected to the
local bus.
DDR
SDRAM
Controller
Vref
Generator
Vref 1.25 V
2.5 V Input
Vref
DDR
SDRAM
DIMM184
DQ[0:63]
DQM[0:7]
DQS[0:7]
A[0:13], BA[0,1],CTRL
MCK[0:3] pairs
MSYNC_OUT
MSYNC_IN
MPC8349E
VTT
Generator
2.5 V Input
I2C– SCK2
I2C–SDA2
VTT 1.25 V

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Figure 6 shows the block diagram and connections for the local bus.
Figure 6. Local Bus Connections
1.2.6 On-Board Flash Memory
Through the general-purpose chip-select machine (GPCM), the MPC8349E-mITX-GP provides a total of
8 Mbyte of 90 ns Flash memory using one chip-select signal. The Flash memory is used with the 16-bit
port size.
The starting address for the Flash bank is 0xFE00_0000 to 0xFE7F_FFFF.
1.2.7 I2C
The MPC8349E has two I2C interfaces. On the MPC8349E-mITX-GP board, the MPC8349E acts as I2C
master for both I2C buses (I2C1 and I2C2). I2C1 is connected to the M24256 serial EEPROM, and I2C2
Table 2. Boot Flash Selection
J22.E BOOT1 Boot Flash Backup Flash
Jumper Off 1 Reserved Reserved
Jumper On 0 U7 U4
MPC834E
Control Signals
LAD[0:31]
BADDR[27:29]
ALE
Address
LE
LBCTL
Local Bus
LCS0
Data
DIR OE
OE
GND A[21:0]
CS
Flash Memory
D[15:0]
Control
A[9:30]
LCLK0 LCLK1 LCKE
LSYNC_OUT LSYN_IN
F1CS
Latch
Buffer
LCS0 Boot Flash
Select F1CS
Control
MX29LV640M
LAD[8:31]
LAD[0:15]
D[0:15]
Controller
Jumpers

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is connected to the DDR DIMM module SPD (serial presence detect) EEPROM, the two PCF8574 I2C
expanders, the DS1339 RTC (real time clock).
The M24256 serial EEPROM can be used to store the reset configuration word of the MPC8349E, as well
as storing the configuration registers values if boot sequencer of MPC8349E is enabled. If user wants to
load the reset configuration word from the I2C1 M24256 EEPROM, the jumper J22 should be set to
ABCDEFGH=01011110, with 1=jumper removed and 0=jumper installed. For more details on how to
program the reset configuration word value in I2C EEPROM and the boot sequencer mode, please refer to
the MPC8349ERM. The I2C address of the M24256 EEPROM on I2C1 bus is 0x50.
The DDR SPD EEPROM is connected to the I2C2 of MPC8349E. The bootload program optionally reads
the SPD EEPROM data to determine the DDR DIMM physical structure (e.g. number of rows and
columns), the DDR timings (e.g. CAS latency, re-fresh timing), and setup the configuration registers of
the MPC8349E DDRmemory controller. The I2C addressof theDDR SPDEEPROM onI2C2 busis 0x51.
There are two PCF8574A I2C I/O expander on the MPC8349E-mITX-GP board to provide general
purpose I/O expansion via the I2C2 interface. The first PCF8574A (U8) has I2C2 address 0x38 and it is
able to control the Green LED (D1) and Yellow LED (D2), set the VSC8201 to powerdown mode. The bit
definition of this PCF8574A (U8) is defined as in Table 3.
The second PCF8574A (U10) has I2C2 address 0x39 and it is able to detect the board revision number,
the PCI M66EN signal level and detect which Flash is currently used to boot. The bit definition of this
PCF8574A (U10) is defined as in Table 4.
Table 3. PCF8574A (U8) Bit Descriptions
PCF8574A(U8)
Bit[0..7] Name Read/Write Description
0LED0Writeonly,
read returns 1
LED0 control
0: LED is on
1: LED is off
1 LED1 Write only,
read returns 1
LED1 control
0: LED is on
1: LED is off
2 VSC8201_PWN Write only,
read returns 1
VSC8201 power down control
0: VSC8201 PHY is powerdown
1: VSC8201 PHY in normal mode
3
Reserved
Write only,
read returns 1 Reserved
4 LCD_EN Write only,
read returns 1 Reserved
5 Not used — —
6 Not used — —
7 Not used — —