NXP Semiconductors FRDMKW36UG User manual

1 Introduction
This guide describes the hardware for the FRDM-KW36 Freedom
development board. The FRDM-KW36 Freedom development board is highly
configurable, low-power, and cost-effective evaluation board for application
prototyping and demonstration of the KW36A/35A and KW36Z/35Z family of
devices. This evaluation board offers easy-to-use mass-storage-device mode
flash programmer, a virtual serial port, and standard programming and run-
control capabilities.
The KW36 is an ultra-low-power, highly integrated single-chip device that enables Bluetooth® Low Energy (LE) or Generic FSK
(at 250, 500 and 1000 kbps) for portable, low-power embedded systems.
The KW36 integrates a radio transceiver operating in the 2.36 GHz to 2.48 GHz range supporting a range of GFSK, an Arm
Cortex-M0+ CPU, up to 512 KB Flash and up to 64 KB SRAM, Bluetooth LE Link Layer hardware and peripherals optimized to
meet the requirements of the target applications.
2 Overview and description
The FRDM-KW36 development board is an evaluation environment supporting KW35Z/36Z/35A/36A (KW36) Wireless
Microcontrollers (MCU). The KW36 integrates a radio transceiver operating in the 2.4 GHz band (supporting a range of GFSK
and Bluetooth LE) and an Arm Cortex-M0+ MCU into a single package. NXP supports the KW36 with tools and software that
include hardware evaluation and development boards, software development IDE, applications, drivers, and a custom PHY with
a Bluetooth LE Link Layer. The FRDM-KW36 development board consists of the KW36A device with a 32 MHz reference crystal
oscillator, RF circuitry (including antenna), 4-Mbit external serial flash, CAN and LIN transceivers and supporting circuitry in the
popular Freedom board form-factor. The board is a standalone PCB and supports application development with NXP’s Bluetooth
LE and Generic FSK libraries.
2.1 Overview
Figure 1 shows a high-level block diagram of the FRDM-KW36 board features.
Contents
1 Introduction............................................ 1
2 Overview and description...................... 1
3 Functional description............................6
4 Headers and jumpers.......................... 22
5 References.......................................... 26
6 Revision history................................... 27
FRDMKW36UG
FRDM-KW36 Freedom Development Board User’s Guide
Rev. 4 — 01/2020 User's Guide

Figure 1. FRDM-KW36 block diagram
2.2 Feature description
The FRDM-KW36 development board is based on NXP Freedom development platform. It is the most diverse reference design
containing the KW36A device and all necessary I/O connections for use as a stand-alone board, or connected in an application.
Figure 2 shows the FRDM-KW36 development board.
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Figure 2. FRDM-KW36 Freedom development board
The FRDM KW36 development board includes these features:
• NXP ultra-low-power KW36A Wireless MCU supporting Bluetooth LE and Generic FSK.
• Compliant Bluetooth 5 LE.
• Reference design area with small-footprint, low-cost RF node:
— Single-ended input/output port.
— Low count of external components.
— Programmable output power from -30 dBm to +3.5 dBm at the SMA connector, when using DCDC Bypass or
operating the DCDC in Buck mode.
— Receiver sensitivity is -100 dBm, typical (@1 % PER for 20-byte payload packet) for GFSK applications (250 kbps,
BT=0.5, h=0.5), at the SMA connector.
— Receiver sensitivity is -95 dBm (for Bluetooth LE applications) at the SMA connector.
• Integrated PCB inverted F-type antenna and SMA RF port (requires moving C55 to C57)
• Selectable power sources.
• DC-DC converter with Buck, and Bypass operation modes.
• 32 MHz reference oscillator for RF operation.
• 32.768 kHz reference oscillator mainly used for RTC operation and RF low power operation.
• 2.4 GHz frequency operation (ISM and MBAN).
• 4-Mbit (512 kB) external serial flash memory for Over-The-Air Programming (OTAP) support
• NXP FXOS8700CQ Digital Sensor, 3D Accelerometer (±2g/±4g/±8g) + 3D Magnetometer
• Thermistor circuit to test KW36 ADC module.
• Coin cell connector compatible with a CR2032 coin cell. CAN/LIN transceivers are not functional when using coin cell.
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• Integrated Open-Standard Serial and Debug Adapter (OpenSDA).
• Cortex 10-pin (0.05") SWD debug port for target MCU.
• Cortex 10-pin (0.05") JTAG port for OpenSDA updates.
• One RGB LED indicator.
• One red LED indicator.
• Two push-button switches.
• NXP TJA1057 high-speed CAN transceiver.
• NXP TJA1027 LIN 2.2A/SAE J2602 transceiver.
Figure 3 shows the main board features and Input/Output headers for the FRDM-KW36 board:
Figure 3. FRDM-KW36 component placement
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2.3 OpenSDA serial and debug
The FRDM-KW36 development board includes OpenSDA v2.2- a serial and debug adapter circuit that includes an open-source
hardware design, an open-source bootloader, and debug interface software. It bridges serial and debug communications between
a USB host and an embedded target processor as shown in Figure 4. The hardware circuit is based on an NXP Kinetis K20 family
MCU (MK20DX128VFM5) with 128 KB of embedded flash and an integrated USB controller. OpenSDAv2.2 comes preloaded
with the DAPLink bootloader - an open-source Mass Storage Device (MSD) bootloader and the CMSIS-DAP Interface firmware,
which provides a MSD flash programming interface, a virtual serial port interface, and a CMSIS-DAP debug protocol interface.
For more information on the OpenSDAv2.2 software, see mbed.org, https://github.com/mbedmicro/DAPLink.
Figure 4. OpenSDAv2.2 high-level block diagram
OpenSDAv2.2 is managed by a Kinetis K20 MCU built on the Arm Cortex-M4 core. The OpenSDAv2.2 circuit includes a status
LED (D1) and a pushbutton (SW1). The pushbutton asserts the Reset signal to the KW36 target MCU. It can also be used to
place the OpenSDAv2.2 circuit into bootloader mode. UART and GPIO signals provide an interface to either the SWD debug port
or the K20. The OpenSDAv2.2 circuit receives power when the USB connector J11 is plugged into a USB host.
2.3.1 Virtual serial port
A serial port connection is available between the OpenSDAv2.2 MCU and pins PTC6 and PTC7 of the KW36.
To enable the Virtual COM, Debug, and MSD features, mbed drivers must be installed. Download the drivers at
https://developer.mbed.org/handbook/Windows-serial-configuration.
NOTE
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3 Functional description
The four-layer board provides the KW36 with its required RF circuitry, 32 MHz reference oscillator crystal, and power supply with
a DC-DC converter including Bypass and Buck modes. The layout for this base-level functionality can be used as a reference
layout for your target board.
3.1 RF circuit
The FRDM-KW36 RF circuit provides an RF interface for users to begin application development. A minimum matching network
to the MCU antenna pin is provided through C50, C51 and L2 to match the printed F-antenna to a 50 Ω controlled line.
The RF matching is different depending of the RF output power targeted. In case of the maximum RF output power
is lower than +3.5 dBm, 2 components is recommended.
NOTE
This is the default mounting components on the FRDM-KW36.
In case of maximum RF output power is between +3.5 dBm and +5 dBm, it’s recommended to use 3 components for the RF
matching.
Maximum RF output power <=+3.5 dBm 2 components RF matching
C50=0.8 pF, L2=4.7 nH, C51=DNP
Refer to Figure 5.
+3.5 dBm < Maximum RF output power < +5 dBm 3 components RF matching
C50=0.6 pF, L2=4.7 nH, C51=0.3 pF
Refer to Figure 6.
An optional SMA is located at J21. This is enabled by rotating the 10-pF capacitor in C55 to the location of C57. Figure 5 and
Figure 6 show the RF circuit in details.
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Figure 5. FRDM-KW36 RF circuit - 2 components
Figure 6. FRDM-KW36 RF circuit - 3 components
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3.1.1 RF path with matching components
RF matching needs to be adjusted to be able to reach sensitivity performances on the FRDM-KW36 board Rev B and Rev B1.
Original component values are L2 = 5.1 nH & C50=0.7 pF.
Measurements are done using the SMA connector. Therefore, the C57 capacitor is mounted and the C55 capacitor is not
mounted.
Figure 7. Matching components
Matching components must be: L2 = 4.7 nH & C50 = 0.6 pF. The following tables show the tested components to achieve proper
sensitivity performance.
• L2 = 4.7 nH
Description Mfr. name Mfr. part number
IND -- 0.0047 mH @ 500 MHz 300 mA
+/-0.1 nH 0402
MURATA LQP15MN4N7B02
• C50 = 0. 6 pF
Description Mfr. name Mfr. part number
CAP CER 0.6 pF 50 V 0.1 pF C0G 0402 MURATA GRM1555C1HR60BA01D
3.1.1.1 Current hardware: FRDM-KW36 Rev. B & B1 results
Figure 8 and Figure 9 show the results when using L2 = 5.1 nH & C50 = 0.7 pF.
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Figure 8. S11 diagram (Rx mode)
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Figure 9. S11 diagram (Tx mode)
Results:
• Rx r eturn loss: -13.6 dB (2.4 GHz) < S11 < -6.5 dB (2.48 GHz)
• Tx r eturn loss: -9.08 dBm (2.48 GHz) < S11 < -21.7 dB (2.4 GHz)
RF matching is not set correctly on this PCB revision. Sensitivity is around -94 dBm instead of -95 dBm.
3.1.1.2 Modified hardware: FRDM-KW36 Rev. B & B1 results
Figure 10 and Figure 11 show the results when using L2 = 4.7 nH & C50 = 0.6 pF.
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Figure 10. S11 diagram (Rx mode)
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Figure 11. S11 diagram (Tx mode)
Results:
• Rx r eturn loss: -11.8 dB (2.4 GHz) < S11 < -19 dB (2.48 GHz)
• Tx r eturn loss: -17.2 dBm (2.48 GHz) < S11 < -17.5 dB (2.4 GHz)
RF matching shows good results on this PCB revision. Sensitivity could reach -95 dBm.
3.2 Clocks
The FRDM-KW36 board provides two clocks. A 32 MHz for clocking the MCU and Radio, and a 32.768 kHz to provide an accurate
low power time base.
Figure 12. FRDM-KW36 32 MHz reference oscillator circuit
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• 32 MHz Reference Oscillator
—Figure 12 shows the 32 MHz external crystal Y1. The Bluetooth LE specification requires the frequency to be
accurate less than ±50 ppm. The FRDM-KW36 is equipped with a ±10 ppm oscillator.
— Internal load capacitors provide the crystal load capacitance. The internal load capacitors are adjustable which
allows the center frequency of the crystal to be tuned.
— To measure the 32 MHz oscillator frequency, program the CLKOUT (PTB0) signal to provide buffered output clock
signal.
Figure 13. FRDM-KW36 32.786 kHz oscillator circuit
• 32.768 kHz Crystal Oscillator (required to support radio deep sleep mode)
— 32.768 kHz crystal Y2 is provided (see Figure 13).
— Internal load capacitors provide the entire crystal load capacitance.
3.3 Power management
There are several ways to power and measure current on the FRDM-KW36 board. Figure 14 shows the FRDM-KW36 power-
management circuit.
Figure 14. FRDM-KW36 power management circuit
The FRDM-KW36 can be powered by the following means:
• Through the micro USB type B connector (J11), which provides 5 V to the P5V_SDA_PSW signal into the 3V3 LDO (U16).
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• Through the Freedom development board header J3 pin-8 by supplying voltage on signal P5-9V_VIN, this would supply
the FRDM-KW36 through LDO 3V3 (U16).
— An external LDO can be populated on header J26 to regulate P5-9V_VIN which feedbacks to header J3 pin-5
(P5V_USB). This LDO is not provided.
• From an external battery (Coin-cell – CR2032). Use selector J35 pins 2-3.
• From an external DC supply in the following ways:
— Connect an adapter that can supply 1.71 to 3.6 VDC to J35 pin 2. If the KW36 DC-DC is configured in buck mode,
then, the voltage should be in the range of 2.1 V to 3.6 V.
— Connect an adapter that can supply 12V to the connector J32, J23 pin 3 or J13 pin 2. This option is to power
CAN/LIN functionality in the board. At the same time, it also provides voltage to the regulator U15 which provides 5V
signal to P5V that also powers the KW36 through P3V3_LDO (U16). J35 needs to be in 1-2 position.
The jumper/headers J28 and J24 can supply current to various board components and can be used to measure the current (if
desired). Green LED marked as LED2 is available as a power indicator.
Power headers (J24, J28 and J35) can supply either the LED, MCU, or peripheral circuits. Measure the current by inserting a
current meter in place of a designated jumper. See Table 4 for details on jumper descriptions.
The FRDM-KW36 can be configured to use any of the DCDC converter operating modes. These modes are Bypass, Buck
(Manual-Start) and Buck (Auto-Start). Figure 15, Figure 16, Figure 17, and Table 1 highlight the jumper settings for each of these
modes. The board is configured in Buck (Auto-Start) by default. If different DCDC mode is desired, cut traces (bottom layer of
the board) and jumpers (J27, J28, J29, J30, J31 and J38) should be populated to be able to configure the desired DCDC mode.
Figure 15. Jumper settings for Bypass mode
Figure 16. Jumper settings for Buck mode (manual start)
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Figure 17. Jumper settings for Buck mode (auto start)
Table 1 describes the DCDC mode jumper configurations.
Table 1. DCDC configurations
DCDC operating mode PSW_CFG
J38
REG_CFG
J27
REG_CFG
J30
Bypass mode 1-2 ON ON
Buck mode (manual start) 1-2 OFF OFF
Buck mode (auto start) 2-3 OFF OFF
By default, the FRDM-KW36 is configured in Buck mode (auto start). When device is in Buck mode, the VDD pins are supplied
by VDD_1P8OUT pin. This pin is configured to 1.8 V by default, if higher voltage domain is desired, the DCDC software driver
can be configured to provide different voltages on its outputs. Please, refer to Connectivity Framework Reference Manual which
is part of the FRDM-KW36 SDK documentation for details about DCDC software driver. For more details about the DCDC module
operation, refer to AN5025.
3.4 Serial flash memory
Component U3 is the AT45DB041E 4-Mbit (512 KB) serial flash memory with SPI interface. It is intended for Over-the-Air
Programming (OTAP) or for storing non-volatile system data, or parameters.
Figure 18 shows the memory circuit:
• Memory power supply is P1V8_3V3_BRD.
• Discrete pull-up resistors pads for SPI port.
• You can share the SPI with other peripherals using the J1 I/O header.
• The SPI Write Protect and Reset have a discrete pull-up resistor.
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Figure 18. AT45DB041E 4-Mbit (512 KB) serial flash memory circuit
3.5 Acceleromater and magnetometer combo sensor
Component U11 is an NXP FXOS8700CQ sensor, a six-axis sensor with integrated linear accelerometer and magnetometer with
very low power consumption, and selectable I2C/SPI interface.
Figure 19 shows the sensor circuit.
• The sensor is powered by the P1V8_3V3_BRD rail.
• Discrete pull-up resistors for the I2C bus lines are provided.
• Default address is configured as 0x1F:
— Address can be changed by pull-up/pull-down resistors on SA0 and SA1 lines.
• There is one interrupt signal routed to PTA19 pin of KW36.
• The I2C can be shared with other peripherals through the J4 I/O header.
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Figure 19. FXOS8700CQ combo sensor circuit
FXOS8700CQ requires above 2.0 V to work. Make sure that DCDC software driver is configured to supply such
voltage. DCDC software driver is part of the FRDM-KW36 SDK.
NOTE
3.6 Thermistor
One thermistor (RT1) is connected to a differential ADC input (ADC0_DP0 & ADC_DM0) of KW36 for ADC module evaluation.
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Figure 20. Thermistor circuit
3.7 User application LEDs
The FRDM-KW36 provides a RGB LED and a single Red LED for user applications. Figure 21 and Figure 22 show the circuitry
for the application controlled LEDs.
Figure 21. FRDM-KW36 RGB LED circuit
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Figure 22. FRDM-KW36 RGB LED3 circuit
When operating in default Buck configuration, the MCU would be operating at 1.8 V, which means that GPIO would
be operating at 1.8 V. The LED circuitry allows proper behavior of the LEDs if P_LED is connected to V_MAIN with
J24 in 1-2 position. The V_MAIN voltage should be at 3.3 V to work properly.
NOTE
3.8 Interrupt pushbuttons
Two tactile buttons are populated on the FRDM-KW36 for Human Machine Interaction (HMI). Figure 23 shows the circuit for the
tactile buttons.
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Figure 23. FRDM-KW36 HMI circuit
3.9 CAN/LIN power
As discussed in Power management, the FRDM-KW36 can be powered through the J32, J23 pin 3 or J13 pin 2. The connector
J32 is meant to be used as the power supply for the CAN and LIN interfaces. U15 is used to generates the P5V signal that CAN
interface requires as per CAN physical requirements. P12V_BAT is used to supply the LIN transceiver as per LIN voltage domain.
Figure 24 show sthe CAN/LIN power circuit.
The P5V signal also goes to the regulator U16 to generate P3V3_LDO to supply KW36 if J35 is set to 1-2 configuration.
Figure 24. CAN power circuit
P12V signal can be also supplied through J23 pin 3 or J13 pin 2. Only one power input shall be chosen to supply
P12V voltage (J32 or J23 or J13).
NOTE
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