NXP Semiconductors QorIQ LX2160A User manual

QorIQ LX2160A Reference Design Board
Reference Manual
Supports LX2160ARDB Revision B
NXP Semiconductors Document identifier: LX2160ARDBRM
Reference Manual Rev. 4, 07/2020

Contents
Chapter 1 LX2160ARDB Overview........................................................................3
Chapter 2 LX2160ARDB Functional Description................................................. 10
Chapter 3 Qixis Programming Model...................................................................56
Appendix A Revision History..............................................................................115
NXP Semiconductors
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 2 / 116

Chapter 1
LX2160ARDB Overview
The QorIQ® LX2160A reference design board (RDB) provides a comprehensive platform that enables design and evaluation of
the QorIQ LX2160A processor. The LX2160ARDB comes preloaded with Layerscape software development kit (LSDK) image.
The board comes in a 1U rackmount chassis form factor. It is lead-free and RoHS-compliant.
The board:
• Enables network intelligence with the next generation Datapath (DPPA2) which provides differentiated offload and a rich
set of input/output, including 10/25/40 Gigabit Ethernet and PCIe Gen 3
• Delivers unprecedented efficiency and new virtualized networks
• Supports designs in 5G packet processing, network function virtualization, storage controller, white box switching, network
interface cards, and mobile edge computing
• Supports all three LX2 family members (16-core LX2160A, 12-core LX2120A, and 8-core LX2080A)
This document provides detailed information about LX2160ARDB interfaces, power supplies, clocks, DIP switches, LEDs, and
CPLD system controller.
1.1 Acronyms and abbreviations
The table below lists and explains the acronyms and abbreviations used in this document.
Table 1. Acronyms and abbreviations
Term Description
ATX Advanced Technology eXtended
CAN Controller area network
CCI Cache coherency interconnect
CCS CodeWarrior connection server
CPLD Complex programmable logic device
CTS Clear to send
DCM Development system control monitor
DDR SDRAM Double data rate synchronous dynamic random-access memory
DIMM Dual inline memory module
DIP Dual inline package
DPAA Data path acceleration architecture
DUT Device under test
EC Ethernet controller
ECC Error correcting code
ECID Electronic chip identification
EDINK e500 core demonstrative interactive nanokernel
EMI Ethernet management interface
Table continues on the next page...
NXP Semiconductors
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 3 / 116

Table 1. Acronyms and abbreviations (continued)
Term Description
eMMC Embedded multimedia card
eSDHC Enhanced secure digital host controller
FET Field-effect transistor
FlexSPI Flexible serial peripheral interface
FPGA Field-programmable gate array
GbE Gigabit Ethernet
GPIO General purpose input/output
HDLC High-level data link control
HSSI High-speed serial interface
I2C Inter-integrated circuit
JTAG Joint Test Action Group (IEEE® Standard 1149.1™)
LOS Loss of signal
MDIO Management data input/output
OCM Offline configuration manager
OTG On-The-Go
PBL Pre-boot loader
PLL Phase-locked loop
POR Power-on reset
PSU Power supply unit
PTP Precision time protocol
PWM Pulse width modulation
QSPI Quad serial peripheral interface
RCW Reset configuration word
RDIMM Registered dual inline memory module
RTC Real time clock
RTS Request to send
SATA Serial advanced technology attachment
SDRAM Synchronous dynamic random-access memory
SerDes Serializer/deserializer
SGMII Serial gigabit media independent interface
SPD Serial presence detect
SPI Serial peripheral interface
Table continues on the next page...
NXP Semiconductors
LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 4 / 116

Table 1. Acronyms and abbreviations (continued)
Term Description
SS Spread spectrum
SSC Spread spectrum clocking
TCXO Temperature compensated crystal (Xtal) oscillator
UART Universal asynchronous receiver/transmitter
UDIMM Unbuffered dual inline memory module
UFT Universal frequency translator
USB Universal serial bus
USXGMII Universal serial 10 gigabit media independent interface
XGT 10GBase-T
XSPI Octal serial peripheral interface
1.2 Related documentation
The table below lists and explains the additional documents and resources that you can refer to for more information on the
LX2160ARDB. Some of the documents listed below may be available only under a non-disclosure agreement (NDA). To request
access to these documents, contact your local NXP field applications engineer (FAE) or sales representative.
Table 2. Related documentation
Document Description Link / how to access
QorIQ LX2160A Reference Design
Board Getting Started Guide
Explains the LX2160ARDB settings and physical connections
needed to boot the board
LX2160ARDBGSG.pdf
QorIQ LX2160A Reference Design
Board Errata
Describes known errata and workarounds for the
LX2160ARDB
LX2160ARDBE.pdf
QorIQ LX2160A Product Brief Provides a brief overview of the LX2160A processor LX2160APB.pdf
QorIQ LX2160A Data Sheet Provides information about electrical characteristics,
hardware design considerations, and ordering information
Contact NXP FAE /
sales representative
QorIQ LX2160A Reference Manual Provides a detailed description about the LX2160A QorIQ
multicore processor and its features, such as memory map,
serial interfaces, power supply, chip features, and clock
information
Contact NXP FAE /
sales representative
QorIQ LX2160A Chip Errata Lists the details of all known silicon errata for the LX2160A Contact NXP FAE /
sales representative
QorIQ LX2160A Design Checklist,
AN5407
Provides recommendations for new designs based on the
LX2160A. This document can also be used to debug newly
designed systems by highlighting those aspects of a design
that merit special attention during initial system start-up.
Contact NXP FAE /
sales representative
Layerscape Software Development
Kit User Guide
Describes how to work with LSDK, which is a complete Linux
kit for NXP QorIQ Arm-based SoCs and the reference and
evaluation boards available for them.
LSDKUG.pdf
Table continues on the next page...
NXP Semiconductors
LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 5 / 116

Table 2. Related documentation (continued)
Document Description Link / how to access
CodeWarrior Development Studio
for QorIQ LS series - ARM V8 ISA,
Targeting Manual
Explains how to use the CodeWarrior Development Studio for
QorIQ LS series - ARM V8 ISA product.
CWARMv8TM.pdf
CodeWarrior TAP Probe User
Guide
Provides details of CodeWarrior® TAP, which enables target
system debugging through a standard debug port (usually
JTAG) while connected to a developer workstation through
Ethernet or USB
CWTAPUG.pdf
1.3 Block diagram
The figure below shows the LX2160ARDB block diagram.
Qualcomm
AR8035
Aquantia
AQR107
PCIe x4 slot
Gen 1-3
LX2160A
Power supplies
VDD USB_HVDD
GVDD SD_SVDD
OVDD
USB 3.0
type A
SDHC
1
JTAG
RS232 IO
USB
3.0
I2C1
I2C devices
SPD SFP+
INA220 Temp
Fan PWM DCM
Qix CPLD Clocks
SystemID
UART
DB9 stack
JTAG
x4
Inphi
CS4223
SDHC
2
PWR
QSFP+
40G-SR4
40G-CR4
40G-KR4
S
E
R
D
E
S
1
12V
5V
3.3V
5VSB
RST
Dual RJ45
USXGMII
2x 10G
QixMin CPLD
system controller
Dual cage
SFP+
2x 25G
x4
CFG
C
L
O
C
K
S
uATX
Switches
USB 3.0
micro AB
SD slot
eMMC
128 GB
Aquantia
AQR107
Inphi
IN112525
x2
x2
x4
x2
x2
H,G
0,1
F,E
2,3
D-A
4-7
x4
S
E
R
D
E
S
2
A-D
0-3
E-H
4-7
S
E
R
D
E
S
3
PCIe x8 slot
Gen 1-3
x8
A-H
0-7
Protocol #19
Protocol #5
Protocol #2
DDR
1
DDR4 slot
288 pins
DDR
2
DDR4 slot
288 pins
x2
x2
x2
DB9 stack CAN IO
x2 CAN1
CAN2
Up to 32 GB at 3200 MT/s
Qualcomm
AR8035 Dual RJ45
2x 1G
RGMII
HS
Mux
HS
mux IEEE
header
HS
Mux
HS
mux
XSPI
A
SPI
emulator
MT35XU512
XSPI 64 MB
MT35XU512
XSPI 64 MB
Up to 32 GB at 3200 MT/s
SD1
161.13 MHz
SYS
DDR
100.00 MHz
SiliconLabs
Si52208
SD2
100 MHz
SD3
100 MHz
To
slots
125.00 MHz EC
To
10G
25G
40G
PHYs
UEFI memory
1 MB
PWM fans
100.00 MHz
SiliconLabs
Si5341
156.25 MHz
100.00 MHz
25.00 MHz
SATA 3.0SATA 3.0
I2C5
RTC
Figure 1. LX2160ARDB block diagram
NXP Semiconductors
LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 6 / 116

1.4 Board features
The table below lists the features of the LX2160ARDB.
Table 3. LX2160ARDB features
LX2160ARDB feature Specification Description
Processor LX2160A processor QorIQ LX2160A processor, supporting speeds of up to 2.2 GHz.
For more details on the LX2160A processor, see QorIQ
LX2160A Reference Manual .
NOTE
DDR memory Two 72-bit DDR4
ports (64-bit data, 8-
bit ECC)
Each DDR4 port supports:
• Two 288-pin DIMM connectors, one supporting four chip selects and
other supporting two chip selects
• Single-/dual-/quad-rank, unbuffered/registered DDR4 memory
modules with 8-/16-bit data width
Quad rank is only supported if the second DIMM
connector of a DDR4 port is left unused.
NOTE
• 64-bit data and 8-bit ECC
• Data rates of up to 3.2 GigaTransfers/second (GT/s)
High-speed serial ports
(SerDes)
Three SerDes
controllers (24 lanes)
• SerDes1:
— Lanes 0-1: Supports two 10 GbE RJ45 USXGMII connectors,
each connected through an Aquantia AQR107 PHY
— Lanes 2-3: Supports two 25 GbE SFP+ modules, connected
through an Inphi IN112525 PHY
— Lanes 4-7: Supports one 40 GbE (40G-SR4, 40G-CR4, or 40G-
KR4) QSFP+ module, connected through an Inphi CS4223 PHY
• SerDes2:
— Lanes 0-3: Supports one PCIe x4 (Gen 1/2/3) connector
— Lanes 4-7: Supports four SATA 3.0 connectors
• SerDes3:
— Lanes 0-7: Supports one PCIe x8 (Gen 1/2/3) connector
• Each SerDes lane supports speeds of up to 25 GHz
eSDHC eSDHC1 Supports a secure digital (SD) connector (J42) for connecting an SD card
eSDHC2 Supports 128 GB Micron MTFC128GAJAECE-IT embedded multimedia
card (eMMC), supporting HS-400 high-speed transfer mode
Octal SPI (XSPI) One XSPI controller
(XSPI_A)
• Supports two 64 MB onboard octal SPI flash memories
• Supports a QSPI emulator for offboard QSPI emulation
Table continues on the next page...
NXP Semiconductors
LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 7 / 116

Table 3. LX2160ARDB features (continued)
LX2160ARDB feature Specification Description
I2C Six I2C controllers
(I2C1, I2C2, I2C3,
I2C4, I2C5, and I2C6)
• Most system devices (other than UEFI) are accessed via I2C1, which
is multiplexed to isolate address conflicts and reduce capacitive load
• I2C1 is translated to 3V3_SB, allowing programming access to
devices, such as power controllers, clocks, and memories, while the
system is off
• I2C2 is only used for SDHC1_CD_B and SDHC1_WP
• I2C3 is only used for CAN1 input/output
• I2C4 is only used for CAN2 input/output
• I2C5 is used for UEFI support (memory and RTC)
• I2C6 is used for optional AQR107 PHY access
Serial ports Two UART ports
(UART1 and UART2)
A dual-stack DB9 male connector providing two UART connectors, each
connected through an RS-232 transceiver
USB 3.0 Two high-speed USB
3.0 ports with
integrated PHYs
• Supports super-speed (5 Gbit/s), high-speed (480 Mbit/s), full-speed
(12 Mbit/s), and low-speed (1.5 Mbit/s) operations
• USB#1 3.0 port is connected to a Type A host connector
• USB#2 3.0 port is configured as On-The-Go (OTG) with a Micro-AB
connector
Ethernet Two tri-speed RGMII
interfaces
• 10 Mb / 100 Mb / 1 Gb Ethernet is supported
• An RJ45 connector with link and activity status is used with each
RGMII interface
• IEEE 1588™ precision time protocol (PTP) is supported through an
onboard header (J29)
Clocks System clock
(SYSCLK) and DDR
clock (DDRCLK)
• 100 MHz differential clock to DIFF_SYSCLK
• 100 MHz single-ended clock to DDRCLK
SerDes clocks • 161.1328125 MHz clock to SerDes1 PLL 1 and PLL 2
• 100 MHz clock to SerDes2 PLL 1 and PLL 2
• 100 MHz clock to SerDes3 PLL 1 and PLL 2
• 100 MHz clock to AQR107 10 GbE PHY 1 and 2
• 25 MHz clock to IN112525 25 GbE PHY
• 156.25 MHz clock to CS4223 40 GbE PHY
• 100 MHz clock to x4 and x8 PCIe slots
Ethernet clocks 125 MHz clocks to Ethernet controllers and IEEE 1588 port
Power supplies • 12 V, 5 V, 3.3 V, and 5 V (standby) ATX power supplies
• 0.8 V (VDD) for the LX2160A core
Table continues on the next page...
NXP Semiconductors
LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 8 / 116

Table 3. LX2160ARDB features (continued)
LX2160ARDB feature Specification Description
• 1.2 V (G1VDD and G2VDD) for DDR4
• 0.92 V (SD_SVDD) for SerDes cores
• 1.8 V (SD_OVDD) for SerDes I/O drivers
• 0.9 V (SD_AVDD) for SerDes PLLs
• 1.8 V (OVDD) for general I/O
• 1.8 V (standby) and 3.3 V (standby) for CPLD core and I/O
• 0.8 V for USB_SVDD and USB_SDVDD
• 3.3 V for USB_HVDD
• 0.8 V (TA_BB_VDD) for the LX2160A secure monitor
• 1.8 V for TA_PROG_SFP and PROG_MTR
Debug features Arm Cortex 10-pin JTAG connector
System logic CPLD • Manages the following:
— System power sequencing
— System reset sequencing
— System and SerDes clock speed selections
— SoC POR configuration at reset
• Implements registers for system control and monitoring
• General fault monitoring and logging
1.5 Board top view
The figure below shows the top-side view of the LX2160ARDB.
Figure 2. LX2160ARDB top view
NXP Semiconductors
LX2160ARDB Overview
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 9 / 116

Chapter 2
LX2160ARDB Functional Description
The LX2160ARDB architecture is primarily determined by the LX2160A processor, with the need to evaluate the LX2160A
processor features and to deliver an easily usable, off-the-shelf software development platform.
This chapter explains all major functional components of the LX2160ARDB. The chapter is divided into the following sections:
•Power supplies
•Clocks
•DDR interface
•SerDes interface
•Ethernet controller interface
•Ethernet management interface
•eSDHC interface
•XSPI interface
•USB interface
•I2C interface
•UART interface
•CAN interface
•JTAG port
•Interrupt controller
•GPIO access
•Temperature measurement
•LEDs
•DIP switches
•System controller
2.1 Power supplies
The LX2160ARDB provides all the voltages necessary for the correct operation of the LX2160A processor, DDR4 UDIMM, PHYs,
and numerous other peripherals. All power is derived from an external power supply, which supplies bulk +12 V, +5 V, +3.3 V,
as well as +5 V standby power.
The ATX-compatible supply is managed by the system controller CPLD and drives the power supplies shown in the figures below.
NXP Semiconductors
QorIQ LX2160A Reference Design Board Reference Manual, Rev. 4, 07/2020
Reference Manual 10 / 116