NXP Semiconductors QorIQ LX2160A User manual

QorIQ LX2160A Reference Design Board
Reference Manual
Supports LX2160ARDB Revision B
NXP Semiconductors Document identifier: LX2160ARDBRM
Reference Manual Rev. 4, 07/2020

Contents
Chapter 1 LX2160ARDB Overview........................................................................3
Chapter 2 LX2160ARDB Functional Description................................................. 10
Chapter 3 Qixis Programming Model...................................................................56
Appendix A Revision History..............................................................................115
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Chapter 1
LX2160ARDB Overview
The QorIQ® LX2160A reference design board (RDB) provides a comprehensive platform that enables design and evaluation of
the QorIQ LX2160A processor. The LX2160ARDB comes preloaded with Layerscape software development kit (LSDK) image.
The board comes in a 1U rackmount chassis form factor. It is lead-free and RoHS-compliant.
The board:
• Enables network intelligence with the next generation Datapath (DPPA2) which provides differentiated offload and a rich
set of input/output, including 10/25/40 Gigabit Ethernet and PCIe Gen 3
• Delivers unprecedented efficiency and new virtualized networks
• Supports designs in 5G packet processing, network function virtualization, storage controller, white box switching, network
interface cards, and mobile edge computing
• Supports all three LX2 family members (16-core LX2160A, 12-core LX2120A, and 8-core LX2080A)
This document provides detailed information about LX2160ARDB interfaces, power supplies, clocks, DIP switches, LEDs, and
CPLD system controller.
1.1 Acronyms and abbreviations
The table below lists and explains the acronyms and abbreviations used in this document.
Table 1. Acronyms and abbreviations
Term Description
ATX Advanced Technology eXtended
CAN Controller area network
CCI Cache coherency interconnect
CCS CodeWarrior connection server
CPLD Complex programmable logic device
CTS Clear to send
DCM Development system control monitor
DDR SDRAM Double data rate synchronous dynamic random-access memory
DIMM Dual inline memory module
DIP Dual inline package
DPAA Data path acceleration architecture
DUT Device under test
EC Ethernet controller
ECC Error correcting code
ECID Electronic chip identification
EDINK e500 core demonstrative interactive nanokernel
EMI Ethernet management interface
Table continues on the next page...
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Table 1. Acronyms and abbreviations (continued)
Term Description
eMMC Embedded multimedia card
eSDHC Enhanced secure digital host controller
FET Field-effect transistor
FlexSPI Flexible serial peripheral interface
FPGA Field-programmable gate array
GbE Gigabit Ethernet
GPIO General purpose input/output
HDLC High-level data link control
HSSI High-speed serial interface
I2C Inter-integrated circuit
JTAG Joint Test Action Group (IEEE® Standard 1149.1™)
LOS Loss of signal
MDIO Management data input/output
OCM Offline configuration manager
OTG On-The-Go
PBL Pre-boot loader
PLL Phase-locked loop
POR Power-on reset
PSU Power supply unit
PTP Precision time protocol
PWM Pulse width modulation
QSPI Quad serial peripheral interface
RCW Reset configuration word
RDIMM Registered dual inline memory module
RTC Real time clock
RTS Request to send
SATA Serial advanced technology attachment
SDRAM Synchronous dynamic random-access memory
SerDes Serializer/deserializer
SGMII Serial gigabit media independent interface
SPD Serial presence detect
SPI Serial peripheral interface
Table continues on the next page...
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Table 1. Acronyms and abbreviations (continued)
Term Description
SS Spread spectrum
SSC Spread spectrum clocking
TCXO Temperature compensated crystal (Xtal) oscillator
UART Universal asynchronous receiver/transmitter
UDIMM Unbuffered dual inline memory module
UFT Universal frequency translator
USB Universal serial bus
USXGMII Universal serial 10 gigabit media independent interface
XGT 10GBase-T
XSPI Octal serial peripheral interface
1.2 Related documentation
The table below lists and explains the additional documents and resources that you can refer to for more information on the
LX2160ARDB. Some of the documents listed below may be available only under a non-disclosure agreement (NDA). To request
access to these documents, contact your local NXP field applications engineer (FAE) or sales representative.
Table 2. Related documentation
Document Description Link / how to access
QorIQ LX2160A Reference Design
Board Getting Started Guide
Explains the LX2160ARDB settings and physical connections
needed to boot the board
LX2160ARDBGSG.pdf
QorIQ LX2160A Reference Design
Board Errata
Describes known errata and workarounds for the
LX2160ARDB
LX2160ARDBE.pdf
QorIQ LX2160A Product Brief Provides a brief overview of the LX2160A processor LX2160APB.pdf
QorIQ LX2160A Data Sheet Provides information about electrical characteristics,
hardware design considerations, and ordering information
Contact NXP FAE /
sales representative
QorIQ LX2160A Reference Manual Provides a detailed description about the LX2160A QorIQ
multicore processor and its features, such as memory map,
serial interfaces, power supply, chip features, and clock
information
Contact NXP FAE /
sales representative
QorIQ LX2160A Chip Errata Lists the details of all known silicon errata for the LX2160A Contact NXP FAE /
sales representative
QorIQ LX2160A Design Checklist,
AN5407
Provides recommendations for new designs based on the
LX2160A. This document can also be used to debug newly
designed systems by highlighting those aspects of a design
that merit special attention during initial system start-up.
Contact NXP FAE /
sales representative
Layerscape Software Development
Kit User Guide
Describes how to work with LSDK, which is a complete Linux
kit for NXP QorIQ Arm-based SoCs and the reference and
evaluation boards available for them.
LSDKUG.pdf
Table continues on the next page...
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Table 2. Related documentation (continued)
Document Description Link / how to access
CodeWarrior Development Studio
for QorIQ LS series - ARM V8 ISA,
Targeting Manual
Explains how to use the CodeWarrior Development Studio for
QorIQ LS series - ARM V8 ISA product.
CWARMv8TM.pdf
CodeWarrior TAP Probe User
Guide
Provides details of CodeWarrior® TAP, which enables target
system debugging through a standard debug port (usually
JTAG) while connected to a developer workstation through
Ethernet or USB
CWTAPUG.pdf
1.3 Block diagram
The figure below shows the LX2160ARDB block diagram.
Qualcomm
AR8035
Aquantia
AQR107
PCIe x4 slot
Gen 1-3
LX2160A
Power supplies
VDD USB_HVDD
GVDD SD_SVDD
OVDD
USB 3.0
type A
SDHC
1
JTAG
RS232 IO
USB
3.0
I2C1
I2C devices
SPD SFP+
INA220 Temp
Fan PWM DCM
Qix CPLD Clocks
SystemID
UART
DB9 stack
JTAG
x4
Inphi
CS4223
SDHC
2
PWR
QSFP+
40G-SR4
40G-CR4
40G-KR4
S
E
R
D
E
S
1
12V
5V
3.3V
5VSB
RST
Dual RJ45
USXGMII
2x 10G
QixMin CPLD
system controller
Dual cage
SFP+
2x 25G
x4
CFG
C
L
O
C
K
S
uATX
Switches
USB 3.0
micro AB
SD slot
eMMC
128 GB
Aquantia
AQR107
Inphi
IN112525
x2
x2
x4
x2
x2
H,G
0,1
F,E
2,3
D-A
4-7
x4
S
E
R
D
E
S
2
A-D
0-3
E-H
4-7
S
E
R
D
E
S
3
PCIe x8 slot
Gen 1-3
x8
A-H
0-7
Protocol #19
Protocol #5
Protocol #2
DDR
1
DDR4 slot
288 pins
DDR
2
DDR4 slot
288 pins
x2
x2
x2
DB9 stack CAN IO
x2 CAN1
CAN2
Up to 32 GB at 3200 MT/s
Qualcomm
AR8035 Dual RJ45
2x 1G
RGMII
HS
Mux
HS
mux IEEE
header
HS
Mux
HS
mux
XSPI
A
SPI
emulator
MT35XU512
XSPI 64 MB
MT35XU512
XSPI 64 MB
Up to 32 GB at 3200 MT/s
SD1
161.13 MHz
SYS
DDR
100.00 MHz
SiliconLabs
Si52208
SD2
100 MHz
SD3
100 MHz
To
slots
125.00 MHz EC
To
10G
25G
40G
PHYs
UEFI memory
1 MB
PWM fans
100.00 MHz
SiliconLabs
Si5341
156.25 MHz
100.00 MHz
25.00 MHz
SATA 3.0SATA 3.0
I2C5
RTC
Figure 1. LX2160ARDB block diagram
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1.4 Board features
The table below lists the features of the LX2160ARDB.
Table 3. LX2160ARDB features
LX2160ARDB feature Specification Description
Processor LX2160A processor QorIQ LX2160A processor, supporting speeds of up to 2.2 GHz.
For more details on the LX2160A processor, see QorIQ
LX2160A Reference Manual .
NOTE
DDR memory Two 72-bit DDR4
ports (64-bit data, 8-
bit ECC)
Each DDR4 port supports:
• Two 288-pin DIMM connectors, one supporting four chip selects and
other supporting two chip selects
• Single-/dual-/quad-rank, unbuffered/registered DDR4 memory
modules with 8-/16-bit data width
Quad rank is only supported if the second DIMM
connector of a DDR4 port is left unused.
NOTE
• 64-bit data and 8-bit ECC
• Data rates of up to 3.2 GigaTransfers/second (GT/s)
High-speed serial ports
(SerDes)
Three SerDes
controllers (24 lanes)
• SerDes1:
— Lanes 0-1: Supports two 10 GbE RJ45 USXGMII connectors,
each connected through an Aquantia AQR107 PHY
— Lanes 2-3: Supports two 25 GbE SFP+ modules, connected
through an Inphi IN112525 PHY
— Lanes 4-7: Supports one 40 GbE (40G-SR4, 40G-CR4, or 40G-
KR4) QSFP+ module, connected through an Inphi CS4223 PHY
• SerDes2:
— Lanes 0-3: Supports one PCIe x4 (Gen 1/2/3) connector
— Lanes 4-7: Supports four SATA 3.0 connectors
• SerDes3:
— Lanes 0-7: Supports one PCIe x8 (Gen 1/2/3) connector
• Each SerDes lane supports speeds of up to 25 GHz
eSDHC eSDHC1 Supports a secure digital (SD) connector (J42) for connecting an SD card
eSDHC2 Supports 128 GB Micron MTFC128GAJAECE-IT embedded multimedia
card (eMMC), supporting HS-400 high-speed transfer mode
Octal SPI (XSPI) One XSPI controller
(XSPI_A)
• Supports two 64 MB onboard octal SPI flash memories
• Supports a QSPI emulator for offboard QSPI emulation
Table continues on the next page...
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Table 3. LX2160ARDB features (continued)
LX2160ARDB feature Specification Description
I2C Six I2C controllers
(I2C1, I2C2, I2C3,
I2C4, I2C5, and I2C6)
• Most system devices (other than UEFI) are accessed via I2C1, which
is multiplexed to isolate address conflicts and reduce capacitive load
• I2C1 is translated to 3V3_SB, allowing programming access to
devices, such as power controllers, clocks, and memories, while the
system is off
• I2C2 is only used for SDHC1_CD_B and SDHC1_WP
• I2C3 is only used for CAN1 input/output
• I2C4 is only used for CAN2 input/output
• I2C5 is used for UEFI support (memory and RTC)
• I2C6 is used for optional AQR107 PHY access
Serial ports Two UART ports
(UART1 and UART2)
A dual-stack DB9 male connector providing two UART connectors, each
connected through an RS-232 transceiver
USB 3.0 Two high-speed USB
3.0 ports with
integrated PHYs
• Supports super-speed (5 Gbit/s), high-speed (480 Mbit/s), full-speed
(12 Mbit/s), and low-speed (1.5 Mbit/s) operations
• USB#1 3.0 port is connected to a Type A host connector
• USB#2 3.0 port is configured as On-The-Go (OTG) with a Micro-AB
connector
Ethernet Two tri-speed RGMII
interfaces
• 10 Mb / 100 Mb / 1 Gb Ethernet is supported
• An RJ45 connector with link and activity status is used with each
RGMII interface
• IEEE 1588™ precision time protocol (PTP) is supported through an
onboard header (J29)
Clocks System clock
(SYSCLK) and DDR
clock (DDRCLK)
• 100 MHz differential clock to DIFF_SYSCLK
• 100 MHz single-ended clock to DDRCLK
SerDes clocks • 161.1328125 MHz clock to SerDes1 PLL 1 and PLL 2
• 100 MHz clock to SerDes2 PLL 1 and PLL 2
• 100 MHz clock to SerDes3 PLL 1 and PLL 2
• 100 MHz clock to AQR107 10 GbE PHY 1 and 2
• 25 MHz clock to IN112525 25 GbE PHY
• 156.25 MHz clock to CS4223 40 GbE PHY
• 100 MHz clock to x4 and x8 PCIe slots
Ethernet clocks 125 MHz clocks to Ethernet controllers and IEEE 1588 port
Power supplies • 12 V, 5 V, 3.3 V, and 5 V (standby) ATX power supplies
• 0.8 V (VDD) for the LX2160A core
Table continues on the next page...
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Table 3. LX2160ARDB features (continued)
LX2160ARDB feature Specification Description
• 1.2 V (G1VDD and G2VDD) for DDR4
• 0.92 V (SD_SVDD) for SerDes cores
• 1.8 V (SD_OVDD) for SerDes I/O drivers
• 0.9 V (SD_AVDD) for SerDes PLLs
• 1.8 V (OVDD) for general I/O
• 1.8 V (standby) and 3.3 V (standby) for CPLD core and I/O
• 0.8 V for USB_SVDD and USB_SDVDD
• 3.3 V for USB_HVDD
• 0.8 V (TA_BB_VDD) for the LX2160A secure monitor
• 1.8 V for TA_PROG_SFP and PROG_MTR
Debug features Arm Cortex 10-pin JTAG connector
System logic CPLD • Manages the following:
— System power sequencing
— System reset sequencing
— System and SerDes clock speed selections
— SoC POR configuration at reset
• Implements registers for system control and monitoring
• General fault monitoring and logging
1.5 Board top view
The figure below shows the top-side view of the LX2160ARDB.
Figure 2. LX2160ARDB top view
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Chapter 2
LX2160ARDB Functional Description
The LX2160ARDB architecture is primarily determined by the LX2160A processor, with the need to evaluate the LX2160A
processor features and to deliver an easily usable, off-the-shelf software development platform.
This chapter explains all major functional components of the LX2160ARDB. The chapter is divided into the following sections:
•Power supplies
•Clocks
•DDR interface
•SerDes interface
•Ethernet controller interface
•Ethernet management interface
•eSDHC interface
•XSPI interface
•USB interface
•I2C interface
•UART interface
•CAN interface
•JTAG port
•Interrupt controller
•GPIO access
•Temperature measurement
•LEDs
•DIP switches
•System controller
2.1 Power supplies
The LX2160ARDB provides all the voltages necessary for the correct operation of the LX2160A processor, DDR4 UDIMM, PHYs,
and numerous other peripherals. All power is derived from an external power supply, which supplies bulk +12 V, +5 V, +3.3 V,
as well as +5 V standby power.
The ATX-compatible supply is managed by the system controller CPLD and drives the power supplies shown in the figures below.
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LX2160A VDD
Power
stage
VDD
0.5mW(7W)
PS_VDD_EN
PS_VDD_PG
LTC3882
I2C1_CH1
INA220INA220
Power
stage
from CPLD
VDDo
0.825V @ 70A
SMBALERT_B
LTC7150
PS_GVDD_EN
PS_GVDD_PG
from CPLD
12V0 VIN
LX2160A GVDD
VTT1 VDD
VTT2 VDD
DIMM[1:4] VDD
GVDD
0.5mW(7W)
MC34717EP/R2
PS_SD_VDD_EN
PS_SD_VDD_PG
SD_OVDD
1.80V @ 5A
LPFLPF
SD_OVDD_FLT
SD_VDD_FLT
LPFLPF
LPFx4LPFx4
AVDD_xyz
SD3_OVDD_FLT
from CPLD
5V0 VIN[1:2]
LX2160A SD3_OVDD
LX2160A SD_OVDD
SD_SVDD
0.92V @ 5A LX2160A SD_SVDD
LX2160A AVDD[1:5]
LX2160A AVDD_D[1:2]
LX2160A PROG_MTR
HDR 1x2
LX2160A TA_PROG_SFP
HDR 1x2 1K
1K
PS_SD_OVDD_SEL
LTC7150
PS_OVDD_EN
PS_OVDD_PG
from CPLD
12V0 VIN
LX2160A OVDD
LX2160A TH_VDD
LX2160A PROG_MTR
CS4223 40GE
AQR107_1 VDD_IO
AQR107_2 VDD_IO
XSPI / eMMC
OVDD
LPFLPF
SD3_VDD_FLT LX2160A SD3_SVDD
PS_SD_SVDD_SEL
LPFLPF
GVDDo
1.20V @ 20A
OVDDo
1.80V @ 20A
12V0 VIN
Figure 3. Power supplies - Part 1
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MC34712EP
VTT1
0.60V @ 3A
PS_VTT1_EN
from CPLD
3V3 VIN1
UDIMM[1:2] VTT
PS_VTT1_PG
MC34712EP
VTT2
0.60V @ 3A
PS_VTT2_EN
from CPLD
3V3 VIN1
UDIMM[3:4] VTT
PS_VTT2_PG
LTC3026EMSE
USB_SVDD_CPU
PS_USVDD_EN
from CPLD
3V3+5V VIN[1:2]
LX2160A USB_SVDD
PS_USVDD_PG
PS_USVDD_SEL
LPF
USB_SVDD
0.80V @ 1.5A
LPF
USB_SDVDD_CPU
LX2160A USB_SDVDD
LTC3026EMSE
AVDD_SD1_PLL*
PS_SAVDD_EN
from CPLD
3V3+5V VIN[1:2]
LX2160A AVDD_SD1_PLLF
LX2160A AVDD_SD1_PLLS
PS_SAVDD_PG
PS_SAVDD_SEL SD_AVDD
0.90V @ 1.5A
AVDD_SD2_PLL* LX2160A AVDD_SD2_PLLF
LX2160A AVDD_SD2_PLLS
AVDD_SD3_PLL* LX2160A AVDD_SD3_PLLF
LX2160A AVDD_SD3_PLLS
LTC7150
PS_0V85_EN
PS_0V85_PG
from CPLD
12V0 VIN
IN112525 VDD
AQR107_1 VDD
AQR107_2 VDD
DIMM[1:4] VDD
0V85
0.85V @ 20A
NX5P2924BUK
3V3 LX2160A USB_HVDD
USB_HVDD_SW
3.30V @ 1.0A
PS_USB_HVDD_EN
from CPLD
LPF
USB_HVDD_CPU
FPF1321UCX
3V3+OVDD LX2160A EVDD
EVDD
1.80V @ 1.0A \
3.30V @ 1.0A
PS_EVDD_EN
from CPLD
PS_EVDD_SEL
LPFx2
LPFx2
LPFx2
Figure 4. Power supplies - Part 2
The LX2160A processor does not support EVDD operation at 3.3 V; however, the LX2160ARDB can enable it.
NOTE
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MAX8902B
3V3_SB LX2160A TA_BB_VDD
TA_BB_VDD
0.8V @ 0.5A
PS_TA_BB_SEL
from CPLD
PS_TA_BB_PG_B
MC34717EP/R2
PS_LVAUX_EN
PS_LVAUX_PG
1V2
1.20V @ 5A
from CPLD
5V0 VIN[1:2] IN112525 RT1_VDD*
AQR107_1 P0_VA12*
AQR107_2 P0_VA12*
0V9
0.9V @ 5A
CS4223 VDD
CS4223 AVDD
MC34717EP/R2
PS_2VX_EN
PS_2VX_PG
2V5
2.50V @ 5A
from CPLD
5V0 VIN[1:2]
MAX14591 VDD
MX25V4006 VDD
2V1
2.10V @ 5A
AQR107_1 VA21_*
AQR107_2 VA21_*
MC34717EP/R2
3V3_SB
3.30V @ 1.5A
5V0_SB VIN[1:2] EPM2210 IO
PCF2129 VBAT
LTC3882 I2C_IO
MAX8902 TA_BB
1V8_SB
1.80V @ 1.5A
EPM2210 IO
EPM2210 VDD
Figure 5. Power supplies - Part 3
Note that several power supplies have onboard low-pass filters, to prevent board switching noise from coupling into sensitive
analog supplies. The figure below shows the filters used.
2.2uF 2.2uF
2.2uF =NFM18PC225B1A3
2.2uF =GRM155R60J22 5KE95
LPF
LPF
47uF 3nF
4.7uF
0.33OHm
LPF
10uF 1uF
5.1OHm
0.22uF
Figure 6. Passive low pass filters
2.1.1 Primary power supply
The primary power supply for the LX2160ARDB is an external 300 W ATX12V/EPS12V power supply. The following tables show
its main features.
Table 4. Primary power supply
Power supply Description
External ATX 12 V power
supply
Vin 90 - 264 Vac
Fin frequency 50 - 60 Hz
Iin < 8.5 A at 100 Vac, 4 A at 240 Vac
Power good Power-on delay time of 100 ~ 500 ms
Operating temperature range 0 ~ 50 °C on full load
Relative humidity 20~ 80%
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Table 5. ATX12V/EPS12V power supply characteristics
Group Outputs Unit
Voltage +3.3 +5 +12 -12 +5 (SB) V
Maximum load 10 14 25 0.3 2.0 A
Minimum load 0.5 1 2 0 0.1 A
Regulation ±5 ±5 ±5 ±10 ±5 %
Ripple and noise 60 60 120 120 50 mV
Capacitive loads 10000 10000 10000 330 10000 μF
2.1.2 Secondary power supplies
The table below lists the secondary power supplies for the LX2160ARDB. These supplies are derived from the ATX power supply
unit and they are used to power various onboard devices. A few are on all the time, while most others are enabled and disabled
in a particular order, as controlled by the CPLD system controller.
Table 6. Secondary power supplies
Part
identifier
Manufacturing
part number
Part
manufacturer
Power supply Specifications Description
U12 LTC3882 Linear
Technology
VDD 0.825 V at 70 A with ±3%
accuracy
Supplies power to the
LX2160A cores
U16 LTC7150 Linear
Technology
GVDD 1.2 V at 20 A with ±3%
accuracy
Supplies power to the
LX2160A DDR controllers,
DDR memories, and DDR
memory termination
power supplies (VTT1 and
VTT2)
U15 LTC7150 Linear
Technology
OVDD 1.8 V at 20 A with ±3%
accuracy
Supplies power to the
LX2160A general I/O
drivers. OVDD also
supplies power to the
PROG_MTR and
TA_PROG_SFP pins,
through J8 and J9
jumpers, respectively,
which are normally open
(unmounted).
Filtered OVDD
power is also
supplied to the
core CPU PLLs
(AVDD[1:5] and
AVDD_D[1:2]).
NOTE
Table continues on the next page...
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Table 6. Secondary power supplies (continued)
Part
identifier
Manufacturing
part number
Part
manufacturer
Power supply Specifications Description
U17 MC34717EP/R2 NXP
Semiconductors
SD_OVDD 1.8 V at 5 A ±3% accuracy Supplies power to the
LX2160A SerDes I/O
drivers
SD_SVDD 0.92 V at 5 A ±3%
accuracy
Supplies power to the
LX2160A SerDes cores
U20 MC34712EP NXP
Semiconductors
VTT1 0.6 V at 3 A Supplies power to the
DDR#1 UDIMM memory
termination power
U21 MC34712EP NXP
Semiconductors
VTT2 0.6 V at 3 A Supplies power to the
DDR#2 UDIMM memory
termination power
U24 LTC3026EMSE Linear
Technology
SD_AVDD 0.9 V at 1.5 A Supplies power to the
LX2160A SerDes PLLs.
Filtered SD_AVDD
power is supplied to
SerDes1, SerDes2 and
SerDes3 PLLs
(AVDD_SD[1:3]_PLLF
and
AVDD_SD[1:3]_PLLS).
NOTE
U22 LTC3026EMSE Linear
Technology
USB_SVDD 0.8 V at 1.5 A Supplies power to the
LX2160A USB PHY super
speed (SS) and high
speed (HS) power
supplies
U34 NX5P2924BUK NXP
Semiconductors
USB_HVDD_
SW
3.3 V at 1 A Supplies power to the 3.3
V USB PHY HS power
supply
Table continues on the next page...
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LX2160ARDB Functional Description
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Table 6. Secondary power supplies (continued)
Part
identifier
Manufacturing
part number
Part
manufacturer
Power supply Specifications Description
U33 FPF1321UCX
FPF1321UCX
is a power
switch, not a
power supply.
OVDD is the
source of the
1.8 V power.
NOTE
ON
Semiconductor
EVDD 1.8 V or 3.3 V at 1 A
The LX2160A
processor does
not support
EVDD
operation at 3.3
V; however, the
LX2160ARDB
can enable it to
change
between 1.8 V
and 3.3 V on the
commands of
the SDHC IP
block for certain
board
configurations.
NOTE
eSDHC I/O power
U29 LTC7150 Linear
Technology
0V85 0.85 V at 20 A with ±3%
accuracy
Supplies power to the
Aquantia AQR107 PHYs,
Inphi IN112525 PHY, and
DDR memories
U30 MC34717EP/R2 NXP
Semiconductors
1V2 1.2 V at 5 A with ±3%
accuracy
Supplies power to the
Aquantia AQR107 PHYs
and Inphi IN112525 PHY
0V9 0.9 V at 5 A with ±3%
accuracy
Supplies power to the
Inphi CS4223 PHY
U31 MC34717EP/R2 NXP
Semiconductors
2V5 2.5 V at 5 A with ±3%
accuracy
Supplies power to DDR4
DIMM connectors
2V1 2.1 V at 5 A with ±3%
accuracy
Supplies power to the
Aquantia AQR107 PHYs
U3 MC34717EP/R2 NXP
Semiconductors
3V3_SB 3.3 V at 1.5 A Standby (“hot”) power for
the CPLD core
1V8_SB 1.8 V at 1.5 A Standby (“hot”) power for
the CPLD core and I/O
U27 MAX8902B Maxim
Integrated
TA_BB_VDD 0.8 V at 0.5 A Supplies power to the
LX2160A secure monitor
2.1.3 Power supply sequence
The external ATX power supply provides 5V_SB voltage when connected to an AC power outlet. This is an independent 5V power
supply that is always active. This voltage is used to generate the 3V3_SB and 1V8_SB standby power supplies, which are used
to power the CPLD.
NXP Semiconductors
LX2160ARDB Functional Description
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With power available, CPLD can manage the orderly power-up of the rest of the system on an appropriate event (one of the
following):
• The power switch (push button) is pressed
• The SW_AUTO_ON switch (SW4[2]) is set to '1'
On receipt of a power event signal, the CPLD power sequencer block manages the orderly enable of the remaining power supplies,
as shown in the figure below.
Vac (ATX-PS)
5V0_SB
HOT_POWER
1V5_SB,
3V3_SB
TA_BB_VDD
PS_ON_B
TIER 0
3V3, 5V0, 12V0
USB_HVDD
ATXPWRGD
TIER 1
0V85, 0V9, 1V2
TIER 2
VDD, OVDD,
2V1, 2V5,
USB_SVDD
PORESET_B
~12mS
~11mS
220-250mS
~500mS
530mS
550-570mS
570-590mS
~610mS
>= 700mS
t
TIER 3
SD_SVDD,
SD_OVDD,
AVDD_SDn_PLLn
TIER 4
GVDD,
VTT1, VTT2,
DDR_VREF,
EVDD
Figure 7. Power up voltage sequence
The LX2160ARDB follows the power supply sequencing requirements as detailed in QorIQ LX2160A Data Sheet .
2.1.4 Current and power measurements
The LX2160ARDB implements onboard current and power measurements only for the VDD supply. For selected other supplies,
monitoring resistors are available. The table below lists all measurable supplies.
NXP Semiconductors
LX2160ARDB Functional Description
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Table 7. Power monitoring
Power Measurement device Shunt resistor value Notes
VDD LTC3882 − Standard PMBus commands, for
example, READ_IOUT
INA220 0.0005
GVDD External meter 0.0005
Power supplies not listed in the above table are considered as low-current/incidental supplies and are not instrumented for power
measurement.
2.2 Clocks
The LX2160ARDB provides all the clocks required for the processor and peripheral interfaces. The figure below shows the
LX2160ARDB clock architecture.
Si5341B-
Dxxxxx -
GM
CLK8
CLK0
48 MHz XA
XB
LX2160A
Si52208
PCIe slots
CLK_SLOTn_[P,N]
SLOT[1:2]_PRESENT_B
100 MHz
HCSL
2
SSON
CFG_SPREAD
from CPLD
CFG_CLKEN_SLOT[1:2]_B
from CPLD
100 MHz
HCSL
2
OE
PRSNT_SLOT[1:2]_B
to CPLD
SD2_CLK[F,S]_[P,N]
SD3_CLK[F,S]_[P,N]
2
100 MHz
HCSL
SD1_CLKF_[P,N]
161.1328125 MHz
HCSL
SD1_CLKS_[P,N]
161.1328125 MHz
HCSL
CLK4 100.00 MHz
HCSL SYSCLK_DIFF_[P,N]
CLK1A 100.00 MHz
LVCMOS
CLK1B 100.00 MHz
LVCMOS DDRCLK
CLK7A 125.00 MHz
LVCMOS
CLK7B 125.00 MHz
LVCMOS
EC_GTX_CLK
IEEE header
CLK9 156.250 MHz
HCSL CS4223 40 GbE PHY
CLK2 100.00 MHz
HCSL AQR107 10 GbE PHY #1
CLK3 100.00 MHz
HCSL AQR107 10 GbE PHY #2
CLK5 25.00 MHz
HCSL IN112525 25 GbE PHY
Figure 8. LX2160ARDB clock architecture
All the clocks are fixed frequency, and most are produced by the Si5341B or Si52208. The following table summarizes the
specifications of each clock and the component that provides it.
NXP Semiconductors
LX2160ARDB Functional Description
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Table 8. LX2160ARDB clocks
Part identifier Clock generator Clock Specifications Destination
Y1 Hot-powered crystal
oscillator
HOT_CLK • Frequency: 25 MHz
• Output type: CMOS
CPLD
U130 Si5341B-D08333-GM OUT0: CLK_SD1_S_[P, N] • Frequency:
161.1328125 MHz
• Output type: HCSL
• Operating voltage:
1.8 V
SerDes1 controller
PLL 2
OUT1B: DDRCLK_SE • Frequency: 100
MHz
• Output type:
LVCMOS
• Operating voltage:
1.8 V
DDRCLK
OUT2:
CLK_10GE_PHY1_[P, N]
• Frequency: 100
MHz
• Output type: LVDS
• Operating voltage:
1.8 V
10 GbE PHY 1
(AQR107)
OUT3: CLK_10GE_B_[P,
N]
• Frequency: 100
MHz
• Output type: LVDS
• Operating voltage:
1.8 V
10 GbE PHY 2
(AQR107)
OUT4: SYSCLK_DIFF_[P,
N]
• Frequency: 100
MHz
• Output type: HCSL
• Operating voltage:
1.8 V
DIFF_SYSCLK
OUT5:
CLK_25GE_REF_[P, N]
• Frequency: 25 MHz
• Output type: HCSL
• Operating voltage:
1.8 V
25 GbE PHY
(IN112525)
OUT7: EC_CLK125 /
CLK_1588_CGEN
• Frequency: 125
MHz
• Output type:
LVCMOS
Ethernet controller /
IEEE 1588 port
Table continues on the next page...
NXP Semiconductors
LX2160ARDB Functional Description
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Table 8. LX2160ARDB clocks (continued)
Part identifier Clock generator Clock Specifications Destination
• Operating voltage:
1.8 V
OUT8: CLK_SD1_F_[P, N] • Frequency:
161.1328125 MHz
• Output type: HCSL
• Operating voltage:
1.8 V
SerDes1 controller
PLL 1
OUT9:
CLK_PHY_40GE_[P, N]
• Frequency: 156.25
MHz
• Output type: HCSL
• Operating voltage:
1.8 V
40 GbE PHY
(CS4223)
U117 Si52208-A01AGM DIFF0_[P, N]:
CLK_SD2_F_[P, N]
• Frequency: 100
MHz (spread-
spectrum capable)
• Output type: HCSL
SerDes2 controller
PLL 1
DIFF1_[P, N]:
CLK_SD2_S_[P, N]
SerDes2 controller
PLL 2
DIFF2_[P, N]:
CLK_SLOT1_[P, N]
PCIe x4 slot
DIFF3_[P, N]:
CLK_SLOT2_[P, N]
PCIe x8 slot
DIFF4_[P, N]:
CLK_SD3_F_[P, N]
SerDes3 controller
PLL 1
DIFF5_[P, N]:
CLK_SD3_S_[P, N]
SerDes3 controller
PLL 2
2.3 DDR interface
The LX2160ARDB supports two high-speed DDR4 memory ports: DDR#1 and DDR#2.
The figure below shows the architecture of the DDR#1 memory port.
NXP Semiconductors
LX2160ARDB Functional Description
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