Octek HAWK 486 User manual

H A W K
4 8 6

The material in this manual is for information only and is subject to change without notice.
REVISION: 1.0
IBM, IBM PC/XT/AT, PC-DOS, MS-DOS, OS/2, INTEL, WEITEK, PHOENIX ARE THE
TRADEMARKS OR REGISTERED TRADEMARKS OF THEIR RESPECTIVE
OWNERS.

RADIO FREQUENCY INTERFERENCE STATEMENT
This equipment generates and uses radio frequency energy and if not
installed and used properly, that is, in strict accordance with the
manufacturer's instructions, may cause interference with radio and
television reception.
If this equipment does cause interference to radio or TV reception, which
can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the
following measures:
* Reorient the receiving antenna.
* Relocate the computer away from the receiver.
* Move the computer away from the receiver.
*Plug the power cord of computer into a different outlet so that computer
and receiver are on different branch circuits.
*Ensure that card slot covers are in place when no card is installed.
*Ensure that card mounting screws, attachment connector screws, and
ground wires are tightly secured.
*If peripherals are used with this system, it is suggested to use shielded,
grounded cables, with in-line filters if necessary.
If necessary, the user should consult the dealer service representative for
additional suggestions.
The manufacturer is not responsible for any radio or TV interferences
caused by unauthorized modifications to this equipment. It is the
responsibility of the user to correct such interferences.

Note
1. Electronic components are sensitive to dust and dirt. Do inspect
and clean the computer system regularly.
2. Turn off the power whenever you install or remove any connector,
memory module and add-on card. Before turning on the
power, make sure that all the connectors, memory modules and
add-on cards are secured.
3. After power is on, please wait for a minute. The system BIOS are
going through a self-test during this period and nothing is
shown on the screen. After the self-test, the system BIOS will
initialize the display adaptor and show messages.
4. The SIMM sockets are fragile device. Do not force the SIMM
modules into the sockets. It may break the locking latches.

Preface
The manual provides information about the installation and
maintenance of OCTEK HAWK-486 motherboard. In-depth
explanations of the functions of this motherboard are provided. In the
appendix, the system BIOS setup is explained.
The content in this manual is only for reference and is intended
to provide basic information for the general users. There are also some
technical information for hardware and software engineers.
In this manual, there are 4 chapters. Chapter 1 contains a brief
introduction and specification of OCTEK HAWK-486 motherboard. In
the Chapter 2, the functions of OCTEK HAWK-486 are explained. It
also outlines many advanced features of the CPU and the system
architecture. Chapter 3 explains the installation of DRAM modules and
jumpers. Some technical information are provided in the Chapter 4.
System BIOS and the system setup are described in the
Appendix A. All the setup procedures are explained.
Additional information are given in Appendix B, C and D for
the maintenance purpose.

CONTENT
Chapter 1 INTRODUCTION 1-1
Chapter 2 GENERAL FEATURES 2-1
Specification 2-1
Processor 2-3
Memory System 2-8
Dual Bus Design 2-9
System Functions 2-10
Chapter 3 INSTALLING COMPONENTS 3-1
Installing RAM Modules 3-1
Installing External Battery 3-3
Configuration of Memory 3-4
DRAM Configuration 3-5
Control of System Speed 3-6
Reset CMOS Setup 3-6
Information
System Board Jumper Setting 3-7
System Board Connectors 3-8

Chapter 4 TECHNICAL INFORMATION 4-1
Memory Mapping 4-1
I/O Address Map 4-2
System Timers 4-4
System Interrupts 4-6
Direct Memory Access (DMA) 4-7
Real Time Clock and CMOS 4-8
RAM
CMOS RAM Address Map 4-9
Real Time Clock Information 4-10
System Expansion Bus 4-11
APPENDIX A SYSTEM BIOS A-1
Setup Utility Description A-2
Prompt-Line Prompts A-5
Esoteric Prompts A-8
Setup Section A-9
APPENDIX B OPERATION & MAINTENANCE B-1
Static Electricity B-1
Keeping the System Cool B-1
Cleaning the "Golden Finger" B-2
Cleaning the Motherboard B-2

APPENDIX C TROUBLESHOOTING C-1
Main Memory Error C-1
Improper Setting of Wait State C-1
APPENDIX D SYSTEM BOARD LAYOUT D-1

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Chapter 1
Introduction
_______________________________
OCTEK HAWK-486 consists of 32-bit 80486 microprocessor, a
large cache memory and highly integrated chipsets to provide high
performance, reliability and compatibility. OCTEK HAWK-486 is a
perfect choice for CAD/CAM workstation and file server and supports
sophisticated 32-bit computing applications and multi-user operating
systems.
The total memory is 32MB memory is installed on board and
flexible memory configuration for 256K 1M and 4M.
Compatibility and reliability are important issues. I/O channel
is compatible to standard AT bus. Therefore any AT compatible
peripherals may be used on OCTEK HAWK-486. On board
POWERGOOD generator is essential to ensure the reliability of the
system and is well-designed to work with all power supplies.

INTRODUCTION
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THIS PAGE IS INTENTIONALLY LEFT BLANK

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Chapter 2
General Features
_______________________________
SPECIFICATION
Processor :
Intel 80486DX, 80486SX and 80487SX CPU
Speed :
Turbo/normal speed
Software/hardware selectable
I/O Slot :
Compatible to standard AT bus
Two 8-bit and six 16-bit slots
Programmable wait state for AT cycle
Programmable AT Bus speed
Memory :
Shadow RAM for System BIOS and Video BIOS
Fast page mode DRAM controller with burst mode support
SIMM sockets for 256K , 1M or 4M modules
32M bytes on board
CAS# before RAS# refresh to reduce power consumption
Combination of DRAM type support

GENERAL FEATURES
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System Support Functions :
8-Channel DMA (Direct Memory Access)
16-level interrupt
3 programmable timers
CMOS RAM for system configuration
Real time clock with battery backup
Other Features :
On board POWERGOOD generation
On board battery backup CMOS data
External battery connector
Hardware / Software turbo switch

GENERAL
FEATURES
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PROCESSOR
The power of HAWK comes from 80486. 80486 is the
state-of-art microprocessor which merges many innovative features on a
single chip for advanced applications and operation systems. Fabricating
with the 1um process, this CPU consists of more than one million
transistors. With such high density, this CPU incorporates as many as
new features to make itself the most powerful microprocessor.
80486 is a 32-bit microprocessor with 32-bit external data bus
and 32-bit external address bus. It not only contain a central processing
unit, but also integrates a numeric processor and a four-way set associate
cache memory. It is fully binary compatible with 80386 and 80387. All
existing software for PC XT/AT can be used on OCTEK HAWK-486.
However, due to the new internal architecture, the performance of 80486
is two to four times of 80386.
Cache memory can improve the overall performance of a
computer system. Nevertheless, if the cache memory is separated from
CPU, CPU still needs to fetch code and data through external bus. That
means the data transfer rate should not be too fast so that the external
devices are able to keep pace with the CPU. In 80486, the cache
controller and cache memory are integrated into the chip. Most of the
operations can be carried out inside the CPU, which reduces the bus
operations on external data and address bus and thus speeds up the
internal execution.

GENERAL FEATURES
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GENERAL
FEATURES
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The cache memory is a 8K bytes, 16 bytes line size, four-way
set associative configuration. The hit rate of this configuration is much
better than 32K bytes two-way set associative external cache because a
four-way set associative architecture provides better performance in a
multitasking and multi-processor environment.
Bus snooping feature keeps the cache memory consistent with
the main memory. When an external processor overwrites the content in
the main memory, the corresponding data in the internal cache memory
will be invalidated and will be fetched from main memory when CPU
reads this data.
If a read miss occurs, the CPU will initiate a burst mode read
operation. In burst mode read operation, CPU performs four successive
read operations each of which takes only one cycle. Total 128 bits data
are fetched into the CPU's internal cache. Since burst mode read
operation is very fast, the traffic of the CPU bus is greatly reduced and
the bus is available to other bus masters, such as DMA controller.
Reading 128 bits data into CPU will take some times. In order
to reduce the delay, the internal cache controller works parallel with
CPU. It fetches the data needed by CPU for the present operation and
the CPU read cycle is terminated. Then the other data are read into the
internal cache memory while CPU is doing something else. This
arrangement permits the CPU to run at zero wait state.

GENERAL FEATURES
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By eliminating the access to external bus, operations with the
internal cache can be completed in a single cycle. 80386 at least needs
two cycles for an operation. To further increase the rate of data transfer
inside the CPU, the internal bus of the cache memory is increased to 128
bits, which is four times of the external bus. Since, in most of the time,
the CPU is using the internal cache, the large bus size substantially
improves the overall performance.
When the CPU writes data to the main memory, the data is first
stored in a write buffer. There are four write buffers. When the
external bus is idle, data will be sent to the main memory. If all buffers
are filled, it can start write operation in burst mode. Since the internal
cache is updated immediately, the CPU need not suspend its operation
and there is no need to wait for the external device to update the main
memory.
Many often-used instructions are executed in a clock cycle and
some instructions are modified to take fewer cycles than in 80386. On
the contrary, 80386 may take two to three more cycles for the same
instruction. The CPU contains an advanced instruction pipeline structure
and a 32-byte code queue to speed up the execution.
80486 includes all the functions of 80386 and is able to support
sophisticated software and operation systems which are widely employed
now. It is able to operate in real mode, protected mode and virtual 8086
mode.

GENERAL
FEATURES
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Internal memory management unit provides a flexible
addressing scheme for the next generation operation system.
Multitasking, concurrent operation and manipulating huge data base can
be accomplished with excellent performance. Paging mechanism is
employed to allow powerful operating system to implement virtual
memory. Each segment is divided into several pages which are 4K bytes
per page. Page mechanism is transparent to software and allows
software to address 64 terabytes. Furthermore, the 64KB segment
boundary which is an barrier of 8088 and 80286 is removed and the
segment length can be increased up to 4GB.
The demand for sophisticated, number-crunching scientific and
business applications has rapidly increased in recent years. In the past,
microprocessor features an integer Arithmetic Logic Unit which only
handles simple integer operations such as addition and multiplication.
Floating-point operations which are actually utilized by applications must
be accomplished through software routines.
To meet the demand of floating-point calculation, a numeric
coprocessor is necessary. However, an external coprocessor has been
found to be the bottleneck of data transfer. 80486 integrates the
coprocessor on chip and thus the data transfer to external bus is
eliminated. The on-chip coprocessor is compatible with 80387. It
works parallel with other units in the CPU, which results in a better
performance of numeric process.

GENERAL FEATURES
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MEMORY SYSTEM
Two banks of DRAMs can be installed on motherboard and
256K, 1MB and 4MB DRAM SIMM modules are support. One bank of
DRAM refers to four pieces of SIMM modules. The maximum memory
size is 32MB when using 4MB DRAM for all banks. The DRAM
should be fast-page mode DRAM with CAS# before RAS# refresh
capability.
The memory system supports Burst mode. Successive memory
accesses in 3, 2, 2, 2 DRAM burst cycles. It does not require wait state
and thus CPU can run at full speed.
To enhance the system performance, shadow RAM mode is
supported. In shadow RAM mode, system BIOS and video BIOS
contained in low speed memory such as EPROM and ROM are copied
into DRAM. Improvement is significant because access to DRAM is
much faster than ROM.

GENERAL
FEATURES
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DUAL BUS DESIGN
It is very important that a high speed system should be
compatible with existing peripherals without lowering the performance.
To be compatible, the I/O slot should run at 8MHz or slower. On the
other hand, the rest of the system are running at full speed.
A dual bus design is employed. A high speed bus links the
CPU, coprocessor, cache memory and main memory. This bus is
synchronous with the clock of the CPU and the data transfer is 32 bits.
Whenever there is a request for transferring to or from I/O slot, the
chipset is responsible for handling the conversion between the buses.
The clock rate of the high speed bus will not be reduced, which
eliminates many compatibility problem.
CPU
High Speed
bus 8Mhz bus
Chip Set I/O Slot
32 Memory bus
Cache Main
Memory Memory
┌─────┐
│ │
└──┬──┘
│ ┌───────┐ ┌───────┐
├────────────┤ ├──────┤ │

GENERAL FEATURES
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│ └───┬───┘ └───────┘
│ │
┌──┴───┐ ┌───┴───┐
│ │ │ │
│ │ │ │
└──────┘ └───────┘