Octek HIPPO DCA 2 User manual

USER'S MANUAL
HIPPO DCA 2
VESA LOCAL BUS MOTHERBOARD

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Hippo DCA2 486
486 VESALocalBus Motherboard
User’s Manual
Version 2.25 December 1994

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Copyright Notice
Copyright 1994 Ocean Information Systems,Inc.
All rights reserved.
Ocean Information Systems,Inc.
688 Arrow Grand Circle
Covina,CA 91722
Printed in theHong Kong
All of the information contained in this manualis copyrighted and all rights reserved. No part of this
document, in whole or in part, may be reproduced or copied in any form without prior consent in writing
from Ocean Information Systems,Inc.
_____________________________________________________________________________________
Limited Warranty
Buyer agrees that if this product hasany defects,Ocean Information Systems, Inc. (OISI) is only obligated
to replace or refund the purchaseprice for a period of one yearfrom date of purchase. OISI is not liable for
any loss, direct or indirect, that may be incurred as a result of any defects. The warranty does not cover any
loss or damage caused by shipping, improper installation or maintenance, or any repairs made by anyone
other than an authorized Ocean service center.
_____________________________________________________________________________________
Limitations of Liability
While the information in this manual has been carefully reviewed and is believed to be accurate, OISI
assumesno responsibility in the event that any inaccuraciesare found. In no event shallOISI be held liable
for any loss or expenses whether directly or indirectly caused by the support materials provided with this
product. It is further acknowledged that OISI is under no obligation to update the manualor to notify
purchasersof any forthcomingupdates.
_____________________________________________________________________________________
Trademarks
AMD is a registered trademark of Advanced Micro Devices
AMI is a trademark of American Megatrend,Inc.
Fasmath is a registered trademark of Cyrix Corporation
Intel i386, i486, i486SX, i486DX, i486DX2 and Intelare registered trademarksof IntelCorporation.
MS-DOS, Xenix, Windows and Microsoft are registered trademarks of Microsoft Corporation.
MR BIOS is a trademark of Microid Research, Inc.
Novell is a registered trademark of Novell, Inc.
Octek is a registered trademark of Ocean Information Systems,Inc.
OPTi is a registered trademark of OPTi Inc.
Unix is a registered trademark of American Telephone and Telegraph Company Bell Laboratories.
VESA and VL-Bus are registered trademarks of Video Electronic Standard Association.
XT, AT, PS/2, OS/2, & IBM are registered trademarksof InternationalBusiness MachinesCorporation.
All other brand and product namesmentioned in this manualare trademarks orcopyrights of their
respective holders.

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Preface
About the Hippo DCA2
Thank you for purchasing the Hippo DCA2, Ocean Information Systems’new top-of-the-
line 486 motherboard. The Hippo DCA2 utilizes DynamiCache, an innovative cache
memory technology that takes personal computing to a new level of performance.
DynamiCache was designed to eliminate bottlenecks between the CPU and the memory
bank. It does this by replacing traditional DRAM and external L2 cache with a memory
bank that runs at CPU speed. With entire memory running at CPU speed the processor can
handle multitasking just as easily as it handles single applications.
About the Manual
The content of this manual is for reference only and is intended to provide basic
information for the general user. Technical information is also included in the Appendix
for hardwareand softwareengineers.
This manual provides information about the installation and maintenance of the Octek
Hippo DCA2 motherboard. In-depth explanations concerning the functions and features
of this motherboard are provided. Chapter 1 is designed to give the user an overview of
DynamiCache, including an in-depth explanation of what it is as well as how it works.
Chapter 2 describes the features of the Hippo DCA2 motherboard. It provides important
information regarding the main memory system, ISA and VESA slots, the BIOS,and the
CPUs supported. Refer to Chapter 3 for instructions on how to setup and install the
motherboard. This chapter includes the necessary data for properly setting the pin
connectors. Requirements for setting up the BIOS are listed in Chapter 4. An Appendix
is also included that provides address maps as well as advanced technical information for
hardware and softwareprofessionals.

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Tableof Contents
Preface....................................................................................................iii
Chapter1: DCA2SystemOverview
1.1 What is DCA2 ?..................................................................................................1
1.2 What makes DCA2 so powerful ?.......................................................................1
1.3 What is DynamiCache ?......................................................................................1
1.4 Why is DCA2 a better choice ?...........................................................................1
1.5 User advantages of DCA2...................................................................................2
1.6 Technical advantages of DCA2...........................................................................2
1.7 DynamiCache Description ..................................................................................3
1.8 DynamiCache Architecture ................................................................................3
1.9 Distributed Cache................................................................................................4
1.10 DynamiCache Applications.................................................................................4
1.11 Application Overhead and its effect on External Cache.....................................4
1.12 External Cache Saturation Problem ....................................................................5
1.13 DynamiCache Excels and External Cache SuffersUnder
Heavy Processing Loads .....................................................................................5
1.14 Target Operating Environments..........................................................................5
1.15 L2/ DCA2 Cache Efficiency Versus Application Size .......................................6
1.16 General Specifications Overview........................................................................7
Chapter2: Features
2.1 Layout of Hippo DCA2 board..............................................................................8
2.2 System Component Map......................................................................................9
2.3 Jumper Description Table ..................................................................................10
2.4 DynamiCache.....................................................................................................11
2.5 DRAM Memory.................................................................................................11
2.6 Memory Configuration Table.............................................................................12
2.7 Total System Memory........................................................................................13
2.8 ISA Slots............................................................................................................13
2.9 VESA Local Bus................................................................................................13
2.10 CPU....................................................................................................................14
2.11 Processor Types Supported................................................................................14
2.12 BIOS...................................................................................................................14
2.13 Shadow RAM.....................................................................................................15
2.14 Power Management............................................................................................15
2.15 Software Compatibility ......................................................................................15

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Chapter3: SetupandInstallation
3.1 Setup..................................................................................................................16
3.2 Installation Precautions .....................................................................................16
3.3 Operation and Maintenance ..............................................................................16
3.4 CPU Jumper Settings ........................................................................................17
3.5 CPU Installation................................................................................................18
3.6 DynamiCache / DRAM Installation..................................................................19
3.7 Compatible 72-pin SIMM Types ......................................................................20
3.8 Control of System Speeds.................................................................................21
3.9 Fan Voltage.......................................................................................................21
3.10 Fan connector....................................................................................................21
3.11 Reset CMOS buffer...........................................................................................21
3.12 Color / Mono display select. .............................................................................21
3.13 Connectors.........................................................................................................22
3.14 Reset Switch Connector....................................................................................22
3.15 Turbo Switch Connector ...................................................................................22
3.16 Turbo Led Connector........................................................................................23
3.17 Speaker Connector. ...........................................................................................23
3.18 Keyboard Lock Connector................................................................................24
3.19 Keyboard Connector .........................................................................................24
3.20 External Battery Connector...............................................................................25
3.21 Power Supply Connector...................................................................................25
Chapter4: BIOSSetup
4.1 BIOS Power-On Self-Test (POST)...................................................................27
4.2 AMI BIOS Beep Codes.....................................................................................27
4.3 Microid Research BIOS Beep Codes................................................................28
Appendix: AdvancedTechnicalInformation
A.1 Memory Address Map......................................................................................29
A.2 I/O Address Map ..............................................................................................30
A.3 I/O Extension Pinout........................................................................................31
A.3.i 18-Bit ISA Pinout................................................................................31
A.3.ii 16-Bit ISA Extension Pinout...............................................................31
A.4 VL-BUS Extension Pinout...............................................................................32
A.5 Direct Memory Access Channels.....................................................................33
A.6 DMA Controller Registers ...............................................................................33
A.7 Page Register Address......................................................................................34
A.8 System Interrupts..............................................................................................34

Chapter 1 System Overview
Hippo DCA2 User’s Manual
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CHAPTER 1
SYSTEM OVERVIEW
Listed below are answers tosome questions you may have about DCA2and its phenomenal
performance.
1.1 What is DCA2 ?
DCA2(DynamiCache Architecture - 2nd generation) is a high performance cache memory
system that alleviates the traditional bottleneck of mainboards. This evolutionary system
operates up to four times fasterthan standard DRAMor external cache based boards. With
DCA2 users at last have a means of enhancing their systems without the necessity of
processor or external cache upgrades.
1.2 What makes DCA2so powerful?
Unlike external cache, which was implemented as a low-cost enhancement to standard
DRAM, DCA2 was designed for pure performance. DCA2 transforms the entire memory
bank into DynamiCache, a high speed memory that operates at 15ns rather than 70ns.
1.3 What is DynamiCache ?
DynamiCache is a high speed memory module that boosts the entire memory bank so that
it operates at the same speed as the CPU clocking rate. The entire memory bank appears
as cache to the CPU.
1.4 Why is DCA2 abetter choice ?
DCA2 has a far greater impact and offers more benefits dollar for dollar than the best
external cache based boards. Programs such as Windows 3.11, OS/2 and Windows NT
place extreme stress on external cache based systems, often causing bottlenecks between
the CPU and the memory bank. When the cache bank becomes full, the CPU must wait
for new instructions to be loaded up from the slower DRAM memory. With DCA2, the

Chapter 1 System Overview
Hippo DCA2 User’s Manual
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memory operates at thesame speed as the CPU, allowing the CPU to retrieve instructions
from any location within the main memory at zero wait states.
1.5 Users advantages of DCA2
The entire memory bank acts as if its a cache subsytem.
15ns memory (standard DRAMonly operates at 70ns).
Zero wait statesbetween the CPU and memory.
Up to 200% memory performance increase with applications running in a DOS
environment or other 16-bit operating systems.
Up to 400% memory performance increase with applications run in an OS2 and NT
environment or other 32-bit operating systems.
DCA2 memory operates at CPU speed, making it four times fasterthan any other
DRAM memory currently on the market.
1.6 Technical advantages of DCA2
15ns Access Time during Hit Cycle
15ns Posted RandomWrites
35ns RandomRead Access Page Miss
Transparent Refresh during Cache Reads
Hidden DRAM precharge during Page Reads
Consumes 1/3 the power of SRAMplus DRAMsolutions
On-board cache Hit/Miss Comparator
Write Posting Register with Direct Path to Memory Array
1.7 DynamiCache Description
The benefits of DynamiCache are easy to understand. New operating systems such as
Windows 3.11, Windows NT, OS/2, UNIX and theirassociated applications generate a
new level of high stresses on conventional external caches, preventing the power of these
Oss from being fully exploited. Although these operating systems do offerthe ability to
multitask applications, these featuresare rarely used in practice as it causes even the best
designed L2 cache motherboard to perform at unacceptably low levels. DynamiCache,
being able to access any instruction or data string from any physical address in memory
at full cache speed, enables the CPU to handlemultitasked operations as smoothly as it
handles single applications.

Chapter 1 System Overview
Hippo DCA2 User’s Manual
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1.8 DynamiCache Architecture
The DynamiCache chips are physically similar to a standard 4MB page mode or static
column DRAM with the additionof an integrated Row Register Register and an internal
controller that allows it to operate much like page mode or static column DRAM.
DynamiCache’s Row Register register is tightly coupled with the Memory Array. Memory
Reads always occur from the Row Register Registers. When the internal comparitor
detectsapage hit, only theRow Register register is accessed and data is made available in
15ns fromthe column address. When a page read miss is detected, the new Memory Array
row is loaded into the cache and data is available at the output all within a single 35ns
access. Subsequent reads within the page (burst read, local instructions or data) can
continue at a 15ns cycle time.
Figure 1
Since reads occur from the Row Register register, theMemory Array Precharge can occur
simultaneously without degrading performance. The on chip refresh counter with an
independent refresh bus allows the DynamiCache to be refreshed during cache reads.
Memory Writes are internally posted in 15 nSecs and are directed to the DRAM
array.During a write hit, the on chip comparator activates a parallel write path to the Row
Register register to maintain coherency. The DynamiCache delivers 15nSec page mode
memory writes. This high level of performance is achieved with a single non-interleaved
memory consisting of as few as eight 1M x 4 components or a single 72-pin 4Mbyte
DynamiCache module.

Chapter 1 System Overview
Hippo DCA2 User’s Manual
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1.9 Distributed Cache
DynamiCache uses what is referred to as distributed cache rather than lumped cache. The
15 ns access time is available throughout the entire range of installed DynamiCache, not
just in a small external cache. External cache only provides benefit tothe system while the
instructions are housed in the cache. The penalties thatare usually associated with external
cache, such as write back latencies, cache thrashings and cache saturation are not present
in DynamiCache. This architecture provides all of the cache benefits for the entire range
of installed memory withnone of the cache penalties.
1.10 DynamiCache Applications
DynamiCache was designed with the new emerging 32-bit protected mode operating
systems in mind. External cache, prior to 1994 was an acceptable cost based solution for
enhancing DOS applications that typically occupied a memory space that wasless than the
size of theinstalled external cache. If theCPU requested an instruction or a string of data,
this information was made available to the CPU at cache speed (zero wait state). With the
advent of Windows, however, the typical application became larger and much more
complex supporting virtual disks, DLLs and GUI interfaces.
1.11 Application Overhead andits effect on External Cache
These new applications subsequently brought with them tremendous overhead for the
operating systems. OS/2 and Windows NT were created to handle the demandsof the new
applications with the hopes that a pre-emptive multitasking, multithreading 32 bit OS
would break the bottleneck to productivity. It was quickly found that these operating
systems were only effectiveon high end systems, such as DX2, Pentiumor RISCplatforms.
Even with top end CPUs, a large main DRAM bank was needed, typically 16Mbytes or
more and a very expensive L2 cache was often employed, usually 256K to 512K.
1.12 External CacheSaturation Problem
Cache saturation is aneasy concept to understand. Ifthe executing program is smaller than
the externalcache I have installed, then no saturation occurs. There will always be memory
address space available for the execution of this program. If the program is slightly larger
than my L2 cache, saturation may still not occur, provided that the cache is well designed.
There is a point, however, when the L2 cache will remain constantly saturated with
instructions. Some of these may be in the process of being read from the main memory
and some will be waiting tobe written back to memory. The net effectis thatif the program