Oki ML7065-033 User manual

ML7065-033
User’s Manual
Issue Date: September 15, 2005
FEUL7065_033-01

NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the
product, please make sure that the information being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the
standard action and performance of the product. When planning to use the product, please ensure that the external conditions
are reflected in the actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum ratings and within the specified operating
ranges including, but not limited to, operating voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from
misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or
electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or
operation outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in
connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by
us for any infringement of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g.,
office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not,
unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality
and reliability characteristics nor in any system or application where the failure of such system or application may result in the
loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment,
nuclear power control, medical equipment, and life-support systems.
7. Certain products in this document may need government approval before they can be exported to particular countries. The
purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and
necessary steps at their own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
Copyright 2005 Oki Electric Industry Co., Ltd.

Preface
This user’s manual describes the operation of the hardware of the ML7065-033, a
ZigBee® short-distance radio communication IC that conforms to IEEE802.15.4.
The following related manual is available. Read it as required.
ML7065 Design Guide
Contains the hardware information that should be referenced when designing circuits.
•ZigBee is a registered trademark of Koninklijke Philips Electronics N.V.
•Names of companies and products are trademarks or registered trademarks of the respective companies.

Notation
Classification Notation Description
0xnn Represents a hexadecimal number.Numeric value
0bnnnn Represents a binary number.
Address 0xnnnn_nnnn Represents a hexadecimal number. (Indicates 0xnnnnnnnn)
Word, W 1 word = 32 bits
Byte, B 1 byte = 8 bits
Mega, M 106
Kilo, K (uppercase) 210 = 1024
Kilo, k (lowercase) 103= 1000
Milli, m 10-3
Micro, µ10-6
Nano, n 10-9
Unit
Second, s (lowercase) Second
"H" level The signal level on the high voltage side. It indicates the voltage
level of VIH and VOH defined in electrical characteristics.
Terminology
"L" level The signal level on the low voltage side. It indicates the voltage
level of VIL and VOL defined in electrical characteristics.
Register description
Read/Write attribute: R indicates read enable and W indicates write enable.
MSB: Most significant bit in an 8-bit register (memory)
LSB: Least significant bit in an 8-bit register (memory)

ML7065-033 User’s Manual
Contents
Contents – 1
Table of Contents
1. General Description.....................................................................................................................................1
1.1 Features ...................................................................................................................................................1
1.2 Block Diagram.........................................................................................................................................2
1.3 Pin Configuration (Top View) ..................................................................................................................3
1.4 Pin Descriptions.......................................................................................................................................4
1.4.1 RF Related Pins..................................................................................................................................4
1.4.2 Synchronous Communication Interface (SCI) Related Pins..................................................................4
1.4.3 Power Supply Pins..............................................................................................................................5
1.4.4 Other Pins...........................................................................................................................................6
1.4.5 Handling of Unused Pins.....................................................................................................................6
2. Reset Functions............................................................................................................................................7
3. Power Management Function.......................................................................................................................8
4. Mode Setting...............................................................................................................................................9
5. IEEE802.15.4 Modulation..........................................................................................................................10
5.1 Block Diagram of the Modulator Circuit.................................................................................................10
5.2 Chip Order.............................................................................................................................................11
5.3 Pulse Waveforms...................................................................................................................................11
5.4 Packet Format........................................................................................................................................12
6. Synchronous Communication Interface (SCI) Function...............................................................................13
7. Commands.................................................................................................................................................17
7.1 List of Commands..................................................................................................................................17
7.2 Config Commands .................................................................................................................................18
7.2.1 RST_CTL0.......................................................................................................................................18
7.2.2 RST_CTL1.......................................................................................................................................18
7.2.3 CLK_CTL0......................................................................................................................................19
7.2.4 CLK_CTL1......................................................................................................................................19
7.3 MAC Commands...................................................................................................................................20
7.3.1 MCPS-DATA.request.......................................................................................................................22
7.3.2 MCPS-DATA.confirm......................................................................................................................22
7.3.3 MCPS-DATA.indication...................................................................................................................23
7.3.4 MCPS-PURGE.request.....................................................................................................................23
7.3.5 MCPS-PURGE.confirm....................................................................................................................23
7.3.6 MLME-ASSOCIATE.request ...........................................................................................................24
7.3.7 MLME-ASSOCIATE.confirm ..........................................................................................................24
7.3.8 MLME-ASSOCIATE.indication.......................................................................................................25
7.3.9 MLME-ASSOCIATE.response.........................................................................................................25
7.3.10 MLME-DISASSOCIATE.request.....................................................................................................26
7.3.11 MLME-DISASSOCIATE.confirm....................................................................................................26
7.3.12 MLME-DISASSOCIATE.indication.................................................................................................26
7.3.13 MLME-BEACON-NOTIFY.indication .............................................................................................27
7.3.14 MLME-GET.request.........................................................................................................................27
7.3.15 MLME-GET.confirm........................................................................................................................27
7.3.16 MLME-GTS.request.........................................................................................................................28
7.3.17 MLME-GTS.confirm........................................................................................................................28
7.3.18 MLME-GTS.indication.....................................................................................................................28
7.3.19 MLME-ORPHAN.indication ............................................................................................................29
7.3.20 MLME-ORPHAN.response ..............................................................................................................29
7.3.21 MLME-RESET.request.....................................................................................................................29
7.3.22 MLME-RESET.confirm....................................................................................................................30

ML7065-033 User’s Manual
Contents
Contents – 2
7.3.23 MLME-RX-ENABLE.request...........................................................................................................30
7.3.24 MLME-RX-ENABLE.confirm..........................................................................................................30
7.3.25 MLME-SCAN.request......................................................................................................................31
7.3.26 MLME-SCAN.confirm.....................................................................................................................31
7.3.27 MLME-COMM-STATUS.indication ................................................................................................32
7.3.28 MLME-SET.request .........................................................................................................................32
7.3.29 MLME-SET.confirm ........................................................................................................................33
7.3.30 MLME-START.request....................................................................................................................33
7.3.31 MLME-START.confirm...................................................................................................................34
7.3.32 MLME-SYNC.request......................................................................................................................34
7.3.33 MLME-SYNC-LOSS.indication .......................................................................................................34
7.3.34 MLME-POLL.request.......................................................................................................................34
7.3.35 MLME-POLL.confirm......................................................................................................................35
7.3.36 MLME-PROTOCOL-ERROR.indication..........................................................................................35
7.3.37 PANDescriptor Details .....................................................................................................................36
7.3.38 Status Details....................................................................................................................................37
7.4 Notes on Operation and Restrictions.......................................................................................................58
8. Electrical Characteristics............................................................................................................................59
8.1 Absolute Maximum Ratings...................................................................................................................59
8.2 Absolute Maximum Ratings...................................................................................................................60
8.3 Supply Current Specification..................................................................................................................61
8.4 DC Characteristics .................................................................................................................................62
8.5 RF Characteristics..................................................................................................................................63
8.6 Synchronous Communication Interface (SCI) Characteristics..................................................................64
8.7 Reset Characteristics..............................................................................................................................67
8.8 Clock Output Characteristics..................................................................................................................68
8.9 Power ON and Power Down Characteristics ...........................................................................................68
9. Package Dimensions..................................................................................................................................69
10. Appendixes................................................................................................................................................70
10.1 Application Circuit.................................................................................................................................70
10.2 About Bypass Capacitors........................................................................................................................71
Revision History................................................................................................................................................72

ML7065-033 User’s Manual
Chapter 1 General Description
1
1. General Description
The ML7065-033 supports the 2.4 GHz band and complies with IEEE802.15.4. It is an IC that can be used for has
short-distance radio communication where the RF section, IF section, modem section, PHY section, MAC section,
and MCU data interface section are integrated into one chip. With its low data transfer speed and low power
consumption, the IC achieves a long battery life. By installing the ZigBee® NWK layer software in the MCU, the
ZigBee® network can be easily constructed.
The ML7065-033 is best suited to sensors, tags, toys, remote controllers, and home appliances.
1.1 Features
•IEEE802.15.4-2003 compliant
•Covers 16-channel 2.4 GHz band radio
•A maximum data transfer speed of 250 kbps
•CSMA-CA channel access
•IEEE802.15.4 2.4 GHz PHY mounted
•IEEE802.15.4 MAC mounted
•O-QPSK modulation/demodulation function
•Synchronous Communication Interface (SCI) mounted
•AES function provided (NIST FIPS-197), with a key size of 128 bits available
•The ZigBee® network can be easily constructed by installing ZigBe® NWK layer software
•Power supply voltages:
I/O section VDDIO: 3.0 V Typ. 2.0 V Min. 3.3 V Max.
CORE section, RF section VCORE: 2.5 V Typ. 2.0 V Min. 2.75 V Max.
• Supply current
When the entire circuit is stopped: 2 µA (Typ)
Attransmission: 56mA(Typ)
At reception: 57 mA (Typ)
Note: At transmission/reception, current flows through components other than those indicated above through
external components (such as an inductor of the antenna section).
• Package:
48-pin VQFN (P-VQFN48-0707-0.50) Product name: ML7065-033GD

ML7065-033 User’s Manual
Chapter 1 General Description
2
1.2 Block Diagram
Outline Description of Blocks
The ML7065-033 consists mainly of the following blocks:
RF Block
The RF block comprises the RF circuit, IF circuit, and Analog circuit and is equipped with 2.4 GHz radio
transmission/reception functions.
MODEM Block &RF CTL Block
These blocks are O-QPSK modem circuits. These blocks also have an RF block control circuit.
PHY Block
IEEE802.15.4 compliant PHY circuit.
AES Block
AES function provided (NIST FIPS-197), with a key size of 128 bits available
MAC Block
IEEE802.15.4 compliant MAC circuit
Synchronous Communication Interface Block
Circuit for clock synchronization with MCU.
SRESETN
RESETN
MODE3
MODE2
MODE1
ANT_1
ANT_2
SW
for Ant
Mixe
r
Synthesize
r
(
VCO
,
PLL
)
I/Q
Mod
IF
BPF Limite
r
LPF
LPF
D/A
D/A
802.15.4
MODEM
(O-QPSK)
&
RF CTL
RSSI
ED
802.15.4
PHY
802.15.4
MAC
(U8)
LN
A
P
A
XIN XOUT
PLL
PLL LF
O
PLL LFI
CLKGEN
SDIN
SDO
SCLK
SINT
SCEN
S
y
nchronous Comunication Interface
CLKOUT
EXTCLK
AES
RF IF&Analog
RF Block

ML7065-033 User’s Manual
Chapter 1 General Description
3
1.3 Pin Configuration (Top View)
VDDIO GND VDDCORE MODE1 N.C. VDD_D_RF PLL_LFI GND_D PLL_LFO GND_RF VDD_VCO GND_RF
36 35 34 33 32 31 30 29 28 27 26 25
MODE2 37 24 N.C.
MODE3 38 23 N.C.
CLKOUT 39 22 VDD_MIX
SDO 40 21 GND_RF
SDIN 41 20 VDD_RF
SINT 42 19 ANT_1
N.C. 43 18 GND_RF
GND 44 17 ANT_2
SCL
K
45 16 N.C.
VDDCORE 46 15 N.C.
SCEN 47 14 GND_RF
VDDIO 48 13 VDD_IF
1 2 3 4 5 6 7 8 9 10 11 12
XOUT
XIN
GND
VDDCORE
VDDIO
EXTCLK
RESETN
SRESETN
VDDCORE
GND
N.C.
VDD_IF
48-Pin VQFN

ML7065-033 User’s Manual
Chapter 1 General Description
4
1.4 Pin Descriptions
1.4.1 RF Related Pins
Pin No Symbol At reset I/O Description
Active
Level
19 ANT_1 I IRF/ORF  RF antenna pin (differential out)
17 ANT_2 I IRF/ORF  RF antenna pin (differential out)
28 PLL_LFO O OA External loop filter output pin (VCO side) For
external connection, see Application Circuits.
30 PLL_LFI I IAExternal loop filter input pin (PLL side) For
external connection, see Application Circuits.
I/O definition IRF : RF input pin.
I
A: Analog input pin.
I : Regular input pin.
I
S: Schmitt trigger input pin.
I
U: Input pin with pull-up resistor.
I
SU : Input pin with Schmitt trigger/pull-up resistor.
I
OS : Input pin for oscillation circuit.
O
RF : RF control output pin.
O
A: Analog output pin.
O : Regular output pin.
O
OS : Output pin for oscillation circuit.
Note: We are currently considering our future plan to replace the PLL_LFO pin with an N.C. pin by
eliminating the external component.
1.4.2 Synchronous Communication Interface (SCI) Related Pins
Pin No Symbol At reset I/O Description
Active
Level
41 SDIN I IO  Data input pin for synchronous communication
interface
40 SDO L IO  Data output pin for synchronous
communication interface
45 SCLK I IO PorN
Clock input pin for synchronous
communication interface
42 SINT H IUO L
Interrupt output pin for synchronous
communication interface
47 SCEN I IU Chip enable pin for synchronous
communication interface

ML7065-033 User’s Manual
Chapter 1 General Description
5
1.4.3 Power Supply Pins
Pin No. Symbol At reset I/O Description
Active
Level
20 VDD_RF   Power supply pin for PA, LNA, SW, and IQMOD
(Typ. 2.5 V)
26 VDD_VCO   
Power supply pin for the synthesizer VCO (Typ.
2.5 V)
22 VDD_MIX   
Power supply pin for the Mixer, Synthesizer, and
LocalGen (Typ. 2.5 V)
12 Power supply pin for the BPF, Limiter, RSSI,
and DAC
13
VDD_IF   
(Typ. 2.5 V)
31 VDD_D_RF   
Power supply pin for the Synthesizer Charge
Pump (Typ. 2.5 V)
5
36
48
VDDIO   
Power supply pin for the digital I/O section
(Typ. 3.0 V)
4
9
34
46
VDDCORE   
Power supply pin for the digital CORE section
(Typ. 2.5 V)
14
18
21
25
27
GND_RF    Ground pin for the RF and IF sections
29 GND_D   
Ground pin for the Synthesizer Charge Pump
3
10
35
44
GND   
Digital ground pin
Common ground of the I/O and CORE sections

ML7065-033 User’s Manual
Chapter 1 General Description
6
1.4.4 Other Pins
Pin No. Symbol At reset I/O Description
Active
Level
7 RESETN I ISL Hardware reset pin
8 SRESETN I IUL
When in other than the sleep state: Functions
as a software reset pin. Pin for resetting from
the MCU
When in the sleep state: Functions as a sleep
release pin. This pin is enabled only when
RESETN = 1.
2 XIN H IOS 10 MHz crystal connection pin 1
External clock input pin
1 XOUT H OOS 10 MHz crystal connection pin 2
Left open when the XIN pin is configured as
an external clock input pin.
39 CLKOUT L IO  System clock output pin. Clock supply to
MCU is possible. Mode setting function
6 EXTCLK I I External clock (64 MHz max.) input pin (Used
for testing purposes only)
33 MODE1 I IO Mode setting pin 1
37 MODE2 I I Mode setting pin 2
38 MODE3 I I Mode setting pin 3
32 N.C.   
23 N.C.   
24 N.C.   
16 N.C.   
15 N.C.   
11 N.C.   
N.C. pins
     
Note: Do not connect anything to the N.C. pins.
1.4.5 Handling of Unused Pins
See below for handling of unused pins. Such handling as leads to impair the basic operation of the
ML7065-033 are not included.
Handling of Unused Pins
Symbol Recommended pin handling
XOUT Open (when XIN is configured as an external clock input pin).
MODE1 Connect to GND.
MODE2 Connect to GND.
MODE3 Connect to GND.
CLKOUT Open.
EXTCLK Connect to GND.
SRESETN Connect to VDD.
N.C. Open.
Note: If any input pin is left open, the supply current may become excessive. Therefore, it is recommended that
unused input ports and I/O ports be configured as input with pull-up resistor/input with pull-down resistor.

ML7065-033 User’s Manual
Chapter 2 Reset Functions
7
2. Reset Functions
The ML7065-033 has the following three reset functions:
(1) Reset by the RESETN pin
By asserting the RESETN pin at power-up, the internal circuit can be reset. Refer to the Application
Circuit section for the external circuit for the RESETN pin. Also at a timing other than at power-up, the
internal circuit can be reset by inputting a reset signal to the RESETN pin. After reset, the ML7065-033
enters the normal state after the oscillation circuit and the PLL circuit are stabilized by the clock
stabilization circuit.
(2) Reset by the SRESETN pin
Software reset can be executed from the host by connecting the SRESETN pin to the GPIO pin of the host.
This operation is enabled only when the RESETN pin is deasserted. In a sleep state, the SRESETN pin
functions as a sleep release pin. By asserting the SRESETN pin, the internal circuit can be reset. After
reset, the ML7065-033 enters the normal state after the oscillation circuit and the PLL circuit are stabilized
by the clock stabilization circuit.
(3) Software reset by register access
By setting the SRSTN_INSIDE register to “1” using the RST_CTL1 command, the internal circuit can be
reset. This operation is enabled in states other than a sleep state. After reset, the ML7065-033 enters the
normal state after the oscillation circuit and the PLL circuit are stabilized by the clock stabilization circuit.

ML7065-033 User’s Manual
Chapter 3 Power Management Function
8
3. Power Management Function
The ML7065-033 transitions to the following four states besides the normal communication states (receiving state and
transmitting state).
(1) Total-stop state
Indicates a reset state. The internal circuit is in the initialized state.
(2) Sleep state
State where all the circuits are stopped. As for the internal register data, values prior to the sleep state are
retained. In a sleep state only, the device is returned to the normal state without being reset by asserting
the SRESETN pin or the SCEN pin.
(3) Suspended state
Only the oscillation circuit operates and a clock is supplied to the SCI only. For the internal register data,
the values prior to the suspended state are retained. The device can be returned to the normal state from
the SCI.
(4) Idle state
In this state, only the RF circuit is stopped. The device can be returned to the normal state from the SCI.

ML7065-033 User’s Manual
Chapter 4 Mode Setting
9
4. Mode Setting
The following normal operation modes and test modes are available for the ML7065-033.
Normal operation mode
Pin setting
Mode
No. MODE1 MODE2 MODE3 Description
1 L L L
SCI: LSB data input/output
CLKOUT pin: No OSC clock is output after reset release.
2 H L L
SCI: MSB data input/output
CLKOUT pin: No OSC clock is output after reset release.
3 L H L
SCI: LSB data input/output
CLKOUT pin: The OSC clock is output after reset release.
4 H H L
SCI: MSB data input/output
CLKOUT pin: The OSC clock is output after reset release.
Test mode
By setting the MODE3 pin to a “H” level, a test mode is entered.
The test mode is not released to the public.

ML7065-033 User’s Manual
Chapter 5 IEEE802.15.4 Modulation
10
5. IEEE802.15.4 Modulation
5.1 Block Diagram of the Modulator Circuit
(1) Binary data for transmission to be input to a modem is mapped to the 16 types of symbols “0” to “F” every
four bits in the order the binary data is input.
(2) As shown in the following table, Symbol-to-Chip Mapping, each symbol is mapped to a set of 32 chip data
values that corresponds.
Symbol-to-Chip Mapping
Data Symbol
(Hex)
Data Symbol
(Binary)
b0b1b2b3
Chip Values
(c0, c1,c2, •••••,c29,c30,c31)
(I, Q , I , •••••, Q , I , Q)
0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0
1 1 0 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0
2 0 1 0 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0
3 1 1 0 0 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1
4 0 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1
5 1 0 1 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0
6 0 1 1 0 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1
7 1 1 1 0 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1
8 0 0 0 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1
9 1 0 0 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1
A
0 1 0 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1
B 1 1 0 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0
C 0 0 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0
D 1 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1
E 0 1 1 1 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0
F 1 1 1 1 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0
Bit-to-
Symbol
Symbol
-to-Chip
Symbol
Pulse
Shaping
Symbol
Modulated
Signal
Binary
Data
(b0,b1,b2,b3,b4,b5,b6,b7,b8,•••)
(b0,b1,b2,b3)
(b4,b5,b6,b7)
••••••
(c0,c1,•••••,c30,c31)
(c0,c1,•••••,c30,c31)
••••••
Quadrature
Modulator
Symbol

ML7065-033 User’s Manual
Chapter 5 IEEE802.15.4 Modulation
11
5.2 Chip Order
For the 32 chips corresponding to each symbol, chips in the even-number order of c0, c2,•••••, c28, c30 are
configured as I data and the chips in the odd-number order of c1, c3, •••••, c29, c31 are configured as Q data. Also,
because of OQPSK modulation, the Q data delays from I data by 1/2 chip as shown below.
5.3 Pulse Waveforms
As shown below, the waveforms of the I and Q data are created in the front stage of the orthogonal modulator.
c0
c1
c2
c3c5
c4c0
c27 c29 c31
c26 c28 c30
c1
2Tc
Tc
I-Phase
Q-Phase
c0c2c
4c 6
c1c
3c 5c 7c 31
c30
c29 c27 c25
c28 c26 c24 c22
c23 c21
“1” “0” “1” “0” “0” “0” “1” “0” “0”
“1” “1” “0” “1” “1” “1” “0” “0” “0” “0”
2Tc
Tc
t
t
I-Phase
Q-Phase
p(t) =
sin (πt / 2Tc) ••••• 0 ≤t ≤2Tc
0 ••••• otherwise

ML7065-033 User’s Manual
Chapter 5 IEEE802.15.4 Modulation
12
5.4 Packet Format
The general packets that are sent from the ML7065-033 are structured as follows.
Refer to IEEE802.15.4-2003 for the detail specification of the format.
Preamble Start of frame
Delimiter
Frame length
(7 bits)
Reserved
(1 bit) PSDU
4 bytes 1 byte 1 byte 127 bytes max.
(1) Preamble : 0000 0000 0000 0000 0000 0000 0000 0000 (symbol “0 0 0 0”)
(2) Start of frame delimiter
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
1 1 1 0 0 1 0 1
(3) Frame length: The byte count of the PSDU is represented with 7 bits.
(4) PSDU (PHY layer service data unit): Data frame of the PHY layer
Synchronization header PHY header PHY payload
(symbol “7A”)

ML7065-033 User’s Manual
Chapter 6 Synchronous Communication Interface (SCI) Function
13
6. Synchronous Communication Interface (SCI) Function
The ML7065-033 is equipped with a synchronous communication interface (SCI) as the host interface. SCI is
available for a slave mode only. The interrupt pin, SINT, is used for reading data from the ML7065-033 to the host.
Waveform definition:
The SCI that is incorporated in the ML7065-033 is applied to a slave mode only and the input clock from the host is
applied to the rising edge only.
Two types of transmit/receive data formats are available for selection, big endian and little endian. Set a mode using
the MODE pin. Note that the frequencies of SCLK in a suspended state are restricted.
Refer to Section 8.6, “Synchronous Communication Interface (SCI) Characteristics.”
D7 D6 •••• D1 D0
••••
••••
D7 D6 •••• D1 D0
D0 D1 •••• D6 D7
D0 D1 •••• D6 D7
SCEN
SCLK
(SCLK: Positive clock)
SCLK
(SCLK: Negative clock)
SDI
(Big endian)
SDO
(
Bi
g
endian
)
SDI
(Little endian)
SDO
(Little endian)
Waveforms for SCI Clocks and Data Transmission/Reception

ML7065-033 User’s Manual
Chapter 6 Synchronous Communication Interface (SCI) Function
14
Transaction:
With the 1st transfer byte, a request and a status are exchanged between the host and the ML7065-033. If transfer of
host→ML7065-033, ML7065-033→host, or both is possible, data from the 2nd byte onward is transferred.
1st transfer byte
The host sends a request to the ML7065-033, and, at the same time, the ML7065-033 sends a status to the host. A
request and a status use bits 3 to 0 only (positive logic) as shown below and other bits become Don't Care. See the
table below for details.
When both bits of the same position in a request and a status that are sent from the host and the ML7065 are in a “1”
state, the Request/Enable of that request and status becomes valid.
Access
destination Bit Request (host→ML7065-033) Status (ML7065-033→host)
3 Data write request Data write enable
Config 2 Data read enable Data read request
1 Data write request Data write enableMAC (RAM)
/PHY 0 Data read enable Data read request
2nd transfer byte
Indicates the transfer data length (length) including the command and data (variable within the range from 1 to 255).
3rd transfer byte and onward
Indicates the data (variable within the range from 1 to 255) associated with the command.
*Note that the following restrictions are applied for the data lengths at security ON.
ieee_mode Security suit name Data length (Max).
AES_CTR 122 bytes
AES_CCM_128 106 bytes
AES_CCM_64 114 bytes
AES_CCM_32 118bytes
AES_CBC_MAC_128 111 bytes
AES_CBC_MAC_64 119 bytes
IEEE mode
AES_CBC_MAC_32 123 byte
AES_MIC_32 118 bytes
AES_MIC_64 114 bytes
AES_MIC_128 106 bytes
AES_ENC 122 bytes
AES_ENC_MOC_128 106 bytes
AES_ENC_MOC_64 114 bytes
AES_ENC_MOC_32 118 bytes
ZigBee mode
AES_ECB 127 bytes
Note: Data is transferred in bytes with LSB first. (Since data is fixed to 2 bytes [15: 0] for Config parallel access,
data input/output is performed in the order of [7: 0] and [15: 8])