ON Semiconductor XGS 12000 User manual

©Semiconductor Components Industries, LLC, 2018
April, 2020 −Rev. 3
1Publication Order Number:
XGS12M/D
XGS 12000, XGS 9400 and
XGS 8000 Global Shutter
CMOS Image Sensors
XGS Family
Description
The XGS CMOS image sensor family provides high resolution,
high performance global shutter image capture. The family comes in
different resolutions in a single package; 8.8, 9.4 and 12.6 Megapixels
with up to 1−inch optical format. The 21 mm x 20 mm package makes
the XGS family particularly suited for integration in 29 mm x 29 mm
camera formats. The high speed, 12−bit output maximally leverages
interfaces such as USB 3.2, Thunderboltt2 and 10 GigE.
Image data is read out through a column ADC architecture and then
transferred over a HiSPi interface. On−chip logic, programmable via
the serial interface, generates internal timing for integration and
readout control. Up to three register conÂfigurations can be
programmed and sequentially enabled (frame by frame) using a single
command over the control interface.
Table 1. KEY PERFORMANCE PARAMETERS
Parameter Typical Value
Optical Format XGS 12000 1−inch (16.4 mm Diagonal)
XGS 9400 1/1.2−inch (13.9 mm Diagonal)
XGS 8000 1/1.1−inch (14.8 mm Diagonal)
Active Pixels XGS 12000 4096 (H) x 3072 (V)
XGS 9400 3072 (H) x 3072 (V)
XGS 8000 4096 (H) x 2160 (V)
Pixel Size 3.2 m
Color Filter Array Monochrome, Bayer
Shutter Type Global Shutter
Input Clock 32.4 MHz
Output Interface HiSPi (24 Lanes −777.6 Mbps/lane)
Frame Rate (12−bit) 24 Lanes (−X1)
XGS 12000 90 fps
XGS 9400 90 fps
XGS 8000 128 fps
12 Lanes (−X2)
XGS 9400 56 fps
XGS 8000 80 fps
6 Lanes (−X3)
XGS 12000 28 fps
Read Noise < 4 e−(1x), 1.9 e−(4x)
SNRMAX 40 dB
Dynamic Range 68 dB
Supply Voltages 1.2V, 2.8 V, 3 V (0.4 V, 1.8 V Optional)
Power Consumption 1 W (Full Speed, Full Resolution)
Operating Temp. −40°C to 85°C (Junction)
Package 163−pin CLGA (Ceramic Land Grid Array)
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Features
•On−chip 12−bit Column ADCs
•10−bit Mode with Increased Frame Rate of
100 fps (24−lane) at Full Resolution
•Companding Mode for 60 fps (12−lane)
and 30 fps (6−lane) at Full Resolution
•Data Interface: 24−lane HiSPi (Scalable
Low−Voltage Signaling)
•Configurable Number of HiSPi Lanes:
24, 18, 12 or 6 Lanes
•Two−Wire (I2C) and Four−Wire (SPI)
Serial Interface
•Triggered Integration and Readout Control
•Programmable Control for up to 8 Regions
of Interest (ROI)
•Context Switching
•These Devices are Pb−Free, Halogen Free/
BFR Free and are RoHS Compliant
Applications
•Machine Vision
•Security
•Intelligent Transportation Systems (ITS)
•Broadcasting
•Medical
•Scientific

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ORDERING INFORMATION
Table 2. ORDERABLE PART NUMBERS (Notes 1 and 2)
Part Number Minimum Order Quantity Product Description Speed Grade Resolution (H x V)
NOIX1SN012KB*LTI 25 12.6 Mp Mono 0°CRA 24 Lanes 4096 x 3072
NOIX1SN012KB*LTI1 4
NOIX1SE012KB*LTI 25 12.6 Mp Color 0°CRA
NOIX1SE012KB*LTI1 4
NOIX1SF012KB*LTI 25 12.6 Mp Color 7.3°CRA
NOIX1SF012KB*LTI1 4
NOIX3SN012KB*LTI 25 12.6 Mp Mono 0°CRA 6 Lanes
NOIX3SN012KB*LTI1 4
NOIX3SE012KB*LTI 25 12.6 Mp Color 0°CRA
NOIX3SE012KB*LTI1 4
NOIX1SN9400B*LTI 25 9.4 Mp Mono 0°CRA 24 Lanes 3072 x 3072
NOIX1SN9400B*LTI1 4
NOIX1SE9400B*LTI 25 9.4 Mp Color 0°CRA
NOIX1SE9400B*LTI1 4
NOIX2SN9400B*LTI 25 9.4 Mp Mono 0°CRA 12 Lanes
NOIX2SN9400B*LTI1 4
NOIX2SE9400B*LTI 25 9.4 Mp Color 0°CRA
NOIX2SE9400B*LTI 4
NOIX1SN8000B*LTI 25 8.8 Mp Mono 0°CRA 24 Lanes 4096 x 2160
NOIX1SN8000B*LTI1 4
NOIX1SE8000B*LTI 25 8.8 Mp Color 0°CRA
NOIX1SE8000B*LTI1 4
NOIX2SF8000B*LTI 25 8.8 Mp Color 7.3°CRA 12 Lanes
NOIX2SF8000B*LTI1 4
NOIX2SN8000B*LTI 25 8.8 Mp Mono 0°CRA
NOIX2SN8000B*LTI1 4
NOIX2SE8000B*LTI 25 8.8 Mp Color 0°CRA
NOIX2SE8000B*LTI1 4
1. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image
sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.
2. All devices listed in Table 2 are equipped with microlenses.
Table 3. ORDERING INFORMATION EVALUATION KITS
Part Number Product Description Additional Information
NOIX1SN012KBLFB−GEVB Sensor Headboard (12.6 Mp, Mono, 24−Lane) Demo Kit Headboard (incl.
NOIX1SN012KB−LTI) (Note 3)
NOIX1SE012KBLFB−GEVB Sensor Headboard (12.6 Mp, Color, 24−Lane) Demo Kit Headboard (incl.
NOIX1SE012KB−LTI) (Note 3)
AGBAN6CS−GEVK Frame Buffer Demo Board AP21088 including Power Adapter
AGB1N0CS−GEVK Demo 3 Board FPGA Base Board including USB Cable and
Tripod
3. Sensors are soldered to the headboard.

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GENERAL DESCRIPTION
The XGS family from ON Semiconductor covers three
resolutions: 12.6 Mp, 9.4 Mp and 8.8 Mp and three speed
grades (24, 12 or 6 HiSPi lanes). Refer to Table 2 for an
overview of the available combinations of resolution and
speed. Various operating modes enable flexible sensor
operation to meet application specific requirements such as
reduced data rate implemented by HiSPi lane multiplexing.
FUNCTIONAL OVERVIEW
The XGS family features global shutter technology for
accurate capture of moving objects. Global shutter requires
all pixels to simultaneously integrate light although the
subsequent readout is sequential. Note that integration and
readout can occur in parallel; while reading out one frame,
integration of the next frame can start (i.e. pipelined
operation). The core of the sensor is the 12.6 Mp active pixel
array.
Figure 1 gives an overview of the major functional blocks
of the XGS sensor.
ROW DRIVER
1 clock lane
1, 2, 3 or 4 data lanes
1 clock lane
1, 2, 3 or 4 data lanes
PIXEL ARRAY
(4096 x 3072)
COLUMN STRUCTURE (G
Rand GB)
COLUMN ADC (GRand GB)
DIGITAL GAIN / DATA PEDESTAL
COLUMN STRUCTURE (R and B)
COLUMN ADC (R and B)
DIGITAL GAIN / DATA PEDESTAL
HiSPi HiSPi HiSPi
DIGITAL MUX DIGITAL MUX DIGITAL MUX
DIGITAL MUX DIGITAL MUX DIGITAL MUX
HiSPi HiSPi HiSPi
MONITOR_[2:0]
SEQUENCER
TRIG_INT
TRIG_RD
RESET_N
BIAS
I2C/SPI DECODER
PLL
EXTCLK
Figure 1. Functional Block Diagram (XGS 12000)
I2C/SPI

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The on−chip logic, programmable through the Two−Wire
(I2C) or Four−Wire (SPI) Serial Interface, generates all
internal timing for integration control and frame readout.
Once a row has been read, the data from the columns is
sequenced through an analog signal chain (providing coarse
analog gain) and then through a 12−bit column ADC. The
data from the ADCs is first stored in the on−chip column
memory bank prior to being processed by the digital data
path (which provides additional data processing including
digital gain and offset). The digital multiplexer can be
configured to reduce the number of active data lanes. The
maximum output pixel rate on a single lane is 64.8
Megapixel per second, corresponding to a clock rate of 32.4
MHz.
Advanced trigger functions enable synchronization to
external events (triggered master and slave mode) but also
allow synchronizing image readout with the host (receiver)
on a frame or line basis (triggered frame or line readout). The
sensor supports configuration of up to eight independent
ROIs and up to three register configurations (contexts) can
be programmed and sequentially applied (frame by frame)
with a single command over the control interface.
Refer to Figure 1 for the functional blocks described
hereafter.
•Two−Wire Serial Interface (I2C)
I2C−compatible, two−wire serial interface enables user
interaction with sensor.
•(Four−Wire) Serial Peripheral Interface (SPI)
The Four−Wire serial interface can be used as an
alternative to the two−wire interface. The SPI enables
faster sensor (re−)configuration compared to the
two−wire serial interface.
•EXTCLK
The nominal input−clock frequency is 32.4 MHz. This
clock serves as the base clock for the derived clock
domains required by the internal sub−blocks and HiSPi
output interface.
•Phase−locked Loop (PLL)
The on−chip phase−locked loop generates all the
internal system clocks, including the HiSPi clock.
•Bias Generator
The bias generator generates the required reference
currents used by the on−chip blocks.
•Sequencer
The sequencer generates the sensor timing and controls
the image core which contains all pixels, driving and
readout circuits. It controls the ADC circuits and
provides the necessary information to the digital data
path. The sequencer operating and readout modes (ROI
readout, subsampling...) can be configured through the
SPI interface. The readout parameters are synchronized
to frame boundaries to support dynamic reconfiguration
without generating any corrupted images.
•Row Driver
The row drivers generate the reset and select signals
used to operate the pixel array.
•Monitor Pins
The sequencer can communicate its internal states
through the monitor output pins.
•Column Structure
The column structure contains the analog circuits
necessary to ensure a proper transfer of the signal to the
column ADC. This structure includes the column
amplifiers which can be used to apply analog gain to
the signal before these are converted by the ADCs. The
sensor supports analog gain of 1x, 2x and 4x. The
analog gain is applied globally to all pixels.
•Column ADC
For each column, a 12−bit ADC converts the analog
signal into a digital value.
•Digital Gain
A linear, digital gain ranging from 1/32x up to 2x can
be configured separately for each color channel in steps
of 1/32.
•Data Pedestal
This block adds a user programmable, per color channel
digital offset to the pixel values.
•Digital Mux
This block handles the lane multiplexing which can be
used to reduce the number of output lanes.
•HiSPi
The 24 HiSPi lanes are laid out in six identical HiSPi
blocks. Each block consists of four data lanes and one
clock lane. The number of active data lanes (1, 2, 3 or
4) depends on the selected multiplex mode.

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PIXEL DATA FORMAT
PIXEL ARRAY STRUCTURE
The XGS 12000 active pixel array consists of 4096
columns by 3072 rows of optically active pixels. The active
resolution of XGS 8000 and XGS 9600 can be found in
Table 1. As shown in Figures 2 through 4, the active array
is surrounded by a four−pixel wide collar of interpolation
pixels for color interpolation purposes. The entire active
array (including interpolation pixels) is isolated from the
black reference pixels by a collar of dummy pixels. The
purpose of these dummy pixels is to improve the image
uniformity within the active area. The complete pixel array,
including all dummy, black and interpolation pixels,
consists of a total of 4176 columns and 3102 rows (2190
rows for XGS 8000). The sensor’s active pixel array is
shown with the first pixel in the bottom left corner (refer to
Figures 2 through 4).
The color version of the sensor has a Bayer Color Filter
Array (CFA) placed on top of the pixels. The mapping of the
CFA with respect to the active pixel array is shown in
Figure 2 through 4.
PIXEL ARRAY READOUT
The electrical black reference lines are read out at the start
of every frame. The number of lines to be read out is
configurable through the M lines configuration
(configurable for each context). The ROI configurations are
processed after the black reference lines. The lines
accessible through the window configurations are limited to
the active area region, including interpolation rows. Note
that the windows are configured in logical kernel addresses.
A kernel contains four image lines and the kernel with
logical address 0 corresponds to the lines with physical
addresses:
−15:18 for XGS 12000 and XGS 9400
−471:474 for XGS 8000
Each window configuration consists of two parameters: a
start address and window height. The configured windows
are reordered such that the ROI with the smallest start
address is read out first. After completion of the readout of
the first ROI, the line address pointer will be initialized to the
start address of the next ROI. For overlapping windows, the
sequencer will just continue the readout. Note that the
overlapping part is read out only once.
Lines are read out from left to right and each line contains
different types of pixels. A line starts with 4 dummy pixels
followed by 24 electrical black reference pixels. The regular
image pixels are preceded and followed by 4 dummy pixels.
Dummy pixels are identical to the regular pixels, but may
deviate in performance. Therefore the dummy pixels should
be discarded. Each line is ended by another 32 black
reference pixels followed by 4 dummy pixels.

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Readout Order
Frame readout starts by setting the read address to the first
row of the configured ROI. Once the row is read, the read
address is incremented and the next row is read. This cycle
continues until the last row of the ROI has been read. The
incremental addressing scheme is depicted in Figure 5.
Figure 5. Incremental Row Addressing Sequence
Subsampled Readout
During subsampled readout only a subset of the pixel
array is read out, enabling faster read out with the same field
of view but at the expense of reduced image resolution. In
order to support subsampling on both monochrome and
color sensors, XGS supports two different subsampling
schemes:
1. Read One Skip One
In this mode, one out of four pixels is selected for
readout by selecting every other line and column
in the image array. The Read−One−Skip−One
mode is depicted in Figure 6 below. This
subsampling mode does not preserve the Bayer
pattern so it is recommended for monochrome
devices only.
Figure 6. Monochrome Subsampling
(Read−1−Skip−1)
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
= Skip
= Read
X
Y
2. Read Two Skip Two
The Read−Two−Skip−Two subsampling scheme is
recommended for color sensors as it preserves the
Bayer pattern. When using the
Read−Two−Skip−Two scheme, the sensor first
reads two rows and then skips two rows. From
each row being read, first two adjacent pixels will
be read, then two will be skipped. This readout
scheme is depicted in Figure 7.
Figure 7. Color Subsampling (Read−2−Skip−2)
= Skip
= Read
X
Y
Reverse Readout
XGS supports reverse readout in the vertical (Y−)
direction. If active_config_reg.active_reversed is set to 1,
the ROIs will be read top to bottom instead of the default
(active_config_reg.active_reversed = 0) bottom to top
readout direction.

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CONFIGURATION AND PINOUT
TYPICAL CONFIGURATIONS
Two possible configuration examples are depicted in the
figures below. The first example (Figure 8) uses the
Four−Wire Serial Interface while the second example
(Figure 9) depicts a typical Two−Wire Serial Interface
implementation. Pin connections to (and from) the sensor
and power supply configurations are shown in the figures
below. The recommended decoupling capacitors are listed
in Table 4.
Configuration Example:
•VDD_SLVS = 1.2 V (or 0.4 V); VDD = 1.2 V; VDD_IO
= 2.8 V (or 1.8 V); VDD_PLL = 2.8 V;
•VAA = 2.8 V; VAA_PIX = 3.0 V; VAA_RD = 3.0 V;
VAA_PIX_BST = 3.0 V
•24 data lanes + 2 clock lanes

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Figure 8. Typical Configuration (Four−Wire Serial Interface)
C2C1
VAA
C2C1
VAA_PIX
C2C1
VAA_RD
C2C1
VAA_PIX
_BST
C2C1
VDD_IO
C2C1
VDD
C2C1
VDD_SLVS
C2C1
VDD_PLL
XGS 12000
XGS 9400
XGS 8000
GND
FWSI_EN
32.4 MHz
EXTCLK
From Controller
SDATA
SCLK
CS_N
RESET_N
TRIG_INT
TRIG_RD
C3 C3 C3 C3 C3 C3 C4 C4 C4 C4 C4C4 C5 C5
VAAPIX_A0
VAAPIX_A1
VAAPIX_A2
VAAPIX_A3
VAAPIX_A4
VAAPIX_A5
VAAPIX_B0
VAAPIX_B1
VAAPIX_B2
VAAPIX_B3
VAAPIX_B4
VAAPIX_B5
VAAPIX_C0
VAAPIX_C1
D_CLK_[2,3]_P
D_CLK_[2,3]_N
DATA_[0:23]_P
DATA_[0:23]_N
MONITOR_0
MONITOR_1
MONITOR_2
SDATAOUT
To Receiver
Digital I/O
(2.8 V)
Digital Core
(1.2 V)
HiSPi
(1.2 V)
PLL
(2.8 V)
Analog
(2.8 V)
Analog (Pixel)
(3.0 V)
VDD
VDD_SLVS
VDD_PLL
VAA
VAA_PIX
VAA_RD
VAA_PIX_BST
VDD_IO
RESERVED
100
100
N.C.
10k
1. All power supplies must be adequately decoupled (see Table 4) Decoupling.
2. In this example, only 2 (out of 6) HiSPi clock lanes are used; D_CLK_2 to sample data on the even data lanes (top readout) and
D_CLK_3 to sample data on the odd data lanes (bottom readout).
3. The active HiSPi lanes need to be terminated using 100 resistors placed as close to the receiver as possible.
4. Unused HiSPi outputs (data and/or clock lanes) must be left floating.
5. It is highly recommended to route the monitor signals to the receiver (FPGA) for debugging purposes. If the MONITOR outputs
are not used, they must be left floating.
6. If the TRIGGER inputs are not used, tie them to GND.
7. No distinction is made between analog and digital ground (internally shorted).
8. FWSI_EN must be connected to VDD_IO through a 10 kresistor (enable Four−Wire Serial Interface).
9. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
10. Digital inputs RESET_N and CS_N are both active low.

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Figure 9. Typical Configuration (Two−Wire Serial Interface)
1. All power supplies must be adequately decoupled (see Table 4) Decoupling.
2. In this example, only 2 (out of 6) HiSPi clock lanes are used; D_CLK_2 to sample data on the even data lanes (top readout) and
D_CLK_3 to sample data on the odd data lanes (bottom readout).
3. The active HiSPi lanes need to be terminated using 100 resistors placed as close to the receiver as possible.
4. Unused HiSPi outputs (data and/or clock lanes) must be left floating.
5. It is highly recommended to route the monitor signals to the receiver (FPGA) for debugging purposes. If the MONITOR outputs
are not used, they must be left floating.
6. If the TRIGGER inputs are not used, tie them to GND.
7. No distinction is made between analog and digital ground (internally shorted).
8. FWSI_EN and CS_N must be tied to GND when using the Two−Wire Serial Interface. Sdataout can be left floating.
9. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
10. Digital input RESET_N is active low.
11. ON Semiconductor recommends using a 1.5 kpull−up resistor to VDD_IO on both Sclk and Sdata.
C2C1
VAA
C2C1
VAA_PIX
C2C1
VAA_RD
C2C1
VAA_PIX
_BST
C2C1
VDD_IO
C2C1
VDD
C2C1
VDD_SLVS
C2C1
VDD_PLL
XGS 12000
XGS 9600
XGS 8000
GND
FWSI_EN
32.4 MHz
EXTCLK
From Controller
SDATA
SCLK
CS_N
RESET_N
TRIG_INT
TRIG_RD
C3 C3 C3 C3 C3 C3 C4 C4 C4 C4 C4C4 C5 C5
VAAPIX_A0
VAAPIX_A1
VAAPIX_A2
VAAPIX_A3
VAAPIX_A4
VAAPIX_A5
VAAPIX_B0
VAAPIX_B1
VAAPIX_B2
VAAPIX_B3
VAAPIX_B4
VAAPIX_B5
VAAPIX_C0
VAAPIX_C1
D_CLK_[2,3]_P
D_CLK_[2,3]_N
DATA_[0:23]_P
DATA_[0:23]_N
MONITOR_0
MONITOR_1
MONITOR_2
SDATAOUT
To Receiver
Digital I/O
(2.8 V)
Digital Core
(1.2 V)
HiSPi
(1.2 V)
PLL
(2.8 V)
Analog
(2.8 V)
Analog (Pixel)
(3.0 V)
VDD
VDD_SLVS
VDD_PLL
VAA
VAA_PIX
VAA_RD
VAA_PIX_BST
VDD_IO
100 Ω
100 Ω
1.5 KΩ
RESERVEDN.C.
N.C.
1.5 KΩ

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PIN LIST
Table 5. PIN DESCRIPTIONS (163−PIN LGA PACKAGE)
Name LGA Pin Name Type Description
GND A1, A18, C3, C7, C12, C16, F4, F15,
G3, G16, J4, J15, K3, K16, M4, M11,
M15, N8, N11, P7, P12, T3, T10, T16,
V1, V18, D12, F10, G8, G9, G10, G11,
P6, P13
Ground Ground
VDD_PLL C10 Power PLL Power Supply
VAA C5, C14, M9, M10, N3, N9, N10, N16,
R5, R6, R13, R14, T9
Power Analog Supply
VAA_RD C6, C13, T5, T14 Power Analog Supply for Row Driver
VDD_IO C8, C9, C11, P3, P16 Power I/O Supply
FWSI_EN D10 Input ’HIGH’ −> Four−Wire Serial Interface (SPI)
’LOW’ −> Two−Wire Serial Interface (I2C)
SDATA D11 Input/
Output
Four−Wire Serial Interface (SPI): SPI Slave In
Two−Wire Serial Interface (I2C): Serial Data Input/
Output
VAA_PIX D5, D14, P5, P14 Power Pixel Supply
VDD D6, D13, E3, E16, F7, F12, H3, H16,
J7, J12, L3, L16, M7, M12
Power Digital Supply
MONITOR_2 D7 Output Monitor Output 2. If unused, do not connect.
MONITOR_1 D8 Output Monitor Output 1. If unused, do not connect.
EXTCLK D9 Input External Clock Input
SDATAOUT E10 Output Four−Wire Serial Interface (SPI): SPI Slave Out
Two−Wire Serial Interface (I2C): Do not connect
TRIG_RD E11 Input Trigger Input for Readout Control. If unused, connect to
ground.
DATA_0_N E12 HiSPi Differential Data Channel [0], Negative
DATA_0_P E13 HiSPi Differential Data Channel [0], Positive
DATA_2_N E14 HiSPi Differential Data Channel [2], Negative
DATA_2_P E15 HiSPi Differential Data Channel [2], Positive
DATA_3_P E4 HiSPi Differential Data Channel [3], Positive
DATA_3_N E5 HiSPi Differential Data Channel [3], Negative
DATA_1_P E6 HiSPi Differential Data Channel [1], Positive
DATA_1_N E7 HiSPi Differential Data Channel [1], Negative
MONITOR_0 E8 Output Monitor Output 0. If unused do not connect.
CS_N E9 Input Four−Wire Serial Interface (SPI): SPI Chip Select (active low)
Two−Wire Serial Interface (I2C): Connect to GND
TRIG_INT F11 Input Trigger Input for Integration Control. If unused, connect to
ground.
D_CLK_0_N F13 HiSPi Differential Clock [0], Negative
D_CLK_0_P F14 HiSPi Differential Clock [0], Positive
VDD_SLVS F3, F16, J3, J16, M3, M16 Power HiSPi Supply
D_CLK_1_P F5 HiSPi Differential Clock [1], Positive
D_CLK_1_N F6 HiSPi Differential Clock [1], Negative
RESET_N F8 Input Asynchronous Hard Reset (Active Low)
SCLK F9 Input Serial Interface Clock Input

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Table 5. PIN DESCRIPTIONS (163−PIN LGA PACKAGE)
Name DescriptionTypeLGA Pin Name
DATA_4_N G12 HiSPi Differential Data Channel [4], Negative
DATA_4_P G13 HiSPi Differential Data Channel [4], Positive
DATA_6_N G14 HiSPi Differential Data Channel [6], Negative
DATA_6_P G15 HiSPi Differential Data Channel [6], Positive
DATA_7_P G4 HiSPi Differential Data Channel [7], Positive
DATA_7_N G5 HiSPi Differential Data Channel [7], Negative
DATA_5_P G6 HiSPi Differential Data Channel [5], Positive
DATA_5_N G7 HiSPi Differential Data Channel [5], Negative
DATA_8_N H12 HiSPi Differential Data Channel [8], Negative
DATA_8_P H13 HiSPi Differential Data Channel [8], Positive
DATA_10_N H14 HiSPi Differential Data Channel [10], Negative
DATA_10_P H15 HiSPi Differential Data Channel [10], Positive
DATA_11_P H4 HiSPi Differential Data Channel [11], Positive
DATA_11_N H5 HiSPi Differential Data Channel [11], Negative
DATA_9_P H6 HiSPi Differential Data Channel [9], Positive
DATA_9_N H7 HiSPi Differential Data Channel [9], Negative
D_CLK_2_N J13 HiSPi Differential Clock [2], Negative
D_CLK_2_P J14 HiSPi Differential Clock [2], Positive
D_CLK_3_P J5 HiSPi Differential Clock [3], Positive
D_CLK_3_N J6 HiSPi Differential Clock [3], Negative
DATA_12_N K12 HiSPi Differential Data Channel [12], Negative
DATA_12_P K13 HiSPi Differential Data Channel [12], Positive
DATA_14_N K14 HiSPi Differential Data Channel [14], Negative
DATA_14_P K15 HiSPi Differential Data Channel [14], Positive
DATA_15_P K4 HiSPi Differential Data Channel [15], Positive
DATA_15_N K5 HiSPi Differential Data Channel [15], Negative
DATA_13_P K6 HiSPi Differential Data Channel [13], Positive
DATA_13_N K7 HiSPi Differential Data Channel [13], Negative
DATA_16_N L12 HiSPi Differential Data Channel [16], Negative
DATA_16_P L13 HiSPi Differential Data Channel [16], Positive
DATA_18_N L14 HiSPi Differential Data Channel [18], Negative
DATA_18_P L15 HiSPi Differential Data Channel [18], Positive
DATA_19_P L4 HiSPi Differential Data Channel [19], Positive
DATA_19_N L5 HiSPi Differential Data Channel [19], Negative
DATA_17_P L6 HiSPi Differential Data Channel [17], Positive
DATA_17_N L7 HiSPi Differential Data Channel [17], Negative
D_CLK_4_N M13 HiSPi Differential Clock [4], Negative
D_CLK_4_P M14 HiSPi Differential Clock [4], Positive
D_CLK_5_P M5 HiSPi Differential Clock [5], Positive
D_CLK_5_N M6 HiSPi Differential Clock [5], Negative
DATA_20_N N12 HiSPi Differential Data Channel [20], Negative
DATA_20_P N13 HiSPi Differential Data Channel [20], Positive

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Table 5. PIN DESCRIPTIONS (163−PIN LGA PACKAGE)
Name DescriptionTypeLGA Pin Name
DATA_22_N N14 HiSPi Differential Data Channel [22], Negative
DATA_22_P N15 HiSPi Differential Data Channel [22], Positive
DATA_23_P N4 HiSPi Differential Data Channel [23], Positive
DATA_23_N N5 HiSPi Differential Data Channel [23], Negative
DATA_21_P N6 HiSPi Differential Data Channel [21], Positive
DATA_21_N N7 HiSPi Differential Data Channel [21], Negative
VAA_PIX_A0 P10 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND)
VAA_PIX_A1 P11 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND)
VAA_PIX_A2 R10 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND)
VAA_PIX_A3 T11 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND)
VAA_PIX_A4 T12 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND)
VAA_PIX_A5 T6 Decoupling External Noise Decoupling (0.1 F + 4.7 F to GND)
VAA_PIX_B0 P8 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND)
VAA_PIX_B1 P9 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND)
VAA_PIX_B2 R8 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND)
VAA_PIX_B3 R9 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND)
VAA_PIX_B4 T7 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND)
VAA_PIX_B5 T8 Decoupling External Noise Decoupling (0.1 F + 2.2 F to GND)
VAA_PIX_C0 R11 Decoupling External Noise Decoupling (0.1 F to GND)
VAA_PIX_C1 T13 Decoupling External Noise Decoupling (0.1 F to GND)
VAA_PIX_BST R7, R12 Power Pixel Booster Supply
RESERVED P4, P15 N/A Reserved (do not connect)

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SENSOR STATES
After Power−Up and while the RESET_N pin is driven
low, the image sensor enters a RESET state until the
RESET_N signal is de−asserted.
Once the RESET_N pin is driven high, the sensor will
start loading the default configuration, stored in the on−chip
memory, into its configuration registers before it enters the
SLEEP state. While the sensor is in the SLEEP state, the
registers can be programmed using the serial interface. To
exit the SLEEP state and enter STANDBY mode, the
reset_register_reg (R0x3700) needs to be set to 0x001C.
This register upload enables all analog blocks (including the
on−chip PLL) and as soon as the sensor_status_reg
(R0x3706) returns value 0xEB, the sensor is in STANDBY
state.
When in STANDBY mode and upon user intervention the
training patterns or IDLE words can be sent over the video
interface allowing receiver locking. Once the host is ready
to receive image data, the sensor’s sequencer can be enabled.
Depending on the configured operation mode, the sensor
will either wait for user interaction or start grabbing images
autonomously (CAPTURE). Disabling the sequencer
moves the sensor state back to STANDBY. When disabling
the PLL and analog blocks while in STANDBY state, the
state machine will transition back to the SLEEP state.
Asserting the RESET_N pin forces the sensor to enter the
RESET state, regardless of the current state.
The sensor state diagram is shown in Figure 11.
Figure 11. Sensor State Diagram
RESET_N de−asserted −> internal initialization start
R0x3706 = 0xEB?? −> Initialization complete
*
*The sleep mode functionality is not available. Please use the standby mode when the sensor is idle. Technical details on this issue can be
found in the developer guide.
Table 6. TYPICAL TRANSITION TIMES
Sensor State Transition Time Description
POWER−DOWN 25 ms Time required to transition from POWER−DOWN to CAPTURE state.
SLEEP 10 ms Time required to transition from SLEEP to CAPTURE state.
STANDBY < 16 line times Time required to transition from STANDBY to CAPTURE state.
WAIT_ON_TRIGGER 2 line times + Synchroniza-
tion Delay (< 50 ns)
Time required to transition from WAIT_ON_TRIGGER to CAPTURE (upon
trigger action). A minimum delay of one line time will be added.

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POWER−UP AND POWER−DOWN SEQUENCE
POWER−UP SEQUENCE
The mandatory Power−Up sequence for the XGS sensor
is shown in Figure 12. The available power supplies
(VDD_IO, VDD_PLL, VDD, VAA, VAA_PIX,
VAA_PIX_BST, VAA_RD and VDD_SLVS) must have the
separation specified below.
1. Turn on VDD_IO power supply.
2. After 0−100 s, turn on VDD_PLL power supply.
3. After 0−100 s, turn on VDD power supply.
4. After 0−100 s, turn on VAA power supply.
5. Once VAA is stable, power up VAA_PIX,
VAA_PIX_BST and VAA_RD.
6. Once VAA_PIX, VAA_PIX_BST and VAA_RD are
stable, power up VDD_SLVS.
7. After VDD_SLVS is stable, enable EXTCLK.
8. After EXTCLK has settled, hold RESET_N low
(active) for at least 30 EXTCLK cycles before
de−asserting the reset signal.
9. The sensor then loads the default register values
from its on−chip memory. As soon as RESET_N is
pulled up (released), the sensor starts loading the
default register values from it internal memory.
When loading is done (sensor_status_reg
R0x3706[4:0] −>0x03), the sensor is ready to
accept user uploads. user uploads (e.g. to
configure a special mode).
10. Enable PLL and initialize sensor’s internal analog
blocks (reset_register_reg = 0x001C).
11. Once the analog blocks are initialized
(sensor_status_reg R03706 −> 0xEB), the sensor
transitions to STANDBY state and is ready to start
image operations.
12. Enable the sequencer to transition to the
CAPTURE state (general_config0_reg[0] = 1).
Figure 12. Power−Up Sequence
EXTCLK (32.4 MHz)

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Table 7. POWER−UP SEQUENCE
Symbol Definition Min Typ Max Unit
t0VDD_IO to VDD_PLL 0
(Note 5)
100 s
t1VDD_PLL to VDD 0
(Note 5)
100 s
t2VDD to VAA 0
(Note 5)
100 s
t3VAA to VAA_PIX/VAA_PIX_BST/VAA_RD 0
(Note 5)
100 s
t4VAA_PIX/VAA_PIX_BST/VAA_RD to VDD_SLVS 0
(Note 5)
100 s
tXEXTCLK Settling Time 0.5 30
(Note 4)
ms
t5Hard Reset 30 EXTCLK cycles
t6Internal Initialization (ready once R0x3706 reads back
0xEB)
1.5 ms
t7PLL Lock Time 10 70 s
t8Internal Initialization 6.5 ms
4. The EXTCLK settling time is component−dependent.
5. The minimum time does not include the settling time of the power supply.

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POWER−DOWN SEQUENCE
The recommended Power−Down sequence for the
XGS sensor is shown in Figure 13. The available power
supplies must have the separation specified below.
1. Disable CAPTURE if output is active by disabling
the sequencer (general_config0_reg[0] = 0).
2. Issue a sensor STANDBY request
(reset_register_reg[2] = 0). By default, the
transition to STANDBY state happens either after
completion of current row (or frame) readout or
instantly (configurable).
3. In STANDBY mode, activate reset by pulling
down the RESET_N line for at least 30
EXTCLKs.
4. EXTCLK can be stopped 0.5 ms after RESET_N.
5. Turn off power supplies one by one. Wait at least
until the supplies are stable before turning off the
next supply. (reverse order of Power−Up
Sequence).
Figure 13. Power−Down Sequence
EXTCLK (32.4 MHz)
Table 8. POWER−DOWN SEQUENCE
Symbol Definition Min Typ Max Unit
t0Hard Reset 30 EXTCLK
cycles
t1Reset to Disable EXTCLK 0.5 ms
t2VAA_RD / VAA_PIX_BST / VAA_PIX to VAA 0 (Note 6) s
t3VDD_SLVS to VAA_RD / VAA_PIX_BST / VAA_PIX 0 (Note 6) s
t4VAA_RD / VAA_PIX_BST / VAA_PIX to VAA 0 (Note 6) s
t5VAA to VDD 0 (Note 6) s
t6VDD to VDD_PLL 0 (Note 6) s
t7VDD_PLL to VDD_IO 0 (Note 6) s
6. The minimum time does not include the settling time of the power supply.
This manual suits for next models
29
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