XGS Family
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4
The on−chip logic, programmable through the Two−Wire
(I2C) or Four−Wire (SPI) Serial Interface, generates all
internal timing for integration control and frame readout.
Once a row has been read, the data from the columns is
sequenced through an analog signal chain (providing coarse
analog gain) and then through a 12−bit column ADC. The
data from the ADCs is first stored in the on−chip column
memory bank prior to being processed by the digital data
path (which provides additional data processing including
digital gain and offset). The digital multiplexer can be
configured to reduce the number of active data lanes. The
maximum output pixel rate on a single lane is 64.8
Megapixel per second, corresponding to a clock rate of 32.4
MHz.
Advanced trigger functions enable synchronization to
external events (triggered master and slave mode) but also
allow synchronizing image readout with the host (receiver)
on a frame or line basis (triggered frame or line readout). The
sensor supports configuration of up to eight independent
ROIs and up to three register configurations (contexts) can
be programmed and sequentially applied (frame by frame)
with a single command over the control interface.
Refer to Figure 1 for the functional blocks described
hereafter.
•Two−Wire Serial Interface (I2C)
I2C−compatible, two−wire serial interface enables user
interaction with sensor.
•(Four−Wire) Serial Peripheral Interface (SPI)
The Four−Wire serial interface can be used as an
alternative to the two−wire interface. The SPI enables
faster sensor (re−)configuration compared to the
two−wire serial interface.
•EXTCLK
The nominal input−clock frequency is 32.4 MHz. This
clock serves as the base clock for the derived clock
domains required by the internal sub−blocks and HiSPi
output interface.
•Phase−locked Loop (PLL)
The on−chip phase−locked loop generates all the
internal system clocks, including the HiSPi clock.
•Bias Generator
The bias generator generates the required reference
currents used by the on−chip blocks.
•Sequencer
The sequencer generates the sensor timing and controls
the image core which contains all pixels, driving and
readout circuits. It controls the ADC circuits and
provides the necessary information to the digital data
path. The sequencer operating and readout modes (ROI
readout, subsampling...) can be configured through the
SPI interface. The readout parameters are synchronized
to frame boundaries to support dynamic reconfiguration
without generating any corrupted images.
•Row Driver
The row drivers generate the reset and select signals
used to operate the pixel array.
•Monitor Pins
The sequencer can communicate its internal states
through the monitor output pins.
•Column Structure
The column structure contains the analog circuits
necessary to ensure a proper transfer of the signal to the
column ADC. This structure includes the column
amplifiers which can be used to apply analog gain to
the signal before these are converted by the ADCs. The
sensor supports analog gain of 1x, 2x and 4x. The
analog gain is applied globally to all pixels.
•Column ADC
For each column, a 12−bit ADC converts the analog
signal into a digital value.
•Digital Gain
A linear, digital gain ranging from 1/32x up to 2x can
be configured separately for each color channel in steps
of 1/32.
•Data Pedestal
This block adds a user programmable, per color channel
digital offset to the pixel values.
•Digital Mux
This block handles the lane multiplexing which can be
used to reduce the number of output lanes.
•HiSPi
The 24 HiSPi lanes are laid out in six identical HiSPi
blocks. Each block consists of four data lanes and one
clock lane. The number of active data lanes (1, 2, 3 or
4) depends on the selected multiplex mode.
