ON Semiconductor AR0331 Series Operating and maintenance instructions

©Semiconductor Components Industries, LLC, 2011
March, 2017 −Rev. 14
1Publication Order Number:
AR0331/D
AR0331
AR0331 1/3‐Inch 3.1 Mp/Full
HD Digital Image Sensor
General Description
The ON Semiconductor AR0331 is a 1/3-inch CMOS digital image
sensor with an active-pixel array of 2048 (H) x 1536 (V). It captures
images in either linear or high dynamic range modes, with a
rolling-shutter readout. It includes sophisticated camera functions
such as in-pixel binning, windowing and both video and single frame
modes. It is designed for both low light and high dynamic range scene
performance. It is programmable through a simple two-wire serial
interface. The AR0331 produces extraordinarily clear, sharp digital
pictures, and its ability to capture both continuous video and single
frames makes it the perfect choice for a wide range of applications,
including surveillance and HD video.
The ON Semiconductor AR0331 can be operated in its default mode
or programmed for frame size, exposure, gain, and other parameters.
The default mode output is a 1080p-resolution image at 60 frames per
second (fps). In linear mode, it outputs 12-bit or 10-bit A-Law
compressed raw data, using either the parallel or serial (HiSPi) output
ports. In high dynamic range mode, it outputs 12-bit compressed data
using parallel output. In HiSPi mode, 12- or 14-bit compressed, or
16-bit linearized data may be output. The device may be operated in
video (master) mode or in single frame trigger mode.
FRAME_VALID and LINE_VALID signals are output on dedicated
pins, along with a synchronized pixel clock in parallel mode.
The AR0331 includes additional features to allow application-
specific tuning: windowing and offset, auto black level correction, and
on-board temperature sensor. Optional register information and
histogram statistic information can be embedded in the first and last 2
lines of the image frame.
The sensor is designed to operate in a wide temperature range
(–30°C to +85°C).
Features
•Superior Low-light Performance
•Latest 2.2 μm Pixel with ON Semiconductor A-Pix™Technology
•Full HD Support at 1080 P 60 fps for Superior Video Performance
•Linear or High Dynamic Range Capture
•3.1 M (4:3) and 1080 P Full HD (16:9) Images
•Optional Adaptive Local Tone Mapping (ALTM)
•Interleaved T1/T2 Output
•Support for External Mechanical Shutter
•Support for External LED or Xenon Flash
•Slow-motion Video (VGA 120 fps)
•On-chip Phase-locked Loop (PLL) Oscillator
•Integrated Position-based Color and Lens Shading Correction
•Slave Mode for Precise Frame-rate Control
•Stereo/3D Camera Support
•Statistics Engine
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See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
ILCC48 10x10
CASE 847AG
•Data Interfaces: Four-lane Serial High-speed
Pixel Interface (HiSPi) Differential
Signaling (SLVS and HiVCM), or Parallel
•Auto Black Level Calibration
•High-speed Context Switching
•Temperature Sensor
Applications
•Video Surveillance
•Stereo Vision
•Smart Vision
•Automation
•Machine Vision
•1080p60 Video Applications
•High Dynamic Range Imaging
IBGA52 9x9
CASE 503AA

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Table 1. KEY PARAMETERS
Parameter Typical Value
Optical Format 1/3-inch (5.8 mm)
Note: Sensor optical format will also work with lenses designed for
1/3.2” format.
Active Pixels 2048 (H) x 1536 (V) (4:3, mode)
Pixel Size 2.2 μm x 2.2 μm
Color Filter Array RGB Bayer
Shutter Type Electronic rolling shutter and GRR
Input Clock Range 6 – 48 MHz
Output Clock Maximum 148.5 Mp/s (4-lane HiSPi)
74.25 Mp/s (Parallel)
Output Serial HiSPi 10-, 12-, 14-, or 16-bit
Parallel 10-, 12-bit
Frame Rate Full Resolution 30 fps
1080p 60 fps
Responsivity 1.9 V/lux-sec
SNRMAX 39 dB
Max Dynamic Range Up to 100 dB
Supply Voltage I/O 1.8 or 2.8 V
Digital 1.8 V
Analog 2.8 V
HiSPi 0.3 V−0.6 V, 1.7 V−1.9 V
Power Consumption (Typical) <780 mW
Operating Temperature (Ambient) –30°C to +85°C
Package Options 10 x 10 mm 48 pin iLCC
9.5 x 9.5 mm 63-pin iBGA
ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number Product Description Orderable Product Attribute Description
AR0331SRSC00SHCA0-DRBR 48-pin iLCC HiSPi, 0°CRA Dry Pack without Protective Film, Double Side BBAR Glass
AR0331SRSC00SHCAD3-GEVK 48-pin iLCC HiSPi, 0°CRA Demo Kit 3
AR0331SRSC00SHCAD-GEVK 48-pin iLCC HiSPi, 0°CRA Demo Kit
AR0331SRSC00SHCAH-GEVB 48-pin iLCC HiSPi, 0°CRA Demo Board
AR0331SRSC00SUCA0-DPBR 48-pin iLCC Parallel, 0°CRA Dry Pack with Protective Film, Double Side BBAR Glass
AR0331SRSC00SUCA0-DRBR 48-pin iLCC Parallel, 0°CRA Dry Pack without Protective Film, Double Side BBAR Glass
AR0331SRSC00SUCAD3-GEVK 48-pin iLCC Parallel, 0°CRA Demo Kit 3
AR0331SRSC00SUCAD-GEVK 48-pin iLCC Parallel, 0°CRA Demo Kit
AR0331SRSC00SUCAH-GEVB 48-pin iLCC Parallel, 0°CRA Demo Board
AR0331SRSC00XUEAD3-GEVK 63-pin iBGA Demo Kit 3
AR0331SRSC00XUEAD-GEVK 63-pin iBGA Demo Kit
AR0331SRSC00XUEAH-GEVB 63-pin iBGA Demo Board
AR0331SRSC00XUEE0−BY−DRBR 63-pin iBGA, 0°CRA Dry Pack without Protective Film, Double Side BBAR Glass
AR0331SRSC00XUEE0-DPBR 63-pin iBGA, 0°CRA Dry Pack with Protective Film, Double Side BBAR Glass
AR0331SRSC00XUEE0-DRBR 63-pin iBGA, 0°CRA Dry Pack without Protective Film, Double Side BBAR Glass
AR0331SRSC00XUEE0-DRBR1 63-pin iBGA, 0°CRA Dry Pack without Protective Film, Double Side BBAR Glass

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FUNCTIONAL OVERVIEW
The AR0331 is a progressive-scan sensor that generates
a stream of pixel data at a constant frame rate. It uses an
on-chip, phase-locked loop (PLL) that can be optionally
enabled to generate all internal clocks from a single master
input clock running between 6 and 48 MHz. The maximum
output pixel rate is 148.5 Mp/s, corresponding to a clock rate
of 74.25 MHz. Figure 1 shows a block diagram of the sensor.
Figure 1. Block Diagram
Row noise correction
Black level correction
Adaptive CD filter
Motion correction and
Blue Halo filter
HDR linearization
(ME or DLO)
Pixel defect correction
Smooting filter
Digital gain and
pedestal
12
12
16
Companding
16, 14, or 12 bits
Parallel HiSPi
12 bits
( HDR and Linear),
12 or 10 bits Linear
Test pattern generator
ADC data
User interaction with the sensor is through the two-wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 3.1 Mp Active-pixel Sensor array. The timing and
control circuitry sequences through the rows of the array,
resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the data from the
columns is sequenced through an analog signal chain
(providing offset correction and gain), and then through an
analog-to-digital converter (ADC). The output from the
ADC is a 12-bit value for each pixel in the array. The ADC
output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain). The sensor also offers a high dynamic range
mode of operation where multiple images are combined
on-chip to produce a single image at 16-bit per pixel value.
A compression mode is further offered to allow the 16-bit
pixel value to be transmitted to the host system as a 12-bit
value with close to zero loss in image quality.

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Figure 2. Typical Configuration: Serial Four-Lane HiSPi Interface
VAA_PIX
Master clock
(6–48 MHz)
DGND
Digital
ground
Analog
ground
1.5 kW2
1.5 kW2
Notes: 1. All power supplies should be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.
3. The parallel interface output pads can be left unconnected if the serial output interface is used.
4. ON Semiconductor recommends that 0.1 μF and 10 μF decoupling capacitors for each power supply
are mounted as close as possible to the pad. Actual values and results may vary depending on layout and design
considerations. Refer to the AR0331 demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling
with the digital power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
EXTCLK
From
Controller
VDD_IO VDD
VDD_SLVS
VDD_PLL VAA
To
Controller
Digital I/0
Power1
Digital
Core
Power1
HiSPi
Power1
PLL
Power1
Analog
Power1
Analog
Power1
VDD_IO VDD VDD_SLVS VDD_PLL VAA
AGND
SLVSC_N
SLVSC_P
SLVS0_P
SLVS0_N
SLVS1_P
SLVS1_N
SLVS2_P
SLVS2_N
SLVS3_P
SLVS3_N
SHUTTER
FLASH
SDATA
SCLK
RESET_BAR
TEST
TRIGGER
OE_BAR
SADDR
VAA_PIX

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Figure 3. Typical Configuration: Parallel Pixel Data Interface
Notes:
Master clock
(6–48 MHz)
SDATA
SCLK
RESET_BAR
TEST
FLASH
FRAME_VALID
SHUTTER
DOUT [11:0]
EXTCLK
DGND
Digital
ground
Analog
ground
To
Controller
LINE_VALID
PIXCLK
1.5kΩ2
1.5kΩ2
VAA_PIX
VDD_IO VDD VDD_PLL VAA
VDD_IO VDD VDD_PLL VAA
Digital I/0
Power1
Digital
Core
Power1
PLL
Power1
Analog
Power1
Analog
Power1
1. All power supplies should be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kΩ, but a greater value may be used for slower two-wire speed.
3. The serial interface output pads and VDDSLVS can be left unconnected if the parallel output interface is used.
4. ON Semiconductor recommends that 0.1 μF and 10 μF decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations. Refer
to the AR0331 demo headboard schematics for circuit recommendations.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage currents.
7. The EXTCLK input is limited to 6−48 MHz.
SADDR
OE_BAR
TRIGGER
AGND
From
Controller
VAA_PIX

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Figure 4. 48 iLCC Package, Parallel Output
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
VDD_IO
PIXCLK
VDD
SCLK
SDATA
RESET_BAR
VDD_IO
NC
NC
VAA
AGND
VAA_PIX
Reserved
NC
VAA_PIX
VAA
AGND
VAA
Reserved
VDD
NC NC NC
OE_BAR
SADDR
TEST
FLASH
TRIGGER
FRAME_VALID
LINE_VALID
DGND
EXTCLK
VDD_PLL
DOUT6
DGND
DGND
DOUT5 DOUT4 DOUT3 DOUT2 DOUT1 DOUT0
NC
7
8
9
10
11
12
13
14
15
16
17
18
42
41
40
39
38
37
36
35
34
33
32
31
19 20 21 22 23 24 25 26 27 28 29 30
6 5 4 3 2 1 48 47 46 45 44 43
Table 3. PIN DESCRIPTION
Pin
Number Name Type Description
1 DOUT4 Output Parallel Pixel Data Output
2 DOUT5 Output Parallel Pixel Data Output
3 DOUT6 Output Parallel Pixel Data Output
4 VDD_PLL Power PLL Power
5 EXTCLK Input External Input Clock
6 DGND Power Digital Ground
7 DOUT7 Output Parallel Pixel Data Output
8 DOUT8 Output Parallel Pixel Data Output
9 DOUT9 Output Parallel Pixel Data Output
10 DOUT10 Output Parallel Pixel Data Output

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Table 3. PIN DESCRIPTION (continued)
Pin
Number DescriptionTypeName
11 DOUT11 Output Parallel Pixel Data Output (MSB)
12 VDD_IO Power I/O Supply Power
13 PIXCLK Output Pixel Clock Out. DOUT is Valid on Rising Edge of this Clock
14 VDD Power Digital Power
15 SCLK Input Two-wire Serial Clock Input
16 SDATA I/O Two-wire Serial Data I/O
17 RESET_BAR Input Asynchronous Reset (Active LOW). All Settings are Restored to Factory Default
18 VDD_IO Power I/O Supply Power
19 VDD Power Digital Power
20 NC
21 NC
22 NC
23 OE_BAR Input Output Enable (Active LOW)
24 SADDR Input Two-wire Serial Address Select. 0: 0x20. 1: 0x30
25 TEST Input Manufacturing Test Enable Pin (Connect to DGND)
26 FLASH Output Flash Output Control
27 TRIGGER Input Receives Slave Mode VD Signal for Frame Rate Synchronization and Trigger to
Start a GRR Frame
28 FRAME_VALID Output Asserted when DOUT Frame Data is Valid
29 LINE_VALID Output Asserted when DOUT Line Data is Valid.
30 DGND Power Digital Ground
31 Reserved
32 SHUTTER Output Control for External Mechanical Shutter. Can be Left Floating if not Used
33 Reserved
34 VAA Power Analog Power
35 AGND Power Analog Ground
36 VAA Power Analog Power
37 VAA_PIX Power Pixel Power
38 VAA_PIX Power Pixel Power
39 AGND Power Analog Ground
40 VAA Power Analog Power
41 NC
42 NC
43 NC
44 DGND Power Digital Ground
45 DOUT0 Output Parallel Pixel Data Output (LSB)
46 DOUT1 Output Parallel Pixel Data Output
47 DOUT2 Output Parallel Pixel Data Output
48 DOUT3 Output Parallel Pixel Data Output

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Figure 5. 48 iLCC Package, HiSPi Output
DGND
VDD_IO
SCLK
SDATA
RESET_BAR
NC
VAA
VAA_PIX
Reserved
VAA_PIX
VAA
AGND
VDD
NC
OE_BAR
FLASH
TRIGGER
VDD_PLL
SLVS0_N SLVS1_N
DGND
NC
7
8
9
10
11
12
13
14
15
16
17
18
42
41
40
39
38
37
36
35
34
33
32
31
19 20 21 22 23 24 25 26 27 28 29 30
6 5 4 3 2 1 48 47 46 45 44 43
SLVS0_P SLVS1_P
SLVSC_N
SLVSC_P
SLVS2_N
SLVS2_P
SLVS3_N
SLVS3_P
DGND
VDD_IO
SADDR
NC
DGND
Reserved
TEST
VDD
EXTCLK
VDD
DGND
VDD_IO
VDD_SLVS AGND
NC
VAA
NC
SHUTTER
Table 4. PIN DESCRIPTION, 48 ILCC
Pin Number Name Type Description
1 SLVSC_N Output HiSPi Serial DDR Clock Differential N
2 SLVS1_P Output HiSPi Serial Data, Lane 1, Differential P
3 SLVS1_N Output HiSPi Serial Data, Lane 1, Differential N
4 SLVS0_P Output HiSPi Serial Data, Lane 0, Differential P
5 SLVS0_N Output HiSPi Serial Data, Lane 0, Differential N
6 NC
7 VDD_SLVS Power 0.3 V−0.6 V or 1.7 V−1.9 V Port to HiSPi Output Driver. Set the High_VCM
(R0x306E[9]) Bit to 1 when Configuring VDD_SLVS to 1.7–1.9 V
8 VDD_IO Power I/O Supply Power
9 DGND Power Digital Ground
10 VDD Power Digital Power

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Table 4. PIN DESCRIPTION, 48 ILCC (continued)
Pin Number DescriptionTypeName
11 EXTCLK Input External Input Clock
12 VDD Power Digital Power
13 DGND Digital Ground
14 VDD_IO Power I/O Supply Power
15 SDATA I/O Two-wire Serial Data I/O
16 SCLK Input Two-wire Serial Clock Input
17 TEST Manufacturing Test Enable Pin (Connect to DGND)
18 RESET_BAR Input Asynchronous Reset (Active LOW). All Settings are Restored to Factory Default
19 VDD Power Digital Power
20 DGND Power Digital Ground
21 VDD_IO Power I/O Supply Power
22 NC
23 SADDR Input Two-wire Serial Address Select. 0: 0x20. 1: 0x30
24 NC
25 OE_BAR Output Enable (active LOW)
26 TRIGGER Input Receives Slave Mode VD Signal for Frame Rate Synchronization and Trigger to
Start a GRR Frame
27 FLASH Output Flash Output Control
28 DGND Power
29 VDD_PLL Power PLL Power
30 Reserved
31 AGND Power Analog Ground
32 VAA Power Analog Power
33 Reserved
34 SHUTTER Output Control for External Mechanical Shutter. Can be Left Floating if not Used
35 VAA_PIX Power Pixel Power
36 VAA_PIX Power Pixel Power
37 NC
38 VAA Power Analog Power
39 NC
40 NC
41 VAA Power Analog Power
42 AGND Power Analog Ground
43 DGND Power Digital Ground
44 SLVS3_P Output HiSPi Serial Data, Lane 3, Differential P
45 SLVS3_N Output HiSPi Serial Data, Lane 3, Differential N
46 SLVS2_P Output HiSPi Serial Data, Lane 2, Differential P
47 SLVS2_N Output HiSPi Serial Data, Lane 2, Differential N
48 SLVSC_P Output HiSPi Serial DDR Clock Differential P

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Figure 6. 9.5 x 9.5 mm 63−Ball IBGA Package
A
B
C
D
E
F
G
H
Top View
(Ball Down)
SLVS0_N SLVS0_P SLVS1_N SLVS1_P VDD NC
VDD_PLL SLVS_CN SLVSC_P SLVS2_N SLVS2_P VDD VAA VAA
EXTCLK VDD_
SLVS SLVS3_N SLVS3_P DGND VDD AGND
SADDR SCLK SDATA DGND DGND VDD VAA_PIX VAA_PIX
LINE_
VALID
FRAME_
VALID
PIXCLK FLASH DGND VDD_IO NC
DOUT8DOUT9DOUT10 DOUT11 DGND VDD_IO TEST
DOUT4DOUT5DOUT6DOUT7DGND VDD_IO TRIGGER OE_BAR
DOUT0DOUT1DOUT2DOUT3DGND VDD_IO VDD_IO RESET_
BAR
12 3 567 84
VDD
AGND
SHUTTER
Reserved
(NC)
Table 5. PIN DESCRIPTIONS, 9.5 x 9.5 mm, 63-BALL IBGA
Name iBGA Pin Type Description
SLVS0_N A2 Output HiSPi Serial Data, Lane 0, Differential N
SLVS0_P A3 Output HiSPi Serial Data, Lane 0, Differential P
SLVS1_N A4 Output HiSPi Serial Data, Lane 1, Differential N
SLVS1_P A5 Output HiSPi Serial Data, Lane 1, Differential P
VDD_PLL B1 Power PLL power.
SLVSC_N B2 Output HiSPi Serial DDR Clock Differential N
SLVSC_P B3 Output HiSPi Serial DDR Clock Differential P
SLVS2_N B4 Output HiSPi Serial Data, Lane 2, Differential N
SLVS2_P B5 Output HiSPi Serial Data, Lane 2, Differential P
VAA B7, B8 Power Analog Power
EXTCLK C1 Input External Input Clock.
VDD_SLVS C2 Power 0.3 V−0.6 V or 1.7 V−1.9 V port to HiSPi Output Driver. Set the
High_VCM (R0x306E[9]) bit to 1 when configuring VDD_SLVS to
1.7–1.9 V
SLVS3_N C3 Output HiSPi Serial Data, Lane 3, Differential N
SLVS3_P C4 Output HiSPi Serial Data, Lane 3, Differential P
DGND C5, D4, D5, E5,
F5, G5, H5
Power Digital Ground

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Table 5. PIN DESCRIPTIONS, 9.5 x 9.5 mm, 63-BALL IBGA (continued)
Name DescriptionTypeiBGA Pin
VDD A6, A7, B6, C6, D6 Power Digital Power
AGND C7, C8 Power Analog Ground
SADDR D1 Input Two-wire Serial Address Select. 0: 0x20. 1: 0x30
SCLK D2 Input Two-wire Serial Clock Input
SDATA D3 I/O Two-Wire Serial Data I/O
VAA_PIX D7, D8 Power Pixel Power
LINE_VALID E1 Output Asserted when DOUT Line Data is Valid
FRAME_VALID E2 Output Asserted when DOUT Frame Data is Valid.
PIXCLK E3 Output Pixel Clock Out. DOUT is Valid on Rising Edge of this Clock.
VDD_IO E6, F6, G6, H6, H7 Power I/O Supply Power
DOUT8 F1 Output Parallel Pixel Data Output
DOUT9 F2 Output Parallel Pixel Data Output
DOUT10 F3 Output Parallel Pixel Data Output
DOUT11 F4 Output Parallel Pixel Data Output (MSB)
TEST F7 Input. Manufacturing Test Enable Pin (Connect to DGND)
DOUT4 G1 Output Parallel Pixel Data Output
DOUT5 G2 Output Parallel Pixel Data Output
DOUT6 G3 Output Parallel Pixel Data Output
DOUT7 G4 Output Parallel Pixel Data Output
TRIGGER G7 Input Exposure Synchronization Input
OE_BAR G8 Input Output Enable (Active LOW)
DOUT0 H1 Output Parallel Pixel Data Output (LSB)
DOUT1 H2 Output Parallel Pixel Data Output
DOUT2 H3 Output Parallel Pixel Data Output
DOUT3 H4 Output Parallel Pixel Data Output
RESET_BAR H8 Input Asynchronous reset (active LOW). All settings are restored to factory
default
SHUTTER E8 Output Control for external mechanical shutter. Can be left floating if not used
FLASH E4 Output Flash Control Output
NC A8, E7
Reserved F8

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PIXEL DATA FORMAT
Pixel Array Structure
While the sensor’s format is 2048 x 1536, additional
active columns and active rows are included for use when
horizontal or vertical mirrored readout is enabled, to allow
readout to start on the same pixel. The pixel adjustment is
always performed for monochrome or color versions. The
active area is surrounded with optically transparent dummy
pixels to improve image uniformity within the active area.
Not all dummy pixels or barrier pixels can be read out.
Figure 7. Pixel Array Description
16 barrier + 4 border pixels
Light dummy Active pixel
pixel
2064
18 barrier + 4 border pixels
2 barrier + 4 border pixels
1578
2 barrier + 4 border pixels
20521 x 1536
4.51mm x 3.38 mm
1. Maximum of 2048 columns is supported. Additional columns included for mirroring operations.
Figure 8. Pixel Color Pattern Detail (Top Right Corner)
Active Pixel (0,0)
Array Pixel (0, 0)
RowReadout Direction
G
B
G
B
G
B
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
R
G
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
G
B
Column Readout Direction

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Default Readout Order
By convention, the sensor core pixel array is shown with
pixel (0,0) in the top right corner (see Figure 8). This reflects
the actual layout of the array on the die. Also, the first pixel
data read out of the sensor in default condition is that of pixel
(0, 0).
When the sensor is imaging, the active surface of the
sensor faces the scene as shown in Figure 9. When the image
is read out of the sensor, it is read one row at a time, with the
rows and columns sequenced as shown in Figure 9.
Figure 9. Imaging a Scene
Lens
Pixel (0,0)
Row
Readout
Order
Column Readout Order
Scene
Sensor (rear view)

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PIXEL OUTPUT INTERFACES
Parallel Interface
The parallel pixel data interface uses these output-only
signals:
•FRAME_VALID
•LINE_VALID
•PIXCLK
•DOUT[11:0]
The parallel pixel data interface is disabled by default at
power up and after reset. It can be enabled by programming
R0x301A. Table 7 shows the recommended settings.
When the parallel pixel data interface is in use, the serial
data output signals can be left unconnected. Set
reset_register [bit 12 (R0x301A[12] = 1)] to disable the
serializer while in parallel output mode.
Output Enable Control
When the parallel pixel data interface is enabled, its
signals can be switched asynchronously between the driven
and High-Z under pin or register control, as shown in
Table 6.
Table 6. OUTPUT ENABLE CONTROL
OE_BAR Pin Drive Pins R0x301A[6] Description
1 0 Interface High-Z
X 1 Interface Driven
0 X Interface Driven
Configuration of the Pixel Data Interface
Fields in R0x301A are used to configure the operation of
the pixel data interface. The supported combinations are
shown in Table 7.
Table 7. CONFIGURATION OF THE PIXEL DATA INTERFACE
Serializer Disable
R0x301 A[12]
Parallel Enable
R0x301 A[7] Description
0 0 Power up default
Serial pixel data interface and its clocks are enabled. Transitions to soft standby
are synchronized to the end of frames on the serial pixel data interface
1 1 Parallel pixel data interface, sensor core data output. Serial pixel data interface
and its clocks disabled to save power. Transitions to soft standby are
synchronized to the end of frames in the parallel pixel data interface
High Speed Serial Pixel Data Interface
The High Speed Serial Pixel (HiSPi) interface uses four
data lanes and one clock as output.
•SLVSC_P
•SLVSC_N
•SLVS0_P
•SLVS0_N
•SLVS1_P
•SLVS1_N
•SLVS2_P
•SLVS2_N
•SLVS3_P
•SLVS3_N
The HiSPi interface supports three protocols,
Streaming-S, Streaming-SP, and Packetized SP. The
streaming protocols conform to a standard video application
where each line of active or intra-frame blanking provided
by the sensor is transmitted at the same length. The
Packetized SP protocol will transmit only the active data
ignoring line-to-line and frame-to-frame blanking data.
These protocols are further described in the High-Speed
Serial Pixel (HiSPi) Interface Protocol Specification
V1.50.00.
The HiSPi interface building block is a unidirectional
differential serial interface with four data and one double
data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple
lanes. Figure 10 shows the configuration between the HiSPi
transmitter and the receiver.
The HiSPi interface building block is a unidirectional
differential serial interface with four data and one double
data rate (DDR) clock lanes. One clock for every four serial
data lanes is provided for phase alignment across multiple
lanes. Figure 10 shows the configuration between the HiSPi
transmitter and the receiver.

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Figure 10. HiSPi Transmitter and Receiver Interface Block Diagram
A camera containing
the HiSPi transmitter
A host (DSP) containing
the HiSPi receiver
Dp0
Dn0
Dp1
Dn1
Dp2
Dn2
Dp3
Dn3
Cp0
Cn0
Tx
PHY0
Rx
PHY0
Dp0
Dn0
Dp1
Dn1
Dp2
Dn2
Dp3
Dn3
Cp0
Cn0
HiSPi Physical Layer
The HiSPi physical layer is partitioned into blocks of four
data lanes and an associated clock lane. Any reference to the
PHY in the remainder of this document is referring to this
minimum building block.
The PHY will serialize 10-, 12-, 14-, or 16-bit data words
and transmit each bit of data centered on a rising edge of the
clock, the second on the falling edge of the clock. Figure 11
shows bit transmission. In this example, the word is
transmitted in order of MSB to LSB. The receiver latches
data at the rising and falling edge of the clock.
Figure 11. Timing Diagram
cp
dn
…
…
MSB LSB
TxPost
dp
cn
1 UI
TxPre
DLL Timing Adjustment
The specification includes a DLL to compensate for
differences in group delay for each data lane. The DLL is
connected to the clock lane and each data lane, which acts as
a control master for the output delay buffers. Once the DLL
has gained phase lock, each lane can be delayed in 1/8 unit
interval (UI) steps. This additional delay allows the user to
increase the setup or hold time at the receiver circuits and
can be used to compensate for skew introduced in PCB
design.
Delay compensation may be set for clock and/or data lines
in the hispi_timing register R0x31C0. If the DLL timing
adjustment is not required, the data and clock lane delay
settings should be set to a default code of 0x000 to reduce
jitter, skew, and power dissipation.
Figure 12. Block Diagram of DLL Timing Adjustment
delay delay
del 1[2: 0]
delay delay
del 3[2: 0]
delay
del 2[2: 0]
data _lane 0 data _lane 1 clock_lane0
delclock[2:0]
data_lane2 data_lane3
DATA0_DEL[2:0]

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Figure 13. Delaying the Clock with Respect to Data
1 UI
cp (CLOCK_DEL = 000)
dataN (DATAN_DEL = 000)
cp (CLOCK_DEL = 001)
cp (CLOCK_DEL = 010)
cp (CLOCK_DEL = 011)
cp (CLOCK_DEL = 100)
cp (CLOCK_DEL = 101)
cp (CLOCK_DEL = 110)
cp (CLOCK_DEL = 111)
Increasing CLOCK_DEL[2:0] Increases Clock Delay
Figure 14. Delaying Data with Respect to the Clock
1 UI
tDLLSTEP
cp (CLOCK_DEL = 000)
dataN (DATAN_DEL = 000)
dataN (DATAN_DEL = 001)
dataN (DATAN_DEL = 010)
dataN (DATAN_DEL = 011)
dataN (DATAN_DEL = 100)
dataN (DATAN_DEL = 101)
dataN (DATAN_DEL = 110)
dataN (DATAN_DEL = 111)
Increasing DATAN_DEL[2:0] Increases Data Delay
HiSPi Protocol Layer
The HiSPi protocol is described the HiSPi Protocol
Specification document.
Serial Configuration
The serial format should be configured using R0x31AC.
Refer to the AR0331 Register Reference document for more
detail regarding this register.
The serial_format register (R0x31AE) controls which
serial format is in use when the serial interface is enabled
(reset_register[12] = 0). The following serial formats are
supported:
•0x0304 −Sensor supports quad-lane HiSPi operation
•0x0302 −Sensor supports dual-lane HiSPi operation
•0x0301 −Sensor supports single-lane HiSPi operation

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PIXEL SENSITIVITY
Figure 15. Integration Control in ERS Readout
Row Reset
(Start of Integration)
Row Readout
Row Integration
(TINTEGRATION)
A pixel’s integration time is defined by the number of
clock periods between a row’s reset and read operation. Both
the read followed by the reset operations occur within a row
period (TROW) where the read and reset may be applied to
different rows. The read and reset operations will be applied
to the rows of the pixel array in a consecutive order.
The coarse integration time is defined by the number of
row periods (TROW) between a row’s reset and the row read.
The row period is defined as the time between row read
operations (see Sensor Frame Rate).
TCOARSE +TROW coarse_integration_time (eq. 1)
Figure 16. Example of 8.33 ms Integration in 16.6 ms Frame
Vertical Blanking
Read
Reset
Vertical Blanking
Horizontal Blanking
TCOARSE = coarse_integration_time x TROW
8.33 ms = 563 rows x 22.2 μs/row
TFRAME = frame_length_lines x TROW
16.6 ms = 750 rows x 22.22 μs/row

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Figure 17. The Row Integration Time is Greater Than the Frame Readout Time
Vertical Blanking
Read
Shutter
Vertical Blanking
Horizontal Blanking
TCOARSE = coarse_integration_time x TROW TFRAME = frame_length_lines x TROW
20.7 ms = 1390 rows x 14.8 μs/row 16.6 ms = 1125rows x 14.8 μs/row
Horizontal Blanking
Image
Image
4.1 ms
Pointer
Pointer
Time
Extended Vertical Blanking
The minimum frame-time is defined by the number of row
periods per frame and the row period. The sensor frame-time
will increase if the coarse_integration_time is set to a value
equal to or greater than the frame_length_lines.
GAIN STAGES
The analog gain stages of the AR0331 sensor are shown
in Figure 18. The sensor analog gain stage consists of a
variable ADC reference. The sensor will apply the same
analog gain to each color channel. Digital gain can be
configured to separate levels for each color channel.
Figure 18. Gain Stages in AR0331 Sensor
ADC
Reference
Digital Gain
with Dithering
1x, 2x, 4x, and 8x
1x to 16x
(128 steps per 6dB)
The level of analog gain applied is controlled by the
coarse_gain register. The recommended analog gain settings
are listed in Table 8. A minimum analog gain of 1.23x is
recommended. Changes to these registers should be done
prior to streaming images.

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Table 8. RECOMMENDED SENSOR GAIN
coarse_gain(0x3060[5:4])/
coarse_gain_cb (0x3060[13:12])
fine_gain (0x3060[3:0])/
fine_gain_cb (0x3060[11:8]) ADC Gain
0 6 1.23
0 7 1.28
0 8 1.34
0 9 1.39
0 10 1.45
011 1.52
0 12 1.60
0 13 1.69
0 14 1.78
0 15 1.88
1 0 2.00
1 2 2.14
1 4 2.28
1 6 2.47
1 8 2.67
1 10 2.91
1 12 3.20
1 14 3.56
2 0 4
2 4 4.56
2 8 5.34
2 12 6.41
3 0 8
Each digital gain can be configured from a gain of 0 to
15.992. The digital gain supports 128 gain steps per 6dB of
gain. The format of each digital gain register is
“xxxx.yyyyyyy” where “xxxx” refers an integer gain of 1 to
15 and “yyyyyyy” is a fractional gain ranging from 0/128 to
127/128.
The sensor includes a digital dithering feature to reduce
quantization noise resulting from using digital gain. It can be
disabled by setting R0x30BA[5] to 0. The default value is 1.
PEDESTALS
There are two types of constant offset pedestals that may
be adjusted at the end of the datapath.
The data pedestal is a constant offset that is added to pixel
values at the end of the datapath. The default offset when
ALTM is disabled is 168 and is a 12-bit offset. This offset
matches the maximum range used by the corrections in the
digital readout path. The purpose of the data pedestal is to
convert negative values generated by the digital datapath
into positive output data. It is recommended that the data
pedestal be set to 16 when ALTM is enabled.
The data pedestal value can be changed from its default
value by adjusting register R0x301E.
The ALTM pedestal (R0x2450) is also located at the end
of the datapath. The ALTM pedestal default offset is 0.

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HIGH DYNAMIC RANGE MODE
By default, the sensor powers up in HDR Mode. The HDR
scheme used is multi-exposure HDR. This allows the sensor
to handle up to 100 dB of dynamic range. In HDR mode, the
sensor sequentially captures two exposures by maintaining
two separate read and reset pointers that are interleaved
within the rolling shutter readout. The intermediate pixel
values are stored in line buffers while waiting for the two
exposure values to be present. As soon as a pixel’s two
exposure values are available, they are combined to create
a linearized 16-bit value for each pixel’s response.
Depending on whether HiSPi or Parallel mode is selected,
the full 16 bit value may be output, it can be compressed to
12 bits using Adaptive Local Tone Mapping (ALTM), or
companded to 12 or 14 bits.
Adaptive Local Tone Mapping
Real- world scenes often have a very high dynamic range
(HDR) that far exceeds the electrical dynamic range of the
imager. Dynamic range is defined as the luminance ratio
between the brightest and the darkest objects in a scene.
Even though the AR0331 can capture full dynamic range
images, the images are still limited by the low dynamic
range of display devices. Today’s typical LCD monitor has
a contrast ratio around 1000:1 while it is not atypical for an
HDR image having a contrast ratio of around 250000:1.
Therefore, in order to reproduce HDR images on a low
dynamic range display device, the captured high dynamic
range must be compressed to the available range of the
display device. This is commonly called tone mapping. The
AR0331 has implemented an adaptive local tone mapping
(ALTM) feature to reproduce visually appealing images that
increase the local contrast and the visibility of the images.
When ALTM is enabled, the gamma in the backend ISP
should be set to 1 for proper display.
See the AR0331 Developer Guide for more information
on ALTM.
Companding
The 16-bit linearized HDR image may be compressed to
12 bits using on-chip companding. Figure 19 illustrates the
compression from 16- to 12-bits. Companding is enabled by
setting R0x31D0. Table 10 shows the knee points for the
different modes.
Figure 19. HDR Data Compression
500
1000
1500
2000
2500
3000
3500
4000
4500
0 10000 20000 30000 40000 50000 60000 70000
0
12-bit Code Output
16-bit Code Input