ON Semiconductor KAC-12040 User manual

©Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 5 1Publication Order Number:
KAC−12040/D
KAC-12040
4000 (H) x 3000 (V)
CMOS Image Sensor
Description
The KAC−12040 Image Sensor is a high-speed 12 megapixel
CMOS image sensor in a 4/3″optical format based on a 4.7 mm 5T
CMOS platform. The image sensor features very fast frame rate,
excellent NIR sensitivity, and flexible readout modes with multiple
regions of interest (ROI). The readout architecture enables use of 8, 4,
or 2 LVDS output banks for full resolution readout of 70 frames per
second.
Each LVDS output bank consists of up to 8 differential pairs
operating at 160 MHz DDR for a 320 Mbps data rate per pair.
The pixel architecture allows rolling shutter operation for motion
capture with optimized dynamic range or global shutter for precise
still image capture.
Table 1. GENERAL SPECIFICATIONS
Parameter Typical Value
Architecture 5T Global Shutter CMOS
Resolution 12 Megapixels
Aspect Ratio 4:3
Pixel Size 4.7 mm (H) ×4.7 mm (V)
Total Number of Pixels 4224 (H) ×3192 (V)
Number of Effective Pixels 4016 (H) ×3016 (V)
Number of Active Pixels 4000 (H) ×3000 (V)
Active Image Size 18.8 mm (H) ×14.1 mm (V)
23.5 mm (Diagonal), 4/3″Optical Format
Master Clock Input Speed 5 MHz to 50 MHZ
Maximum Pixel Clock Speed 160 MHz DDR LVDS, 320 Mbps
Number of LVDS Outputs 64 Differential Pairs
Number of Output Banks 8, 4, or 2
Frame Rate, 12 Mp 1−70 fps 10 bits
1−75 fps 8 bits
Charge Capacity 16,000 electrons
Quantum Efficiency
KAC−12040−CBA
KAC−12040−ABA 40%, 47%, 45% (470, 540, 620 nm)
53%, 15%, 10% (500, 850, 900 nm)
Read Noise
(at Maximum LVDS Clock) 3.7 e−rms, Rolling Shutter 25.5 e−rms, Global Shutter
Dynamic Range 73 dB, Rolling Shutter
56 dB, Global Shutter
Blooming Suppression > 10,000x
Image Lag 1.3 electron
Digital Core Supply 2.0 V
Analog Core Supply 1.8 V
Pixel Supply 2.8 V & 3.5 V
Power Consumption 1.5 W for 12 Mp @ 70 fps 10 bits
Package 267 Pin Ceramic Micro-PGA
Cover Glass AR Coated, 2-sides
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
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Figure 1. KAC−12040 CMOS Image Sensor
Features
•Global Shutter and Rolling Shutter
•Very Fast Frame Rate
•High NIR Sensitivity
•Multiple Regions of Interest
•Interspersed Video Streams
Applications
•Machine Vision
•Intelligent Transportation Systems
•Surveillance
See detailed ordering and shipping information on page 2 o
f
this data sheet.
ORDERING INFORMATION

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The image sensor has a pre-configured QFHD (4 ×1080p,
16:9) video mode, fully programmable, multiple ROI for
windowing, programmable sub-sampling, and reverse
readout (flip and mirror). The two ADCs can be configured
for 8-bit, 10-bit, 12-bit or 14-bit conversion and output.
Additional features include interspersed video streams
(dual-video), on-chip responsivity calibration, black
clamping, overflow pixel for blooming reduction, black-sun
correction (anti-eclipse), column and row noise correction,
and integrated timing generation with SPI control, 4:1 and
9:1 averaging decimation modes.
ORDERING INFORMATION
Table 2. ORDERING INFORMATION − KAC−12040 IMAGE SENSOR
Part Number Description Marking Code
KAC−12040−ABA−JD−BA Monochrome, Micro-PGA Package, Sealed Clear Cover Glass with AR
Coating (Both Sides), Standard Grade. KAC−12040−ABA
Serial Number
KAC−12040−ABA−JD−AE Monochrome, Micro-PGA Package, Sealed Clear Cover Glass with AR
Coating (Both Sides), Engineering Grade.
KAC−12040−CBA−JD−BA Bayer (RGB) Color Filter Pattern, Micro-PGA Package, Sealed Clear Cover
Glass with AR Coating (Both Sides), Standard Grade. KAC−12040−CBA
Serial Number
KAC−12040−CBA−JD−AE Bayer (RGB) Color Filter Pattern, Micro-PGA Package, Sealed Clear Cover
Glass with AR Coating (Both Sides), Engineering Grade.
1. Engineering Grade samples might not meet final production testing limits, especially for cosmetic defects such as clusters, but also possibly
column and row artifacts. Overall performance is representative of final production parts.
Table 3. ORDERING INFORMATION − EVALUATION SUPPORT
Part Number Description
KAC−12040−CB−A−GEVK Evaluation Hardware for KAC−12040 Image Sensor (Color). Includes Image Sensor.
KAC−12040−AB−A−GEVK Evaluation Hardware for KAC−12040 Image Sensor (Monochrome). Includes Image Sensor.
LENS−MOUNT−KIT−C−GEVK Lens Mount Kit that Supports C, CS, and F Mount Lenses. Includes IR Cut-filter for Color Imaging.
See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention
used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at
www.onsemi.com.

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DEVICE DESCRIPTION
Architecture
Figure 2. Block Diagram
G
B
GR
4000 (H) y3000 (V)
4.7 mm Pixel
G
B
GR
G
B
GR
G
B
GR
LVDS Bank 2 LVDS Bank 4 LVDS Bank 6
Even Row ADC, Analog Gain, Black-Sun Correction
Clk2 Clk4 Clk6
2D0− 2D6
4D0− 4D6
6D0− 6D6
8
88
8
88
Odd Row ADC, Analog Gain, Black-Sun Correction
LVDS Bank 3 LVDS Bank 5 LVDS Bank 7
(0, 0)
Clk7 7D0− 7D6 Clk5 5D0− 5D6 Clk3 3D0− 3D6
LVDS Bank 0 LVDS Bank 1
Digital Gain/Offset, Noise Correction
Clk1
1D0− 1D6
Clk0
0D0− 0D6
Timing Control, Sub-Sampling/Averaging
8
104
8
104
3.5 VA
3.3 VD
2.8 VA
2.0 VD
1.8 VA
Chip Clock (2 Pins)
TRIGGER
RESETN
CSN
SCLK
MOSI
MISO
Serial
Peripheral
Interface
(SPI)
ADC_Ref1
ADC_Ref2
VSS 0 V
4.02 kW±1%

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Physical Orientation
Figure 3. Package Pin Orientation − Top X-Ray View
LVDS Bank 2 LVDS Bank 4 LVDS Bank 6
LVDS Bank 3 LVDS Bank 5 LVDS Bank 7
LVDS Bank 0 LVDS Bank 1
A
B
C
D
E
AA
AB
AC
AD
AE
272625242322212019181716151413121110987654321
272625242322212019181716151413121110987654321
1. The center of the pixel array is aligned to the physical package center.
2. The region under the sensor die is clear of pins enabling the use of a heat sink.
3. Non-symmetric mounting holes provide orientation and mounting precision.
4. Non-symmetric pins prevent incorrect placement in PCB.
5. Letter “F” indicator shows default readout direction relative to package pin 1.
Notes:

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Table 4. PRIMARY PIN DESCRIPTION
Pin Name Type Description
AB09 RESETN DI Sensor Reset (0 V = Reset State)
E07 CLK_In1 DI Sensor Input Clk_In1 (45−50 MHz)
D08 CLK_In2 DI Sensor Input Clk_In2 (Connect to Clk1)
AB08 TRIGGER DI Trigger Input (Optional)
AA05 SCLK DI SPI Master Clock
AA08 MOSI DI SPI Master Output, Slave Input
AA07 MISO DO SPI Master Input, Slave Output
AA06 CSN DI SPI Chip Select (0 V = Selected)
AA14 ADC_Ref1 AO 4.02 kW±1% Resistor between Ref1 & Ref2
AA15 ADC_Ref2 AO 4.02 kW±1% Resistor between Ref1 & Ref2
AB07 MSO DO Mechanical Shutter Output Sync (Optional)
AB06 FLO DO Flash Output Sync (Optional)
E05 FEN DO Frame Enable Reference Output (Optional)
E06 LEN DO Line Enable Reference Output (Optional)
1. DI = Digital Input, DO = Digital Output, AO = Analog Output.
2. Tie unused DI pins to Ground, NC unused DO pins.
3. By default Clk_In2 should equal Clk_In1 and should be the same source clock.
4. The RESETN pin has a 62 kWinternal pull-up resistor, so if left floating the chip will not be in reset mode.
5. The TRIGGER pin has an internal 100 kWpull down resistor. If left floating (and at default polarity) then the sensor state will not be affected
by this pin (i.e. defaults to ‘not triggered’ mode if floated).
6. All of the DI and DO pins nominally operate at 0 V →2.0 V and are associated with the VDD_DIG power supply.
Table 5. POWER PIN DESCRIPTION
Name Voltage Pins Description
VDD_LVDS 3.3 V D C04, C05, C23, C24, D04, D24, E04, E24, AA04, AA24,
AB04, AB24, AC04, AC05 AC23, AC24 LVDS Output Supply
VDD_DIG 2.0 V D C18, C19, D18, D19, E18, AA18, AB18, AB19, AC18, AC19,
C20, C21, C22, D20, D21, D22, D23, E20, E21, E22, AA20,
AA21, AA22, AB20, AB21, AB22, AB23, AC20, AC21,
AC22, AB15, E08
Digital Core Supply
AVDD_HV 3.5 V A C11, D11, E11, AA11, AB11, AC11, C10, D10, E10, AA10,
AB10, AC10 Pixel Supply 1
Vref_P 2.8 V A C13, D13, E13, AA13, AB13, AC13 Pixel Supply 2
AVDD_LV 1.8 V A C17, D16, D17, E17, AA17, AB16, AB17, AC17 Analog Low Voltage Supply
Vpixel_low 0 V E09 Pixel Supply 3. Combine with VSS for
normal operation. Can be pulsed for
Extended Dynamic Range Operation.
VSS 0 V C12, C14, D12, D14, E12, AA12, AB12, AB14, AC12, AC14,
E15, D15, AA09, A02, A14, A26, B14, C03, C06, C25, D03,
D25, E03, E19, E23, E25, AA03, AA19, AA23, AA25, AB25,
AC03, AC06, AC25, AD14, AE02, AE14, AE26
Sensor Ground Reference
No Connect NA A01, AC09, E14, E16, C09, D09, D05, D06, D07, AA16,
AB05 Unused and test-only pins. These pins must be floated.

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Pin Name Description
E01 1DCLK+
E02 1DCLK−
D01 1DATA0+
D02 1DATA0−
C01 1DATA1+
C02 1DATA1−
B01 1DATA2+
B02 1DATA2−
A03 1DATA3+
B03 1DATA3−
A04 1DATA4+
B04 1DATA4−
A05 1DATA5+
B05 1DATA5−
A06 1DATA6+
B06 1DATA6−
Bank 1
LVDS Clock
Bank 1
LVDS Data
Pin Name Description
C07 3DCLK+
C08 3DCLK−
A07 3DATA0+
B07 3DATA0−
A08 3DATA1+
B08 3DATA1−
A09 3DATA2+
B09 3DATA2−
A10 3DATA3+
B10 3DATA3−
A11 3DATA4+
B11 3DATA4−
A12 3DATA5+
B12 3DATA5−
A13 3DATA6+
B13 3DATA6−
Bank 3
LVDS Clock
Bank 3
LVDS Data
Pin Name Description
C15 5DCLK+
C16 5DCLK−
A15 5DATA0+
B15 5DATA0−
A16 5DATA1+
B16 5DATA1−
A17 5DATA2+
B17 5DATA2−
A18 5DATA3+
B18 5DATA3−
A19 5DATA4+
B19 5DATA4−
A20 5DATA5+
B20 5DATA5−
A21 5DATA6+
B21 5DATA6−
Bank 5
LVDS Clock
Bank 5
LVDS Data
Pin Name Description
A22 7DCLK+
B22 7DCLK−
A23 7DATA0+
B23 7DATA0−
A24 7DATA1+
B24 7DATA1−
A25 7DATA2+
B25 7DATA2−
B27 7DATA3+
B26 7DATA3−
C27 7DATA4+
C26 7DATA4−
D27 7DATA5+
D26 7DATA5−
E27 7DATA6+
E26 7DATA6−
Bank 7
LVDS Clock
Bank 7
LVDS Data
Pin Name Description
AA01 0DCLK+
AA02 0DCLK−
AB01 0DATA0+
AB02 0DATA0−
AC01 0DATA1+
AC02 0DATA1−
AD01 0DATA2+
AD02 0DATA2−
AE03 0DATA3+
AD03 0DATA3−
AE04 0DATA4+
AD04 0DATA4−
AE05 0DATA5+
AD05 0DATA5−
AE06 0DATA6+
AD06 0DATA6−
Bank 0
LVDS Clock
Bank 0
LVDS Data
Pin Name Description
AC07 2DCLK+
AC08 2DCLK−
AE07 2DATA0+
AD07 2DATA0−
AE08 2DATA1+
AD08 2DATA1−
AE09 2DATA2+
AD09 2DATA2−
AE10 2DATA3+
AD10 2DATA3−
AE11 2DATA4+
AD11 2DATA4−
AE12 2DATA5+
AD12 2DATA5−
AE13 2DATA6+
AD13 2DATA6−
Bank 2
LVDS Clock
Bank 2
LVDS Data
Pin Name Description
AC15 4DCLK+
AC16 4DCLK−
AE15 4DATA0+
AD15 4DATA0−
AE16 4DATA1+
AD16 4DATA1−
AE17 4DATA2+
AD17 4DATA2−
AE18 4DATA3+
AD18 4DATA3−
AE19 4DATA4+
AD19 4DATA4−
AE20 4DATA5+
AD20 4DATA5−
AE21 4DATA6+
AD21 4DATA6−
Bank 4
LVDS Clock
Bank 4
LVDS Data
Pin Name Description
AE22 6DCLK+
AD22 6DCLK−
AE23 6DATA0+
AD23 6DATA0−
AE24 6DATA1+
AD24 6DATA1−
AE25 6DATA2+
AD25 6DATA2−
AD26 6DATA3+
AD27 6DATA3−
AC26 6DATA4+
AC27 6DATA4−
AB26 6DATA5+
AB27 6DATA5−
AA26 6DATA6+
AA27 6DATA6−
Bank 6
LVDS Clock
Bank 6
LVDS Data
1. All LVDS Data and Clock lines must be routed with 100 Wdifferential transmission line traces.
2. All the traces for a single LVDS Bank should be the same physical length to minimize skew between the clock and data lines.
3. In 2 Bank mode, only LVDS banks 0 and 1 are active.
4. In 4 Bank mode, only LVDS bank 0, 1, 2, and 3 are active.
5. Float the pins of unused LVDS Banks to conserve power.
6. Unused pins in active banks (due to ADC bit depth < 14) are automatically tri-stated to save power, but these can also be floated.
Table 6. LVDS PIN DESCRIPTION

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IMAGING PERFORMANCE
Table 7. TYPICAL OPERATIONAL CONDITIONS
(Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.)
Description Condition Notes
Light Source Continuous Red, Green and Blue LED Illumination 1
Temperature Measured Die Temperature: 40°C and 27°C
Integration Time 16.6 ms (1400d LL, Register 0201h)
Readout Mode Dual-Scan, Global Shutter, 320 MHz, PLL2
Clamps Column/Row Noise Corrections Active, Frame Black Level Clamp Active
ADC Bit Depth 10 bit
Analog Gain Unity Gain or Referred Back to Unit Gain
1. For monochrome sensor, only green LED used.
Table 8. KAC−12040−ABA CONFIGURATION (MONOCHROME)
Description Symbol Wavelength
(nm) Min. Nom. Max. Unit Sampling Plan
Temperature
Tested at
(5C) Test
Peak Quantum Efficiency
Green
NIR1
NIR2
QEMAX 550
850
900
−
−
−
53
15
10
−
−
−
% Design 27
Responsivity − 84 − ke*
Lux @sDesign 27 20
Responsivity − 7.0 − V
Lux @sDesign 27 21
Table 9. KAC−12040−CBA CONFIGURATION (BAYER RGB)
Description Symbol Wavelength
(nm) Min. Nom. Max. Unit Sampling Plan
Temperature
Tested at
(5C) Test
Peak Quantum Efficiency
Green
NIR1
NIR2
QEMAX 470
540
620
850
900
−
−
−
−
−
40
47
45
15
10
−
−
−
−
−
% Design 27
Responsivity Blue
Green
Red
−
−
−
17
35
38
−
−
−
ke*
Lux @sDesign 27 20
Responsivity Blue
Green
Red
−
−
−
1.4
2.9
3.2
−
−
−
V
Lux @sDesign 27 21

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Table 10. PERFORMANCE SPECIFICATIONS ALL CONFIGURATIONS
Description Symbol Min. Nom. Max. Unit Sampling
Plan
Temperature
Tested at
(5C) Test Notes
Photodiode Charge
Capacity PNe − 16 − ke−Die 27, 40 16
Read Noise ne−T −
−3.7 RS 25.5 GS − −e−rms Die 27 8 1
Total Pixelized Noise −
−4.5 RS 28.3 GS − −e−rms Die 27 19 1
Dynamic Range DR −
−73 RS 56 GS − −dB Die 27 1, 4
Column Noise CN−
−0.6 RS 3.0 GS − −e−rms Die 27 9 1, 6
Row Noise RN−
−1.0 RS 5.0 GS − −e−rms Die 27 10 1, 7
Dark Field Local
Non-Uniformity Floor DSNU_flr − −3.0 RS 21 GS − −e−rms Die 27, 40 11, 5
Bright Field Global
Photoresponse
Non-Uniformity
PRNU_1 − 1.5 − % rms Die 27, 40 2 2
Bright Field Global Peak to
Peak Photoresponse
Non-Uniformity
PRNU_2 − 6.5 − % pp Die 27, 40 3 2
Maximum Photoresponse
Non-Linearity NL − 6.3 − % Die 27, 40 11 3
Maximum Gain Difference
between Outputs DG− 0.3 − % Die 27, 40 12 8
Photodiode Dark Current IPD − 4.6 70 e/p/s Die 40 13 9
Storage Node Dark Current IVD − 1,200 5,000 e/p/s Die 40 14 5
Image Lag Lag − 1.3 10 −Design 27, 40 15
Black-Sun Anti-Blooming XAB −
−12 > 10,000 − −W/cm2
xllumSat Design 27 7 14
Parasitic Light Sensitivity PLS − 730 − − Design 27 6 10
Dual-Video WDR −
−140 RS 120 GS − −dB Design 27 1, 11, 12
Pulsed Pixel WDR
(GS Only) − 100 − dB Design 27 12, 13
1. RS = Rolling Shutter Operation Mode, GS = Global Shutter Operation Mode.
2. Measured per color, worst of all colors reported.
3. Value is over the range of 10% to 90% of photodiode saturation, Green response used.
4. Uses 20LOG (PNe / ne−T).
5. Photodiode dark current made negligible.
6. Column Noise Correction active.
7. Row Noise Correction active.
8. Measured at ~70% illumination.
9. Storage node dark current made negligible.
10.GSE (Global Shutter Efficiency) = 1 − 1 / PLS.
11.Min vs Max integration time at 30 fps.
12.WDR measures expanded exposure latitude from linear mode DR.
13.Min/Max responsivity in a 30 fps image.
14.Saturation Illumination referenced to a 3 line time integration.

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TYPICAL PERFORMANCE CURVES
Figure 4. Monochrome QE (with Microlens)
Figure 5. Bayer QE (with Microlens)

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Angular Quantum Efficiency
For the curves marked “Horizontal”, the incident light angle is varied along the wider array dimension.
For the curves marked “Vertical”, the incident light angle is varied along the shorter array dimension.
Figure 6. Monochrome Relative Angular QE (with Microlens)
Figure 7. Bayer Relative Angular QE (with Microlens)