ON Semiconductor AR0330CS User manual

©Semiconductor Components Industries, LLC, 2012
January, 2019 −Rev. 8
1Publication Order Number:
AR0330CS/D
AR0330CS
AR0330CS and AR0330SR
1/3-Inch CMOS Digital
Image Sensor
General Description
The AR0330CS can be operated in its default mode or programmed
for frame size, exposure, gain, and other parameters. The default mode
output is a 2304 x 1296 image at 30 frames per second (fps). The
sensor outputs 10−or 12−bit raw data, using either the parallel or serial
(MIPI) output ports.
The ON Semiconductor AR0330CS is a 1/3−inch CMOS digital
image sensor with an active−pixel array of 2304 (H) x1536 (V). It can
support 3.15 megapixel (2048H x 1536 V) digital still image capture
and a 1080p30 +20%EIS (2304H x 1296 V) digital video mode. It
incorporates sophisticated on−chip camera functions such as
windowing, mirroring, column and row subsampling modes, and
snapshot modes.
Table 1. KEY PARAMETERS
Parameter Typical Value
Optical Format 1/3−inch (6.0 mm)
Entire Array: 6.09 mm
Still Image: 5.63 mm (4:3)
HD Image: 5.82 mm (16:9)
Active Pixels 2304(H) x 1536(V): (Entire Array):
5.07 mm (H) x 3.38 mm (V)
2048(H) x 1536(V) (4:3, Still Mode)
2304(H) x 1296(V) (16:9, sHD Mode)
Pixel Size 2.2 mm x 2.2 mm
Color Filter Array RGB Bayer
Shutter Type ERS and GRR
Input Clock Range 6 – 27 MHz
Output Clock Maximum
(CLK_OP)
98 Mp/s (Parallel, MIPI)
Responsivity 2.0 V/lux−sec
Power Consumption 1080P30 MIPI Mode: 282 mW
1080P30 Parallel Mode: 252 mW
SNRMAX 39 dB
Dynamic Range 69.5 dB
Supply
Voltage
I/O/Digital 1.7–1.9 V (1.8 V Nominal) or
2.4–3.1 V (2.8 V Nominal)
Digital 1.7–1.9 V (1.8 V Nominal)
Analog 2.76–2.9 V
Operating Temperature
(junction) −TJ
–30°C to + 70°C
Package Options 6.28 mm x 6.65 mm CSP
11.43 mm x 11.43 mm PLCC
www.onsemi.com
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
PLCC48
11.43x11.43
CASE 776AM
Features (continued)
•2.2 mm Pixel with ON Semiconductor
A−Pix™technology
•Superior Low−light Performance
•3.5 Mp Active Array, 2.9 Mp (16:9) Video
3.4 Mp (3:2) and 3.15 Mp (4:3) Still Images
•Support for External Mechanical Shutter
•Support for External LED or Xenon Flash
•Data Interfaces: Two−lane Serial MIPI or
Parallel Interface
•On−chip phase−locked Loop (PLL)
Oscillator
•Integrated Position−based Color and Lens
Shading Correction
•Simple Two−wire Serial Interface
•Auto Black Level Calibration
•12−to−10 bit Output A−Law Compression
•Slave Mode for Precise Frame−rate Control
and for Synchronizing Two Sensors
Applications
•1080P30 High−definition Digital Video
Camcorder
•Web Cameras and Video Conferencing
Cameras
•Security
ODCSP64
6.278x6.648
CASE 570BH

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ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number Product Description Orderable Product Attribute Description
AR0330CS1C12SPKA0−CP 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, MIPI, CSP Tray, Protective Film
AR0330CS1C12SPKA0−CR 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, MIPI, CSP Tray, No Protective Film
AR0330CSSC12SPBA0−DR 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, PLCC Tray, No Protective Film
AR0330SR1C00SUKA0−CP 3.5 MP, 1/3−inch, 0 Deg CRA, Parallel, CSP Tray, Protective Film
AR0330SR1C00SUKA0−CR 3.5 MP, 1/3−inch, 0 Deg CRA, Parallel, CSP Tray, No Protective Film
AR0330CS1C12SPKAH3−GEVB 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, MIPI, CSP Evaluation board
FUNCTIONAL OVERVIEW
The AR0330CS is a progressive−scan sensor that
generates a stream of pixel data at a constant frame rate. It
uses an on−chip, phase−locked loop (PLL) that can generate
all internal clocks from a single master input clock running
between 6 and 27 MHz. The maximum CLK_OP is 98 Mp/s
using MIPI serial interface and 98 Mp/s using the parallel
interface.
and
Control
Timing
Figure 1. Block Diagram
Compression (optional)
12−bit
12−bit
12−bit 12−bit 8, 10, or
12−bit
Ma x 98 Mp/s
Parallel I/O:
PIXCLK, FV,
LV, DOUT [11:0]
MIPI I/O:
CLK P/N,
1. Two lane data paths
only 2. 98 Mp/sec
Digital Core
Row Noise Correction
Black Level Correction
Lens Shading Correction
Digital Gain
Data Pedestal
Test Pattern
Generator
Output Data−Path
Analog Core
Ext
Clock
Column
Amplifiers
Pixel Array
Row Drivers
PLL
Registers
Two−wire serial I/F
ADC
Max CLK_OP 98 Mp/s
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 3.5 Mp active−pixel sensor array. The timing and
control circuitry sequences through the rows of the array,
resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the signal from the
column is amplified in a column amplifier and then digitized
in an analog−to−digital converter (ADC). The output from
the ADC is a 12−bit value for each pixel in the array. The
ADC output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain).

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WORKING MODES
The AR0330CS sensor working modes are specified from
the following aspect ratios:
Table 3. AVAILABLE ASPECT RATIOS IN THE AR0330CS SENSOR
Aspect Ratio Sensor Array Usage
3:2 Still Format #1 2256(H) x 1504(V)
4:3 Still Format #2 2048 (H) x 1536 (V)
16:10 Still Format #3 2256 (H) x 1440 (V)
16:9 FHD Format 2304 (H) x 1296 (V)
The AR0330CS supports the following working modes.
To operate the sensor at full speed 98Mp/s the sensor must
use 2−Lane MIPI or parallel interface. The sensor will
operate at full−speed (98 Mp/s) when using the parallel
interface.
Table 4. AVAILABLE WORKING MODES IN THE AR0330CS SENSOR
Mode Aspect Ratio
Active
Readout
Window
Sensor Output
Resolution
FPS
(2 lane MIPI,
12 bit)
FPS (Parallel
Interface) Subsampling FOV
1080p + EIS 16:9 2304 x 1296 2304 x 1296 30 30 – 100%
3M Still 4:3 2048 x 1536 2048 x 1536 30 25 – 100%
3:2 2256 x 1504 2256 x 1504 30 25 – 100%
WVGA + EIS 16:9 2304 x 1296 1152 x 648 60 60 2 x 2 100%

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Figure 2. Typical Configuration: Serial MIPI
1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 10 mF and 0.1 mF decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_MIPI, VDD_IO,
and VDD. Actual values and results may vary depending on layout and design considerations.
2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the
pads as possible. In addition, place a 10 mF capacitor for each supply off−module but close to each supply.
3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
4. The pull−up resistor is not required if the controller drives a valid logic level on SCLK at all times.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. TEST pin must be tied to DGND for the MIPI configuration.
7. ON Semiconductor recommends that GND_MIPI be tied to DGND.
8. VDD_MIPI is tied to VDD_PLL in the CSP package. ON Semiconductor strongly recommends that VDD_MIPI must be connected to a
VDD_PLL in a module design since VDD_PLL and VDD_MIPI are tied together in the die.
9. The package pins or die pads used for the parallel interface must be left floating.
10.If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
11. If the TRIGGER or OE_BAR pin or pad is not used, then it should be tied to DGND.
VDD_IO VDD_PLLVDD VAA
VDD VAA VAA_PIX
Master clock
(6–27MHz)
SCLK
SDATA
RESET_BAR
TEST
EXTCLK
DGND AGND
Digital
ground
Analog
ground
Digital
Core
power1
Analog
power1
To
controller
(MIPI −serial interface)
From
controller
VDD_IO
VDD _PLL
PLL
power1
Digital
I/O
power1
1.5kΩ3, 4 1.5kΩ3, 4
Analog
power1
VAA_PIX
CLK_N
CLK_P
DATA1_P
DATA1_N
DATA2_P
DATA2_N
FLASH
SHUTTER
0.1 μF10 μF0.1 μF10 μF10 μF0.1 μF0.1 μF10 μF0.1 μF
10 μF
SADDR
TRIGGER
VDD_MIPI

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Figure 3. Typical Configuration: Parallel Pixel Data Interface
VDD
Master clock
(6–27 MHz)
SADDR
SCLK
TEST
FRAME_VALID
DOUT [11:0]
EXTCLK
DGND
Digital
ground
Analog
ground
Digital
core
power1
To
controller
From
Controller
LINE_VALID
PIXCLK
RESET_BAR
VDD_IO
Digital
I/O
power1
1.5k3, 4 1.5k3, 4
VAA VAA_PIX
Analog
power1
VDD_PLL
PLL
power1Analog
power1
VAA_PIX
VDD_IO VDD_PLLVDD VAA
AGND
TRIGGER
SHUTTER
FLASH
10 μF10 μF10 μF10 μF10 μF0.1 μF0.1 μF0.1 μF0.1 μF0.1 μF
SDATA
VDD_MIPI
OE_BAR
12.All power supplies must be adequately decoupled. ON Semiconductor recommends having 10 mF and 0.1 mF decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD.
Actual values and results may vary depending on layout and design considerations.
13.To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the
pads as possible. In addition, place a 10 mF capacitor for each supply off−module but close to each supply.
14.ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
15.The pull−up resistor is not required if the controller drives a valid logic level on SCLK at all times.
16.ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
17.TEST pin should be tied to the ground.
18.The data and clock package pins or die pads used for the MIPI interface must be left floating.
19.The VDD_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as it is tied to the VDD_PLL supply both in the
package routing and also within the sensor die itself.
20.If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
21.If the TRIGGER or OE_BAR pin or pad is not used, then it should be tied to DGND.

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PIN DESCRIPTIONS
Table 5. PIN DESCRIPTIONS
Name Type Description
RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default
EXTCLK Input Master input clock, range 6 −27 MHz
TRIGGER Input Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame
SADDR Input Two−wire serial address select
SCLK Input Two−wire serial clock input
TEST Input Enable manufacturing test modes. Tie to DGND for normal sensor operation
OE_BAR Input Parallel port output enable, active low
SDATA I/O Two−wire serial data I/O
PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock
DOUT[11:0] Output Parallel pixel data output
FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used
FRAME_VALID Output Asserted when DOUT data is valid
LINE_VALID Output LINE_VALID output asserted when DOUT data is valid
SHUTTER Output Control for external mechanical shutter. Can be left floating if not used
DATA1_P Output MIPI serial data, lane 1, differential P
DATA1_N Output MIPI serial data, lane 1, differential N
DATA2_P Output MIPI serial data, lane 2, differential P
DATA2_N Output MIPI serial data, lane 2, differential N
CLK_P Output Output MIPI serial clock, differential P
CLK_N Output Output MIPI serial clock, differential N
VDD_MIPI Power MIPI power supply
VAAHV_NPIX Power Power supply pin used to program the sensor OTPM (one−time programmable memory). This pin
should be open if OTPM is not used
VDD Power Digital power
VDD_IO Power IO supply power
VDD_PLL Power PLL power supply
DGND Power Digital GND
VAA Power Analog power
VAA_PIX Power Pixel power
AGND Power Analog GND

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Table 6. AR0330CS CSP (PARALLEL/MIPI) PACKAGE PINOUT
1 2 3 4 5 6 7 8
AVAA VAAHV_NPIX AGND NC VAA_PIX VAA VDD_IO VDD
BVDD SDATA FRAME_VALID DGND AGND DGND TEST SHUTTER
CSADDR FLASH LINE_VALID DGND DGND DGND TRIGGER RESET_BAR
DSCLK VDD_IO DOUT10 DGND VDD_IO VDD_IO EXTCLK DATA_N
EPIXCLK DOUT11 DOUT9 DOUT7 VDD_IO DGND CLK_N DATA_P
F– – DOUT8 DOUT6 DOUT4 VDD_IO CLK_P VDD_PLL
GDGND VDD DOUT5 DOUT3 DOUT1 DOUT0 DATA2_N VDD
H– DGND DGND DOUT2 VDD_IO VDD_MIPI DATA2_P VDD_MIPI
22.NC = Do not connect. For manufacturing test purpose only.
Table 7. AR0330SR CSP (PARALLEL) PACKAGE PINOUT
1 2 3 4 5 6 7 8
AVAA VAAHV_NPIX AGND NC VAA_PIX VAA VDD_IO VDD
BVDD SDATA FRAME_VALID DGND AGND DGND TEST SHUTTER
CSADDR FLASH LINE_VALID DGND DGND DGND TRIGGER RESET_BAR
DSCLK VDD_IO DOUT10 DGND VDD_IO VDD_IO EXTCLK –
EPIXCLK DOUT11 DOUT9 DOUT7 VDD_IO DGND – –
F– – DOUT8 DOUT6 DOUT4 VDD_IO – VDD_PLL
GDGND VDD DOUT5 DOUT3 DOUT1 DOUT0 – VDD
H– DGND DGND DOUT2 VDD_IO VDD_PLL – VDD_PLL
23.NC = Do not connect. For manufacturing test purpose only.

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Figure 4. PLCC Pinout
1 V DD _PLL
2 DGND
3 VDD 5 DGND 4 VDD 6 DGND 48 A GND 47 A GND 43 A GND
42 AGND
39 AGND
38 AGND
46 VAA 45 VAA 44 VAA
41 VAA_PIX
40 VAA_PIX
36 VAA HV_NPIX
34 VDD
32 OE_BAR
31 TEST
33 TRIGGER
35 NC
37 NC
RESET_BAR 30
TOP VIEW
NC 29
DOUT 0 28
DOUT 1 27 DOUT 2 26 DOUT 3 25
DOUT 4 24
DOUT 5 23
DOUT 6 22 DOUT 7 21 DOUT 8 20 DOUT 9 19
DOUT 10 18
DOUT 11 17
LINE_VALID 16
FRAME_VALID 15
SDATA 14
FLASH 13
PIXCLK 12
EXTCLK 11
SADDR 10
SCLK 9
VDD_IO 8
VDD_IO 7
Table 8. AR0330CS PLCC PACKAGE THERMAL RESISTANCE
Using JEDEC 1S0P Board Using JEDEC 2S2P Board
Junction to ambient air thermal resistance (qJA) (°C/W) 51.47 36.92
Junction to board thermal resistance (qJB) (°C/W) 22.16 21.73

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SENSOR INITIALIZATION
Power−Up Sequence
The recommended power−up sequence for the
AR0330CS is shown in Figure 5. The available power
supplies (VDD_IO, VDD_PLL, VDD_MIPI, VAA, VAA_PIX)
must have the separation specified below.
1. Turn on VDD_PLL and VDD_MIPI power supplies
2. After 100 μs, turn on VAA and VAA_PIX power
supply
3. After 100 μs, turn on VDD power supply
4. After 100 μs, turn on VDD_IO power supply
5. After the last power supply is stable, enable
EXTCLK
6. Assert RESET_BAR for at least 1ms
7. Wait 150,000 EXTCLKs (for internal initialization
into software standby
8. Write R0x3052 = 0xA114 to configure the internal
register initialization process
9. Write R0x304A = 0x0070 to start the internal
register initialization process
10. Wait 150,000 EXTCLK periods
11. Configure PLL, output, and image settings to
desired values
12. Wait 1 ms for the PLL to lock
13. Set streaming mode (R0x301A[2] = 1)
Figure 5. Power Up
24.A software reset (R0x301A[0] = 1) is not necessary after the procedure described above since a Hard Reset will automatically triggers
a software reset. Independently executing a software reset, should be followed by steps seven through thirteen above
25.The sensor must be receiving the external input clock (EXTCLK) before the reset pin is toggled. The sensor will begin an internal
initialization sequence when the reset pin toggle from LOW to HIGH. This initialization sequence will run using the external input clock.
Power on default state is software standby state, need to apply two−wire serial commands to start streaming. Above power up sequence
is a general power up sequence. For different interface configurations, MIPI, and Parallel, some power rails are not needed. Those not
needed power rails should be ignored in the general power up sequence..
EXTCLK
VAA
AA (2.8)
VDD_IO (1.8/2.8)
VDD (1.8)
VDD
DD_MIPI (2.8) t0
t1
t2
t3
t4t5
tXSoftware
Standby PLL Clock
Streaming
RESET_BAR t6
Table 9. POWER−UP SEQUENCE
Definition Symbol Min Typ Max Unit
VDD_PLL, VDD_MIPI to VAA/VAA_PIX
(Note 28)
t0 0 100 – ms
VAA/VAA_PIX to VDD t1 0 100 – ms
VDD to VDD_IO t2 0 100 – ms
External clock settling time tx – 30 (Note 26) – ms
Hard Reset t3 1 (Note 27) – – ms
Internal Initialization t4 150000 – – EXTCLKs
Internal Initialization t5 150000 – – EXTCLKs
PLL Lock Time t6 1 – – ms

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26.External clock settling time is component−dependent, usually taking about 10 – 100 ms.
27.Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
28.It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high
current draw on this supply.
29.VDD_MIPI is tied to VDD_PLL in the CSP package and must be powered to 2.8 V.
Power−Down Sequence
The recommended power−down sequence for the
AR0330CS is shown in Figure 6. The available power
supplies (VDD_IO, VDD_PLL, VDD_MIPI., VAA, VAA_PIX)
must have the separation specified below.
1. Disable streaming if output is active by setting
standby R0x301a[2] = 0
2. The soft standby state is reached after the current
row or frame, depending on configuration, has
ended
3. Turn off VDD_IO
4. Turn off VDD
5. Turn off VAA/VAA_PIX
6. Turn off VDD_PLL, VDD_MIPI
Figure 6. Power Down
EXTCLK
VDD
DD_MIPI (2.8)
VDD_IO (1.8/2.8)
VDD
DD_HiSPi (1.8)
VDD_HiSPi_TX (0.4)
t0
Power Down until Next
Power Up Cycle
t1
t2
t3
t4
VAA_PIX, VAA (2.8)
Table 10. POWER−DOWN SEQUENCE
Definition Symbol Minimum Typical Maximum Unit
VDD_IO t0 0 – – ms
VDD_IO to VDD t1 0 – – ms
VDD to VAA/VAA_PIX t2 0 – – ms
VAA/VAA_PIX to VDD_PLL t3 0 – – ms
PwrDn until Next PwrUp Time t4 100 – – ms
30.t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.

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STANDBY MODE
Soft Standby
1. Disable streaming by setting standby R0x301a[2]
= 0
2. Delay 10 ms
3. Stop EXTCLK; pull EXTCLK pin LOW
Hard Standby
1. Disable streaming by setting standby R0x301a[2]
= 0
2. Delay 10 ms
3. Pull RESET_BAR to LOW
ELECTRICAL CHARACTERISTICS
Table 11. DC Electrical Definitions and Characteristics (MIPI Mode)
fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; Output load = 68.5 pF; TJ= 60°C; Data Rate = 588 Mbps; DLL set to 0; 2304 x 1296 at 30 fps
Definition Symbol Min Typ Max Unit
Core digital voltage VDD 1.7 1.8 1.9 V
I/O digital voltage VDD_IO 1.7 1.8 1.9 V
2.4 2.8 3.1 V
Analog voltage VAA 2.76 2.8 2.9 V
Pixel supply voltage VAA_PIX 2.76 2.8 2.9 V
PLL supply voltage VDD_PLL 2.7 2.8 2.9 V
MIPI supply voltage VDD_MIPI 2.7 2.8 2.9 V
Digital operating current −114 −mA
I/O digital operating current −0−mA
Analog operating current −41 −mA
Pixel supply current −9.9 −mA
PLL supply current −15 −mA
MIPI digital operating current −35 −mA
Table 12. DC Electrical Definitions and Characteristics (Parallel Mode)
fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; Output load = 68.5 pF; TJ= 60°C; 2304 x 1296 at 30 fps
Definition Symbol Min Typ Max Unit
Core digital voltage VDD 1.7 1.8 1.9 V
I/O digital voltage VDD_IO 1.7 1.8 1.9 V
2.4 2.8 3.1 V
Analog voltage VAA 2.76 2.8 2.9 V
Pixel supply voltage VAA_PIX 2.76 2.8 2.9 V
PLL supply voltage VDD_PLL 2.7 2.8 2.9 V
Digital operating current I(VDD) 66.5 75 mA
I/O digital operating current I(VDD_IO) 24 35 mA
Analog operating current I(VAA) 36 44 mA
Pixel supply current I(VAA_PIX) 10.5 18 mA
PLL supply current I(VDD_PLL) 6 11 mA

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Table 13. STANDBY POWER
fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V;
VDD_PLL = 2.8 V; Output load = 68.5 pF; TJ= 60°C
Power Typical Max Unit
Hard Standby (CLK OFF) Digital 19.8 35.8 mA
Analog 5.8 7.0 mA
Soft Standby (CLK OFF) Digital 23.5 39.7 mA
Analog 5.4 5.9 mA
Soft Standby (CLK ON) Digital 15700 16900 mA
Analog 5.5 5.7 mA
Table 14. ABSOLUTE MAXIMUM RATINGS
Symbol Definition Min Max Unit
VDD_MAX Core digital voltage –0.3 2.4 V
VDD_IO_MAX I/O digital voltage –0.3 4 V
VAA_MAX Analog voltage –0.3 4 V
VAA_PIX Pixel supply voltage –0.3 4 V
VDD_PLL PLL supply voltage –0.3 4 V
VDD_MIPI MIPI supply voltage –0.3 4 V
tST Storage temperature –40 85 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
31.Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Figure 7. Two−Wire Serial Bus Timing Parameter
DATA
SCLK
Write Start ACK
SDATA
SCLK
Read Start ACK
tr_clk tf_clk
90%
10%
tf_sdattr_sdat
90%
10%
tSDH tSDS tSHAW tAHSW ttSTPH
STPS
Register Address
Bit 7
Write Address
Bit 0
Register Value
Bit 0
Register Value
Bit 7
Read Address
Bit 0
Register Value
Bit 0
Write Address
Bit 7
Read Address
Bit 7
tSHAR tSDSR
tSDHR
tAHSR
tSRTH tSCLK

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Table 15. TWO−WIRE SERIAL BUS CHARACTERISTICS
fEXTCLK = 27 MHz; VDD = 1.8 V; VDD_IO = 2.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; TA= 25°C
Parameter Symbol
Standard Mode Fast Mode
Unit
Min Max Min Max
SCLK Clock Frequency fSCL 0 100 0 400 KHz
Hold time (repeated) START condition
After this period, the first clock pulse is
generated
tHD;STA 4.0 −0.6 −ms
LOW period of the SCLK clock tLOW 4.7 −1.3 −ms
HIGH period of the SCLK clock tHIGH 4.0 −0.6 −ms
Set−up time for a repeated START condi-
tion
tSU;STA 4.7 −0.6 −ms
Data hold time tHD;DAT 043.455060.95ms
Data set−up time tSU;DAT 250 −1006−ns
Rise time of both SDATA and SCLK signals tr −1000 20 + 0.1Cb7300 ns
Fall time of both SDATA and SCLK signals tf −300 20 + 0.1Cb7300 ns
Set−up time for STOP condition tSU;STO 4.0 −0.6 −?s
Bus free time between a STOP and START
condition
tBUF 4.7 −1.3 −?s
Capacitive load for each bus line Cb −400 −400 pF
Serial interface input pin capacitance CIN_SI −3.3 −3.3 pF
SDATA max load capacitance CLOAD_SD −30 −30 pF
SDATA pull−up resistor RSD 1.5 4.7 1.5 4.7 K?
32.This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor.
33.Two−wire control is I2C−compatible.
34.All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz.
35. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the undefined region of the falling edge of SCLK.
36.The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal.
37.A Fast−mode I2C−bus device can be used in a Standard−mode I2C−bus system, but the requirement tSU; DAT 250 ns must then be met.
This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW
period of the SCLK signal, it must output the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the
Standard−mode I2C−bus specification) before the SCLK line is released.
38.Cb = total capacitance of one bus line in pF.
Table 16. I/O PARAMETERS
fEXTCLK = 24 MHz; VDD = 1.8V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output load = 68.5 pF; TJ= 60°C; CLK_OP = 98 MPixel/s
Symbol Definition Conditions Min Max Units
VIH Input HIGH voltage VDD_IO = 1.8 V 1.4 VDD_IO + 0.3
V
VDD_IO = 2.8 V 2.4
VIL Input LOW voltage VDD_IO = 1.8 V GND – 0.3 0.4
VDD_IO = 2.8 V GND – 0.3 0.8
IIN Input leakage current No pull−up resistor; VIN =VDD OR DGND –20 20 mA
VOH Output HIGH voltage At specified IOH VDD_IO −0.4V – V
VOL Output LOW voltage At specified IOL – 0.4 V
IOH Output HIGH current At specified VOH – –12 mA
IOL Output LOW current At specified VOL – 9 mA
IOZ Tri−state output leakage current – 10 mA

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Figure 8. I/O Timing Diagram (Parallel Mode)
Data[11:0]
R
AME_VALID/
LINE_VALID FRAME_VALID leads LINE_VALID by 609 PIXCLKs. FRAME_VALID trails
LINE_VALID by 16 PIXCLKs.
PIXCLK
*PLL disabled for tCP
EXTCLK
tCP
tR
tEXTCLK
tFtRP tFP
tPD
tPD
tPFH
tPLH
tPFL
tPLL
Pxl _ 0 Pxl _ 1 Pxl _ 2 Pxl _ n
90 %
10 %
90 %
10 %
Table 17. I/O TIMING
fEXTCLK = 24 MHz; VDD = 1.8 V; VDD_IO = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V;
Output load = 68.5 pF; TJ= 60°C; CLK_OP = 98 MPixel/s
Symbol Definition Conditions Min Typ Max Units
fEXTCLK Input clock frequency PLL enabled 6 24 27 MHz
tEXTCLK Input clock period PLL enabled 166 41 20 ns
tR Input clock rise time 0.1 – 1 V/ns
tF Input clock fall time 0.1 – 1 V/ns
Clock duty cycle 45 50 55 %
tJITTER Input clock jitter – – 0.3 ns
Output pin slew Fastest CLOAD = 15 pF – 0.7 – V/ns
fPIXCLK PIXCLK frequency Default – 80 – MHz
tPD PIXCLK to data valid Default – – 3 ns
tPFH PIXCLK to FRAME_VALID HIGH Default – – 3 ns
tPLH PIXCLK to LINE_VALID HIGH Default – – 3 ns
tPFL PIXCLK to FRAME_VALID LOW Default – – 3 ns
tPLL PIXCLK to LINE_VALID LOW Default – – 3 ns
Table 18. PARALLEL I/O RISE SLEW RATE
fEXTCLK = 24 MHz; VDD = 1.8 V; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_PLL = 2.8 V; Output load = 68.5 pF;
TJ= 60°C; CLK_OP = 98 MPixel/s
VDD_IO
Parallel Slew Rate (R0x306E[15:13])
Units
0 1 2 3 4 5 6 7
1.70V 0.069 0.115 0.172 0.239 0.325 0.43 0.558 0.836 V/ns
1.80V 0.078 0.131 0.195 0.276 0.375 0.507 0.667 1.018
1.95V 0.093 0.156 0.233 0.331 0.456 0.62 0.839 1.283
2.50V 0.15 0.252 0.377 0.539 0.759 1.07 1.531 2.666
2.80V 0.181 0.305 0.458 0.659 0.936 1.347 1.917 3.497
3.10V 0.212 0.361 0.543 0.78 1.114 1.618 2.349 4.14

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ELECTRICAL DEFINITIONS
Figure 9 is the diagram defining differential amplitude
VOD, VCM, and rise and fall times. To measure VOD and
VCM use the DC test circuit shown in Figure 10 and set the
MIPI PHY to constant Logic 1 and Logic 0. Measure Voa,
Vob and VCM with voltmeters for both Logic 1 and Logic 0.
Figure 9. Single−Ended and Differential Signals
Vo a
Vo b
Single−ended signal
Differential signal
VO D =
|Vo a – Vo b |
VOD =
|Vo b – V o a|
VC M = (Vo a + Vo b) / 2
V
O D
0 V
8 0%
tR
tF
2 0%
VO D_ A C
Vdiff _ pkpk
Vdiff
Figure 10. DC Test Circuit
V
V
5 0 Ω
5 0 Ω
Vo a
Vo b
VC M
VOD(m) +ŤVoa(m) *Vob(m) Ťwhere ȀmȀis either ″1″for logic 1 or ″0″for logic 0 (eq. 1)
VOD +VOD(1) )VOD(0)
2(eq. 2)
Vdiff +VOD(1) )VOD(0) (eq. 3)
DVOD +ŤVOD(1) *VOD(0)Ť(eq. 4)
VCM +VCM(1) )VCM(0)
2(eq. 5)

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DVCM +ŤVCM(1) *VCM(0)Ť(eq. 6)
Both VOD and VCM are measured for all output channels.
The worst case DVOD is defined as the largest difference in
VOD between all channels regardless of logic level. And the
worst case DVCM is similarly defined as the largest
difference in VCM between all channels regardless of logic
level.
Timing Definitions
1. Timing measurements are to be taken using the
Square Wave test mode
2. Rise and fall times are measured between 20% to
80% positions on the differential waveform, as
shown in Figure 9: “Single−Ended and Differential
Signals”
3. Mean Clock−to−Data skew should be measured
from the 0V crossing point on Clock to the 0V
crossing point on any Data channel regardless of
edge, as shown in Figure 11. This time is
compared with the ideal Data transition point of
0.5UI with the difference being the Clock−to−Data
Skew (see Equation 7)
Figure 11. Clock−to−Data Skew Timing Diagram
tpw
1 UI
0.5 UI
t
tCHSKEW
Clock
Data
tCHSKEW(ps) +Dt*tpw
2(eq. 7)
tCHSKEW(UI) +Dt
tpw *0.5 (eq. 8)
4. The differential skew is measured on the two
single−ended signals for any channel. The time is
taken from a transition on Voa signal to
corresponding transition on Vob signal at VCM
crossing point
Figure 12. Differential Skew
tDIFFSKEW
VCM
VCM
VCM_AC
VCM_AC
Common−mode AC Signal

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Figure 12 also shows the corresponding AC VCM
common−mode signal. Differential skew between the Voa
and Vob signals can cause spikes in the common−mode,
which the receiver needs to be able to reject. VCM_AC is
measured as the absolute peak deviation from the mean DC
VCM common−mode.
Transmitter Eye Mask
Figure 13. Transmitter Eye Mask
Normalized Time
0 0.2 0.37 0.5 0.63 10.8
*1.3 * V
OD
*V
OD
*0.7 * V
OD
0
0.7 * VOD
VOD
1.3 * VOD
Differential Amplitude
Eye Width
Eye Height
tPRE tPOST
Figure 13 defines the eye mask for the transmitter. 0.5 UI
point is the instantaneous crossing point of the Clock. The
area in white shows the area Data is prohibited from crossing
into. The eye mask also defines the minimum eye height, the
data tpre and tpost times, and the total jitter pk−pk +mean
skew (tTJSKEW) for Data.
Clock Signal
tHCLK is defined as the high clock period, and tLCLK is
defined as the low clock period as shown in Figure 14. The
clock duty cycle DCYC is defined as the percentage time the
clock is either high (tHCLK) or low (tLCLK) compared with
the clock period T.
Figure 14. Clock Duty Cycle
tHCLK
tLCLK
Clock
DCYC(1) +tHCLK
T(eq. 9)
DCYC(0) +tLCLK
T(eq. 10)
tpw +T
2(i.e, 1 UI) (eq. 11)
Bitrate +1
tpw (eq. 12)

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Figure 15 shows the definition of clock jitter for both the
period and the cycle−to−cycle jitter.
Figure 15. Clock Jitter
tLCLK tHCLK
tpw
tCKJIT (RMS)
Period Jitter (tCKJIT) is defined as the deviation of the
instantaneous clock tPW from an ideal 1UI. This should be
measured for both the clock high period variation DtHCLK,
and the clock low period variation DtLCLK taking the RMS
or 1−sigma standard deviation and quoting the worse case
jitter between DtHCLK and DtLCLK.
If pk−pk jitter is also measured, this should be limited to
±3−sigma.
SEQUENCER
The sequencer digital block determines the order and
timing of operations required to sample pixel data from the
array during each row period. It is controlled by an
instruction set that is programmed into RAM from the
sensor OTPM (One Time Programmable Memory). The
OTPM is configured during production.
The instruction set determines the length of the sequencer
operation that determines the “ADC Readout Limitation”
(Equation 5) listed in the Sensor Frame−Rate section. The
instruction set can be shortened through register writes in
order to achieve faster frame rates. Instructions for
shortening the sequencer can be found in the AR0330CS
Developer Guide.
The sequencer digital block can be reprogrammed using
the following instructions:
Program a new sequencer.
1. Place the sensor in standby
2. Write 0x8000 to R0x3088 (“seq_ctrl_port”)
3. Write each instruction incrementally to R0x3086
Each write must be 16−bit consisting of two bytes
{Byte[N], Byte[N+1]}
4. If the sequencer consists of an odd number of
bytes, set the last byte to “0”
Read the instructions stored in the sequencer.
1. Place the sensor in standby
2. Write 0xC000 to R0x3088 (“seq_ctrl_port”)
3. Sequentially read 2−bytes at a time from R0x3086

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SENSOR PLL
VCO
Figure 16. Relationship Between Readout Clock and Peak Pixel Rate
EXTCLK
(6−27 MHz)
pre_pll_clk_div
2 (1−64) pll_multiplier
58 (32−384) FVCO
The sensor contains a phase−locked loop (PLL) that is
used for timing generation and control. The required VCO
clock frequency is attained through the use of a pre−PLL
clock divider followed by a multiplier. The multiplier is
followed by set of dividers used to generate the output clocks
required for the sensor array, the pixel analog and digital
readout paths, and the output parallel and serial interfaces.
Dual Readout Paths
There are two readout paths within the sensor digital
block.
Figure 17. Sensor Dual Readout Paths
Pixel Array
All Digital
Blocks
S erial Output
CLK_PIX
CLK_PIX
Pixel Rate = 2 x CLK_PIX
= # data lanes x CLK_OP
(Parallel or MIPI)
= CLK_OP (Parallel)
(MIPI or Parallel)
All Digital
Blocks
The sensor row time calculations refers to each data−path
individually. For example, the sensor default configuration
uses 1248 clocks per row (line_length_pck) to output 2304
active pixels per row. The aggregate clocks per row seen by
the receiver will be 2496 clocks (1248 x 2 readout paths).
Parallel PLL Configuration
Figure 18. PLL for the Parallel Interface
pre_pll_clk_div
2 (1−64) 1 ( 1, 2, 4, 6, 8,
10, 12, 14, 16) 6 (4−16)
E X T C L K
( 6−27 MHz)
FV C O
CLK_OP
1/2 CLK_PIX
(Max 49 MPixels/s)
(Max 98 MPixel/s)
pll_multiplier
58 (32 −384)
vt_sys_clk_div vt_pix_clk_div

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The maximum output of the parallel interface is 98
Mpixel/s (CLK_OP). This will limit the readout clock
(CLK_PIX) to 49 MHz. The sensor will not use the FSERIAL,
FSERIAL_CLK when configured to use the parallel interface.
Table 19. PLL PARAMETERS FOR THE PARALLEL INTERFACE
Parameter Symbol Min Max Unit
External Clock EXTCLK 6 27 MHz
VCO Clock FVCO 384 768 MHz
Readout Clock CLK_PIX 49 MHz
Output Clock CLK_OP 98 Mpixel/s
Table 20. EXAMPLE PLL CONFIGURATION FOR THE PARALLEL INTERFACE
Parameter Value Output
FVCO 588 MHz (Max)
vt_sys_clk_div 1
vt_pix_clk_div 6
CLK_PIX 49 MHz (CLK_OP/2)
CLK_OP 98 Mpixel/s (= 588 MHz / 6)
Output pixel rate 98 MPixel/s
Serial PLL Configuration
Figure 19. PLL for the Serial Interface
FS E R IA L
E X T C L K
( 6−27 MHz)
FV C O
FV C O
C L K_P IX
C L K _O P
1/2 FS E R IA L _C L K
pre_pll_clk_div pll_multiplier vt_sys_clk_div vt_pix_clk_div
2 (1−64) 1 ( 1, 2, 4, 6, 8,
10, 12, 14, 16) 6 (4−16)
58 (32 −384)
op_sys_clk_div
(constant = 1)
op_pix_clk_div
12 (8, 10, 12)
The sensor will use op_sys_clk_div and op_pix_clk_div
to configure the output clock per lane (CLK_OP). The
configuration will depend on the number of active lanes (1
or 2) configured. To configure the sensor protocol and
number of lanes, refer to “Serial Configuration”.