ON Semiconductor AR0330CS User manual

©Semiconductor Components Industries, LLC, 2012
January, 2019 −Rev. 8
1Publication Order Number:
AR0330CS/D
AR0330CS
AR0330CS and AR0330SR
1/3-Inch CMOS Digital
Image Sensor
General Description
The AR0330CS can be operated in its default mode or programmed
for frame size, exposure, gain, and other parameters. The default mode
output is a 2304 x 1296 image at 30 frames per second (fps). The
sensor outputs 10−or 12−bit raw data, using either the parallel or serial
(MIPI) output ports.
The ON Semiconductor AR0330CS is a 1/3−inch CMOS digital
image sensor with an active−pixel array of 2304 (H) x1536 (V). It can
support 3.15 megapixel (2048H x 1536 V) digital still image capture
and a 1080p30 +20%EIS (2304H x 1296 V) digital video mode. It
incorporates sophisticated on−chip camera functions such as
windowing, mirroring, column and row subsampling modes, and
snapshot modes.
Table 1. KEY PARAMETERS
Parameter Typical Value
Optical Format 1/3−inch (6.0 mm)
Entire Array: 6.09 mm
Still Image: 5.63 mm (4:3)
HD Image: 5.82 mm (16:9)
Active Pixels 2304(H) x 1536(V): (Entire Array):
5.07 mm (H) x 3.38 mm (V)
2048(H) x 1536(V) (4:3, Still Mode)
2304(H) x 1296(V) (16:9, sHD Mode)
Pixel Size 2.2 mm x 2.2 mm
Color Filter Array RGB Bayer
Shutter Type ERS and GRR
Input Clock Range 6 – 27 MHz
Output Clock Maximum
(CLK_OP)
98 Mp/s (Parallel, MIPI)
Responsivity 2.0 V/lux−sec
Power Consumption 1080P30 MIPI Mode: 282 mW
1080P30 Parallel Mode: 252 mW
SNRMAX 39 dB
Dynamic Range 69.5 dB
Supply
Voltage
I/O/Digital 1.7–1.9 V (1.8 V Nominal) or
2.4–3.1 V (2.8 V Nominal)
Digital 1.7–1.9 V (1.8 V Nominal)
Analog 2.76–2.9 V
Operating Temperature
(junction) −TJ
–30°C to + 70°C
Package Options 6.28 mm x 6.65 mm CSP
11.43 mm x 11.43 mm PLCC
www.onsemi.com
See detailed ordering and shipping information on page 2 of
this data sheet.
ORDERING INFORMATION
PLCC48
11.43x11.43
CASE 776AM
Features (continued)
•2.2 mm Pixel with ON Semiconductor
A−Pix™technology
•Superior Low−light Performance
•3.5 Mp Active Array, 2.9 Mp (16:9) Video
3.4 Mp (3:2) and 3.15 Mp (4:3) Still Images
•Support for External Mechanical Shutter
•Support for External LED or Xenon Flash
•Data Interfaces: Two−lane Serial MIPI or
Parallel Interface
•On−chip phase−locked Loop (PLL)
Oscillator
•Integrated Position−based Color and Lens
Shading Correction
•Simple Two−wire Serial Interface
•Auto Black Level Calibration
•12−to−10 bit Output A−Law Compression
•Slave Mode for Precise Frame−rate Control
and for Synchronizing Two Sensors
Applications
•1080P30 High−definition Digital Video
Camcorder
•Web Cameras and Video Conferencing
Cameras
•Security
ODCSP64
6.278x6.648
CASE 570BH

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ORDERING INFORMATION
Table 2. AVAILABLE PART NUMBERS
Part Number Product Description Orderable Product Attribute Description
AR0330CS1C12SPKA0−CP 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, MIPI, CSP Tray, Protective Film
AR0330CS1C12SPKA0−CR 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, MIPI, CSP Tray, No Protective Film
AR0330CSSC12SPBA0−DR 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, PLCC Tray, No Protective Film
AR0330SR1C00SUKA0−CP 3.5 MP, 1/3−inch, 0 Deg CRA, Parallel, CSP Tray, Protective Film
AR0330SR1C00SUKA0−CR 3.5 MP, 1/3−inch, 0 Deg CRA, Parallel, CSP Tray, No Protective Film
AR0330CS1C12SPKAH3−GEVB 3.5 MP, 1/3−inch, 12 Deg CRA, Parallel, MIPI, CSP Evaluation board
FUNCTIONAL OVERVIEW
The AR0330CS is a progressive−scan sensor that
generates a stream of pixel data at a constant frame rate. It
uses an on−chip, phase−locked loop (PLL) that can generate
all internal clocks from a single master input clock running
between 6 and 27 MHz. The maximum CLK_OP is 98 Mp/s
using MIPI serial interface and 98 Mp/s using the parallel
interface.
and
Control
Timing
Figure 1. Block Diagram
Compression (optional)
12−bit
12−bit
12−bit 12−bit 8, 10, or
12−bit
Ma x 98 Mp/s
Parallel I/O:
PIXCLK, FV,
LV, DOUT [11:0]
MIPI I/O:
CLK P/N,
1. Two lane data paths
only 2. 98 Mp/sec
Digital Core
Row Noise Correction
Black Level Correction
Lens Shading Correction
Digital Gain
Data Pedestal
Test Pattern
Generator
Output Data−Path
Analog Core
Ext
Clock
Column
Amplifiers
Pixel Array
Row Drivers
PLL
Registers
Two−wire serial I/F
ADC
Max CLK_OP 98 Mp/s
User interaction with the sensor is through the two−wire
serial bus, which communicates with the array control,
analog signal chain, and digital signal chain. The core of the
sensor is a 3.5 Mp active−pixel sensor array. The timing and
control circuitry sequences through the rows of the array,
resetting and then reading each row in turn. In the time
interval between resetting a row and reading that row, the
pixels in the row integrate incident light. The exposure is
controlled by varying the time interval between reset and
readout. Once a row has been read, the signal from the
column is amplified in a column amplifier and then digitized
in an analog−to−digital converter (ADC). The output from
the ADC is a 12−bit value for each pixel in the array. The
ADC output passes through a digital processing signal chain
(which provides further data path corrections and applies
digital gain).

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WORKING MODES
The AR0330CS sensor working modes are specified from
the following aspect ratios:
Table 3. AVAILABLE ASPECT RATIOS IN THE AR0330CS SENSOR
Aspect Ratio Sensor Array Usage
3:2 Still Format #1 2256(H) x 1504(V)
4:3 Still Format #2 2048 (H) x 1536 (V)
16:10 Still Format #3 2256 (H) x 1440 (V)
16:9 FHD Format 2304 (H) x 1296 (V)
The AR0330CS supports the following working modes.
To operate the sensor at full speed 98Mp/s the sensor must
use 2−Lane MIPI or parallel interface. The sensor will
operate at full−speed (98 Mp/s) when using the parallel
interface.
Table 4. AVAILABLE WORKING MODES IN THE AR0330CS SENSOR
Mode Aspect Ratio
Active
Readout
Window
Sensor Output
Resolution
FPS
(2 lane MIPI,
12 bit)
FPS (Parallel
Interface) Subsampling FOV
1080p + EIS 16:9 2304 x 1296 2304 x 1296 30 30 – 100%
3M Still 4:3 2048 x 1536 2048 x 1536 30 25 – 100%
3:2 2256 x 1504 2256 x 1504 30 25 – 100%
WVGA + EIS 16:9 2304 x 1296 1152 x 648 60 60 2 x 2 100%

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Figure 2. Typical Configuration: Serial MIPI
1. All power supplies must be adequately decoupled. ON Semiconductor recommends having 10 mF and 0.1 mF decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_MIPI, VDD_IO,
and VDD. Actual values and results may vary depending on layout and design considerations.
2. To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the
pads as possible. In addition, place a 10 mF capacitor for each supply off−module but close to each supply.
3. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
4. The pull−up resistor is not required if the controller drives a valid logic level on SCLK at all times.
5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
6. TEST pin must be tied to DGND for the MIPI configuration.
7. ON Semiconductor recommends that GND_MIPI be tied to DGND.
8. VDD_MIPI is tied to VDD_PLL in the CSP package. ON Semiconductor strongly recommends that VDD_MIPI must be connected to a
VDD_PLL in a module design since VDD_PLL and VDD_MIPI are tied together in the die.
9. The package pins or die pads used for the parallel interface must be left floating.
10.If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
11. If the TRIGGER or OE_BAR pin or pad is not used, then it should be tied to DGND.
VDD_IO VDD_PLLVDD VAA
VDD VAA VAA_PIX
Master clock
(6–27MHz)
SCLK
SDATA
RESET_BAR
TEST
EXTCLK
DGND AGND
Digital
ground
Analog
ground
Digital
Core
power1
Analog
power1
To
controller
(MIPI −serial interface)
From
controller
VDD_IO
VDD _PLL
PLL
power1
Digital
I/O
power1
1.5kΩ3, 4 1.5kΩ3, 4
Analog
power1
VAA_PIX
CLK_N
CLK_P
DATA1_P
DATA1_N
DATA2_P
DATA2_N
FLASH
SHUTTER
0.1 μF10 μF0.1 μF10 μF10 μF0.1 μF0.1 μF10 μF0.1 μF
10 μF
SADDR
TRIGGER
VDD_MIPI

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Figure 3. Typical Configuration: Parallel Pixel Data Interface
VDD
Master clock
(6–27 MHz)
SADDR
SCLK
TEST
FRAME_VALID
DOUT [11:0]
EXTCLK
DGND
Digital
ground
Analog
ground
Digital
core
power1
To
controller
From
Controller
LINE_VALID
PIXCLK
RESET_BAR
VDD_IO
Digital
I/O
power1
1.5k3, 4 1.5k3, 4
VAA VAA_PIX
Analog
power1
VDD_PLL
PLL
power1Analog
power1
VAA_PIX
VDD_IO VDD_PLLVDD VAA
AGND
TRIGGER
SHUTTER
FLASH
10 μF10 μF10 μF10 μF10 μF0.1 μF0.1 μF0.1 μF0.1 μF0.1 μF
SDATA
VDD_MIPI
OE_BAR
12.All power supplies must be adequately decoupled. ON Semiconductor recommends having 10 mF and 0.1 mF decoupling capacitors for
every power supply. If space is a concern, then priority must be given in the following order: VAA, VAA_PIX, VDD_PLL, VDD_IO, and VDD.
Actual values and results may vary depending on layout and design considerations.
13.To allow for space constraints, ON Semiconductor recommends having 0.1 mF decoupling capacitor inside the module as close to the
pads as possible. In addition, place a 10 mF capacitor for each supply off−module but close to each supply.
14.ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
15.The pull−up resistor is not required if the controller drives a valid logic level on SCLK at all times.
16.ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is
minimized.
17.TEST pin should be tied to the ground.
18.The data and clock package pins or die pads used for the MIPI interface must be left floating.
19.The VDD_MIPI package pin and sensor die pad should be connected to a 2.8 V supply as it is tied to the VDD_PLL supply both in the
package routing and also within the sensor die itself.
20.If the SHUTTER or FLASH pins or pads are not used, then they must be left floating.
21.If the TRIGGER or OE_BAR pin or pad is not used, then it should be tied to DGND.

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PIN DESCRIPTIONS
Table 5. PIN DESCRIPTIONS
Name Type Description
RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default
EXTCLK Input Master input clock, range 6 −27 MHz
TRIGGER Input Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame
SADDR Input Two−wire serial address select
SCLK Input Two−wire serial clock input
TEST Input Enable manufacturing test modes. Tie to DGND for normal sensor operation
OE_BAR Input Parallel port output enable, active low
SDATA I/O Two−wire serial data I/O
PIXCLK Output Pixel clock out. DOUT is valid on rising edge of this clock
DOUT[11:0] Output Parallel pixel data output
FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used
FRAME_VALID Output Asserted when DOUT data is valid
LINE_VALID Output LINE_VALID output asserted when DOUT data is valid
SHUTTER Output Control for external mechanical shutter. Can be left floating if not used
DATA1_P Output MIPI serial data, lane 1, differential P
DATA1_N Output MIPI serial data, lane 1, differential N
DATA2_P Output MIPI serial data, lane 2, differential P
DATA2_N Output MIPI serial data, lane 2, differential N
CLK_P Output Output MIPI serial clock, differential P
CLK_N Output Output MIPI serial clock, differential N
VDD_MIPI Power MIPI power supply
VAAHV_NPIX Power Power supply pin used to program the sensor OTPM (one−time programmable memory). This pin
should be open if OTPM is not used
VDD Power Digital power
VDD_IO Power IO supply power
VDD_PLL Power PLL power supply
DGND Power Digital GND
VAA Power Analog power
VAA_PIX Power Pixel power
AGND Power Analog GND

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Table 6. AR0330CS CSP (PARALLEL/MIPI) PACKAGE PINOUT
1 2 3 4 5 6 7 8
AVAA VAAHV_NPIX AGND NC VAA_PIX VAA VDD_IO VDD
BVDD SDATA FRAME_VALID DGND AGND DGND TEST SHUTTER
CSADDR FLASH LINE_VALID DGND DGND DGND TRIGGER RESET_BAR
DSCLK VDD_IO DOUT10 DGND VDD_IO VDD_IO EXTCLK DATA_N
EPIXCLK DOUT11 DOUT9 DOUT7 VDD_IO DGND CLK_N DATA_P
F– – DOUT8 DOUT6 DOUT4 VDD_IO CLK_P VDD_PLL
GDGND VDD DOUT5 DOUT3 DOUT1 DOUT0 DATA2_N VDD
H– DGND DGND DOUT2 VDD_IO VDD_MIPI DATA2_P VDD_MIPI
22.NC = Do not connect. For manufacturing test purpose only.
Table 7. AR0330SR CSP (PARALLEL) PACKAGE PINOUT
1 2 3 4 5 6 7 8
AVAA VAAHV_NPIX AGND NC VAA_PIX VAA VDD_IO VDD
BVDD SDATA FRAME_VALID DGND AGND DGND TEST SHUTTER
CSADDR FLASH LINE_VALID DGND DGND DGND TRIGGER RESET_BAR
DSCLK VDD_IO DOUT10 DGND VDD_IO VDD_IO EXTCLK –
EPIXCLK DOUT11 DOUT9 DOUT7 VDD_IO DGND – –
F– – DOUT8 DOUT6 DOUT4 VDD_IO – VDD_PLL
GDGND VDD DOUT5 DOUT3 DOUT1 DOUT0 – VDD
H– DGND DGND DOUT2 VDD_IO VDD_PLL – VDD_PLL
23.NC = Do not connect. For manufacturing test purpose only.

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Figure 4. PLCC Pinout
1 V DD _PLL
2 DGND
3 VDD 5 DGND 4 VDD 6 DGND 48 A GND 47 A GND 43 A GND
42 AGND
39 AGND
38 AGND
46 VAA 45 VAA 44 VAA
41 VAA_PIX
40 VAA_PIX
36 VAA HV_NPIX
34 VDD
32 OE_BAR
31 TEST
33 TRIGGER
35 NC
37 NC
RESET_BAR 30
TOP VIEW
NC 29
DOUT 0 28
DOUT 1 27 DOUT 2 26 DOUT 3 25
DOUT 4 24
DOUT 5 23
DOUT 6 22 DOUT 7 21 DOUT 8 20 DOUT 9 19
DOUT 10 18
DOUT 11 17
LINE_VALID 16
FRAME_VALID 15
SDATA 14
FLASH 13
PIXCLK 12
EXTCLK 11
SADDR 10
SCLK 9
VDD_IO 8
VDD_IO 7
Table 8. AR0330CS PLCC PACKAGE THERMAL RESISTANCE
Using JEDEC 1S0P Board Using JEDEC 2S2P Board
Junction to ambient air thermal resistance (qJA) (°C/W) 51.47 36.92
Junction to board thermal resistance (qJB) (°C/W) 22.16 21.73

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SENSOR INITIALIZATION
Power−Up Sequence
The recommended power−up sequence for the
AR0330CS is shown in Figure 5. The available power
supplies (VDD_IO, VDD_PLL, VDD_MIPI, VAA, VAA_PIX)
must have the separation specified below.
1. Turn on VDD_PLL and VDD_MIPI power supplies
2. After 100 μs, turn on VAA and VAA_PIX power
supply
3. After 100 μs, turn on VDD power supply
4. After 100 μs, turn on VDD_IO power supply
5. After the last power supply is stable, enable
EXTCLK
6. Assert RESET_BAR for at least 1ms
7. Wait 150,000 EXTCLKs (for internal initialization
into software standby
8. Write R0x3052 = 0xA114 to configure the internal
register initialization process
9. Write R0x304A = 0x0070 to start the internal
register initialization process
10. Wait 150,000 EXTCLK periods
11. Configure PLL, output, and image settings to
desired values
12. Wait 1 ms for the PLL to lock
13. Set streaming mode (R0x301A[2] = 1)
Figure 5. Power Up
24.A software reset (R0x301A[0] = 1) is not necessary after the procedure described above since a Hard Reset will automatically triggers
a software reset. Independently executing a software reset, should be followed by steps seven through thirteen above
25.The sensor must be receiving the external input clock (EXTCLK) before the reset pin is toggled. The sensor will begin an internal
initialization sequence when the reset pin toggle from LOW to HIGH. This initialization sequence will run using the external input clock.
Power on default state is software standby state, need to apply two−wire serial commands to start streaming. Above power up sequence
is a general power up sequence. For different interface configurations, MIPI, and Parallel, some power rails are not needed. Those not
needed power rails should be ignored in the general power up sequence..
EXTCLK
VAA
AA (2.8)
VDD_IO (1.8/2.8)
VDD (1.8)
VDD
DD_MIPI (2.8) t0
t1
t2
t3
t4t5
tXSoftware
Standby PLL Clock
Streaming
RESET_BAR t6
Table 9. POWER−UP SEQUENCE
Definition Symbol Min Typ Max Unit
VDD_PLL, VDD_MIPI to VAA/VAA_PIX
(Note 28)
t0 0 100 – ms
VAA/VAA_PIX to VDD t1 0 100 – ms
VDD to VDD_IO t2 0 100 – ms
External clock settling time tx – 30 (Note 26) – ms
Hard Reset t3 1 (Note 27) – – ms
Internal Initialization t4 150000 – – EXTCLKs
Internal Initialization t5 150000 – – EXTCLKs
PLL Lock Time t6 1 – – ms

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26.External clock settling time is component−dependent, usually taking about 10 – 100 ms.
27.Hard reset time is the minimum time required after power rails are settled. In a circuit where Hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
28.It is critical that VDD_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that VDD_PLL is powered after other supplies then sensor may have functionality issues and will experience high
current draw on this supply.
29.VDD_MIPI is tied to VDD_PLL in the CSP package and must be powered to 2.8 V.
Power−Down Sequence
The recommended power−down sequence for the
AR0330CS is shown in Figure 6. The available power
supplies (VDD_IO, VDD_PLL, VDD_MIPI., VAA, VAA_PIX)
must have the separation specified below.
1. Disable streaming if output is active by setting
standby R0x301a[2] = 0
2. The soft standby state is reached after the current
row or frame, depending on configuration, has
ended
3. Turn off VDD_IO
4. Turn off VDD
5. Turn off VAA/VAA_PIX
6. Turn off VDD_PLL, VDD_MIPI
Figure 6. Power Down
EXTCLK
VDD
DD_MIPI (2.8)
VDD_IO (1.8/2.8)
VDD
DD_HiSPi (1.8)
VDD_HiSPi_TX (0.4)
t0
Power Down until Next
Power Up Cycle
t1
t2
t3
t4
VAA_PIX, VAA (2.8)
Table 10. POWER−DOWN SEQUENCE
Definition Symbol Minimum Typical Maximum Unit
VDD_IO t0 0 – – ms
VDD_IO to VDD t1 0 – – ms
VDD to VAA/VAA_PIX t2 0 – – ms
VAA/VAA_PIX to VDD_PLL t3 0 – – ms
PwrDn until Next PwrUp Time t4 100 – – ms
30.t4 is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.