Opal Kelly XEM6310 User manual

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Find the Opal Kelly XEM6310-LX45 at our website: Click HERE

Opal Kelly
A compact (75mm x 50mm) integration board featur-
ing the Xilinx Spartan-6 FPGA, SuperSpeed USB
3.0, on-board DDR2 memory, and two 16 MiB Flash
memories.
XEM6310 User’s Manual
The XEM6310 is a compact USB 3.0 (SuperSpeed) FPGA integration module featuring the Xilinx Spar-
tan-6 FPGA, 1 Gib (64 Mx16-bit) DDR2 SDRAM, two 128 Mib SPI Flash devices, high-efciency switch-
ing power supplies, and two high-density 0.8-mm expansion connectors. The USB 3.0 SuperSpeed
interface provides fast conguration downloads and PC-FPGA communication as well as easy access
with our popular FrontPanel application and SDK. A low-jitter, 100 MHz crystal oscillator is attached to
the FPGA.

Software, documentation, samples, and related materials are
Copyright © 2014-2015 Opal Kelly Incorporated.
Opal Kelly Incorporated
Portland, Oregon
http://www.opalkelly.com
All rights reserved. Unauthorized duplication, in whole or part, of this document by any means except for brief
excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated.
Opal Kelly, the Opal Kelly Logo, and FrontPanel are trademarks of Opal Kelly Incorporated.
Linux is a registered trademark of Linus Torvalds. Microsoft and Windows are both registered trademarks of
Microsoft Corporation. All other trademarks referenced herein are the property of their respective owners and no
trademark rights to the same are claimed.
Revision History:
Date Description
20120610 Initial release.
20120927 Added note regarding FPGA Bank 2 pins on JP1 and JP2.
20130115 Fixed error in XEM6010 comparison page (U12 is the correct pin. U22 was in the previous rev).
20130115 Added language about the host interface RESET pin.
20130115 Fix reference to Bank 2 I/O voltage. Corrected to 1.8v. (Previous rev said 3.3v.)
20140123 Fix incorrect non-volatile memory amount on page 5.
20140402 Added remarks about Pins reference.
20150303 Added additional information about Pins.
20160107 Added missing oscillator pin locations.

Contents
Introducing the XEM6310 ......................5
PCB Footprint .....................................5
BRK6110 Breakout Board.........................5
Functional Block Diagram............................6
FPGA ...........................................6
Power Supply .....................................6
DC Power Connector ............................7
SuperSpeed USB 3.0 Interface .......................7
On-board Peripherals ...............................7
Low-Jitter Crystal Oscillator .......................7
128-MByte Word-Wide DDR2 Synchronous DRAM ....7
FPGA Flash - 16 MiB Serial Flash Memory ...........7
System Flash - 16 MiB Serial Flash Memory ..........7
LEDs.........................................7
Expansion Connectors ..............................8
FrontPanel Support.................................8
Programmer’s Interface ..........................8
Applying the XEM6310 ........................9
Powering the XEM6310 .............................9
Power Budget ..................................9
Example XEM6310-LX150 FPGA Power Consumption..10
Supply Heat Dissipation (IMPORTANT!!).............10
Host Interface .....................................11
Reset Prole RESET ............................11
System Flash .....................................11
Layout........................................11
Loading a Power-On FPGA Conguration ............11
FPGA Flash ......................................12
LEDs ............................................12
Low-Jitter 100 MHz Oscillator.........................12
DDR2 SDRAM ....................................12
Clock Conguration (Source Synchronous) ...........13
Memory Controller Blocks ........................13
MIG Settings...................................13
JTAG ............................................14
Key Memory Storage (LX150 only) .....................14
Volatile Encryption Key Storage (Vbatt)..............14
Non-Volatile Encryption Key Storage (eFUSE) ........15
Expansion Connectors ..............................15
JP1 ..........................................15
JP2 ..........................................16
Setting I/O Voltages .............................16
Considerations for Differential Signals...............16
BRK6110 Breakout Board ............................17
Pins .............................................17
Toolbar .......................................17

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Pin Lists ......................................18
Filters ........................................18
Search .......................................18
Export (PDF, CSV, Constraints Files)................18
Peripherals ....................................19
Migrating Hardware from the XEM6010 to the XEM6310....20
FPGA Boot Conguration.........................20
Clock PLL → Clock Oscillator .....................20
Expansion Connector Differences ..................20
PCB Version History ................................21
20120517 .....................................21
XEM6310 Mechanical Drawing ..................22
BRK6110 Mechanical Drawing...................23
XEM6310 Quick Reference .....................24
XEM6310 Quick Reference .....................25

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The XEM6310 is a compact FPGA board featuring the Xilinx Spartan-6 FPGA and SuperSpeed
USB 3.0 connectivity via a USB 3.0 Micro-B receptacle. Designed as a full-featured integration
system, the XEM6310 provides access to over 110 I/O pins on its 484-pin Spartan-6 device and
has a 128-MiByte DDR2 SDRAM available to the FPGA. Two SPI Flash devices provide a total
of 32 MiB of non-volatile memory, one attached to the USB microcontroller and one attached to
the FPGA. Available with LX45 and LX150 FPGA densities, the XEM6310 is designed for me-
dium- to large-sized FPGA designs with a wide variety of external interface requirements.
PCB Footprint
A mechanical drawing of the XEM6310 is shown at the end of this manual. The PCB is 75mm
x 50mm with four mounting holes (M2 metric screws) spaced as shown in the gure. These
mounting holes are electrically isolated from all signals on the XEM6310. The two connectors
(USB and DC power) overhang the PCB by approximately 1mm in order to accommodate mount-
ing within an enclosure.
The XEM6310 has two high-density 80-pin connectors on the bottom side which provide access
to many FPGA pins, power, and JTAG.
BRK6110 Breakout Board
A simple breakout board (the BRK6110) is provided as an optional accessory to the XEM6310.
This breakout board provides DC power, JTAG connector, and easy access to the high-density
connectors on the XEM6310 by routing them to lower-density 2mm-spaced thru-holes. The
breakout board also provides a convenient reference for building boards that will mate to the
XEM6310.
Introducing the XEM6310

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Opal Kelly reserves the right to change the form-factor and possibly pinout of the BRK6110.
Therefore, unlike the XEM6310, it is not intended or recommended for production integration.
Full schematics and Gerber artwork les for the BRK6110 are provided free of charge. If your
application depends on the existing form-factor, you may reproduce this board from these docu-
ments.
A mechanical drawing of the BRK6110 is also shown at the end of this document.
Functional Block Diagram
USB Micro Spartan-6 FPGA
XC6SLX45-2FGG484
or
XC6SLX150-2FGG484
Samtec Expansion Connector
Samtec Expansion Connector
100 MHz
Clock
Host
Interface
Bus
63 I/O61 I/O
USB 3.0
8 LEDs
DDR2 SDRAM
128 MiB
FPGA Flash
16 MiB
System Flash
16 MiB
LVDS
FPGA
The XEM6310 is offered in two variants. These two variants are identical except for the FPGA
provided. The table below lists some of the differences between the two devices. Please consult
the Xilinx documentation for a more thorough comparison.
Feature XEM6310-LX45 XEM6310-LX150
FPGA XC6SLX45-2FGG484C XC6SLX150-2FGG484C
Slice Count 6,822 23,038
D Flip-Flops 54,576 184,304
Distributed RAM 401 Kib 1,355 Kib
Block RAM 2,088 Kib 4,824 Kib
DSP Slices 58 180
Clock Management Tiles 4 6
Power Supply
The XEM6310 is designed to be operated from a 5-volt power source supplied through the DC
power jack on the device or the expansion connectors on the bottom of the device. This provides
power for the three high-efciency switching regulators on-board to provide 3.3v, 1.8v and 1.2v.
0.9v is derived from the 3.3-volt supply using a small low-dropout (LDO) regulator for use as a

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DDR2 termination voltage. Each of the three switching regulators can provide up to 2A of cur-
rent.
DC Power Connector
The DC power connector on the XEM6310 is part number PJ-102AH from CUI, Inc. It is a stan-
dard “canon-style” 2.1mm / 5.5mm jack. The outer ring is connected to DGND. The center pin is
connected to +VDC.
SuperSpeed USB 3.0 Interface
The XEM6310 uses a Cypress CYUSB3014-BZXI FX3 USB microcontroller to make the XEM
a USB 3.0 peripheral. As a USB peripheral, the XEM is instantly recognized as a plug and play
peripheral on millions of PCs. More importantly, FPGA downloads to the XEM happen quickly,
virtual instruments under FrontPanel update quickly, and data transfers are blazingly fast.
On-board Peripherals
The XEM6310 is designed to compactly support a large number of applications with a small num-
ber of on-board peripherals. These peripherals are listed below.
Low-Jitter Crystal Oscillator
A xed-frequency, 100 MHz, low-jitter oscillator is included on-board and outputs LVDS to the
FPGA. The Spartan-6 FPGA can produce a wide range of clock frequencies using the on-chip
DCM and PLL capabilities.
128-MByte Word-Wide DDR2 Synchronous DRAM
The XEM also includes a 128-MiByte DDR2 SDRAM with a full 16-bit word-wide interface to the
FPGA. This SDRAM is attached exclusively to the FPGA and does not share any pins with the
expansion connector. The maximum clock rate of the SDRAM is 333 MHz. With the -2 speed
grade of the Spartan-6, the maximum clock rate is 312.5 MHz for a supported peak memory
bandwidth of 10 Gb/s.
The DDR2 SDRAM is a Micron MT47H64M16HR-3:G (or compatible).
FPGA Flash - 16 MiB Serial Flash Memory
A 128 Mib serial ash device (Numonyx N25Q128A11B1240E or equivalent) provides on-board
non-volatile storage for the FPGA. This device is attached directly to the FPGA for use in your
design.
System Flash - 16 MiB Serial Flash Memory
A 128 Mib serial ash device (Numonyx N25Q128A11B1240E or equivalent) provides on-board
non-volatile storage accessible to the USB microcontroller. This device is used to store device
rmware and conguration settings as well as other user assets such as FPGA conguration les
or calibration data. Erase, read, and write functions are available at all times (with or without a
congured FPGA) through the use of FrontPanel API methods.
LEDs
Eight LEDs and are available for general use as indicators.

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Expansion Connectors
Two high-density, 80-pin expansion connectors are available on the bottom-side of the XEM6310
PCB. These expansion connectors provide user access to several power rails on the XEM6310,
the JTAG interface on the FPGA, and 124 non-shared I/O pins on the FPGA, including several
GCLK inputs.
The connectors on the XEM6310 are Samtec part number: BSE-040-01-F-D-A. The table below
lists the appropriate Samtec mating connectors along with the total mated height.
Samtec Part Number Mated Height
BTE-040-01-F-D-A 5.00mm (0.197”)
BTE-040-02-F-D-A 8.00mm (0.315”)
BTE-040-03-F-D-A 11.00mm (0.433”)
BTE-040-04-F-D-A 16.10mm (0.634”)
BTE-040-05-F-D-A 19.10mm (0.752”)
FrontPanel Support
The XEM6310 is fully supported by Opal Kelly’s FrontPanel Application. FrontPanel augments
the limited peripheral support with a host of PC-based virtual instruments such as LEDs, hex
displays, pushbuttons, toggle buttons, and so on. Essentially, this makes your PC a recongu-
rable I/O board and adds tremendous value to the XEM6310 as an experimentation or prototyp-
ing system.
Programmer’s Interface
In addition to complete support within FrontPanel, the XEM6310 is also fully supported by the
FrontPanel SDK, a powerful C++ class library available to Windows, Mac OS X, and Linux pro-
grammers allowing you to easily interface your own software to the XEM.
In addition to the C++ library, wrappers have been written for C#, Java, and Python making the
API available under those languages as well. Sample wrappers (unsupported) are also provided
for Matlab and LabVIEW.
Complete documentation and several sample programs are installed with FrontPanel.

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Applying the XEM6310
Powering the XEM6310
The XEM6310 requires that this supply be clean, ltered, and within the range of 4.5v to 5.5v.
This supply must be delivered through the +VDC pins on the two device’s two expansion connec-
tors or the DC power connector.
The expansion bus has several power supply pins, described below:
• +VDC is provided by an external device to the XEM6310. It must be a clean, filtered sup-
ply within the range of +4.5 volts and +5.5 volts.
• +3.3v is the output of a 2-Amp switching regulator on the XEM6310.
• +1.8v is the output of a 2-Amp switching regulator on the XEM6310.
• +1.2v is the output of a 2-Amp switching regulator on the XEM6310.
• +VCCO0 is the bank-0 I/O voltage to the FPGA. Factory default is +3.3v
• +VCCO1 is the bank-1 I/O voltage to the FPGA. Factory default is +3.3v
Power Budget
The table below can help you determine your power budget for each supply rail on the XEM6310.
All values are highly dependent on the application, speed, usage, and so on. Entries we have
made are based on typical values presented in component datasheets or approximations based
on Xilinx power estimator results. Shaded boxes represent unconnected rails to a particular
component. Empty boxes represent data that the user must provide based on power estimates.
The user may also need to adjust parameters we have already estimated (such as FPGA Vcco
values) where appropriate.

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Component(s) 1.2v 1.8v 3.3v
100 MHz 150 mW
DDR2 600 mW 250 mW
FPGA Vccint
FPGA Vccaux 250 mW
FPGA Vcco3(DDR2), est. 250 mW
FPGA Vcco2(USB), est. 250 mW
FPGA Vcco0,1
Total:
Available: 2,400 mW 3,600 mW 6,600 mW
Example XEM6310-LX150 FPGA Power Consumption
XPower Estimator version 12.3 was used to compute the following power estimates for the Vc-
cint supply. These are simply estimates; your design requirements may vary considerably. The
numbers below indicate approximately 70% to 80% utilization.
Component Parameters Vccint
Clock 150 MHz GCLK - 70,000 fanout 384 mW
Clock 100 MHz GCLK - 70,000 fanout 256 mW
Logic (DFF) 150 MHz, 70,000 DFFs 380 mW
Logic (DFF) 100 MHz, 70,000 DFFs232 mW
Logic (LUT) 150 MHz, 32,000 Combinatorial, 1,000 SR, 1,000 RAM 287 mW
Logic (LUT) 100 MHz, 32,000 Combinatorial, 1,000 SR, 1,000 RAM 191 mW
BRAM 18-bit, 100 @ 150 MHz, 100 @ 100 MHz 237 mW
DSP 150 MHz, 140 slices 78 mW
MCB 150 MHz 85 mW
Misc. DCM, PLL, etc. 100 mW
Total: 2,230 mW
Available: 2,400 mW
Supply Heat Dissipation (IMPORTANT!!)
Due to the limited area available on the small form-factor of the XEM6310 and the density of logic
provided, heat dissipation may be a concern. This depends entirely on the end application and
cannot be predicted in advance by Opal Kelly. Heat sinks may be required on any of the devices
on the XEM6310. Of primary focus should be the FPGA (U5) and SDRAM (U7). Although the
switching supplies are high-efciency, they are very compact and consume a small amount of
PCB area for the current they can provide.
If you plan to put the XEM6310 in an enclosure, be sure to consider heat dissipation in your
design.

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Host Interface
There are 41 signals that connect the on-board USB microcontroller to the FPGA. These signals
comprise the host interface on the FPGA and are used for conguration downloads. After con-
guration, these signals are used to allow FrontPanel communication with the FPGA.
If the FrontPanel okHost module is instantiated in your design, you must map the interface pins to
specic pin locations using Xilinx LOC constraints. This may be done using the Xilinx constraints
editor or specifying the constraints manually in a text le. Please see the sample projects includ-
ed with your FrontPanel installation for examples.
Reset Prole RESET
Pin AB8 of the FPGA is an active-high RESET signal from the host interface. This signal is as-
serted when conguration download begins and is deasserted during the execution of the Reset
Prole. For more information on the timing of this deassertion event, see the FrontPanel User’s
Manual.
System Flash
The Flash memory attached to the USB microcontroller stores device rmware and settings as
well as user data that is accessible via the FrontPanel API. The API includes three methods
for accessing this memory: FlashEraseSector, FlashWrite, and FlashRead. Please refer to
the FrontPanel User’s Manual and the FrontPanel API Reference for information about applying
these methods.
Layout
The Numonyx N25Q128A11B1240E is a 16 MiB Flash memory arranged into 256 64-kiB sectors.
Each sector contains 256 256-byte pages. Sectors 0...15 are reserved for device rmware and
settings and are not accessible to user software. The remaining 15 MiB may be erased, written,
and read using the FrontPanel API at any time even without a valid FPGA conguration. Full 64
kiB sectors must be erased at a time. However, contents may be read or written on any page
address boundary.
Loading a Power-On FPGA Conguration
The user-area in System Flash may be used to store a Xilinx bitle to congure the FPGA at
power-on. Power-on conguration takes approximately 6-10 seconds from when power is ap-
plied. A full Reset Prole may also be performed after conguration.
The API is used to erase and program the power-on bitle and the Flashloader sample is pro-
vided to perform these steps from a simple command-line utility. Source code to the Flashloader
sample is included with the FrontPanel SDK.
Called with a single argument (the lename for a valid Xilinx bitle), the Flashloader sample will
erase the rst sectors in the System Flash user-area, then write the bitle. It will also setup the
Boot Reset Prole to point to this area on power-on.
No Power-On Conguration
Called with no arguments, the Flashloader sample will clear the existing Boot Reset Prole. This
has the effect of preventing an FPGA conguration from being loaded at power-on. This func-
tionality may also be accomplished from the API by setting an empty okTFPGAResetProle using
the API SetFPGABootResetProle. See the FrontPanel API Reference for details.

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FPGA Flash
The SPI Flash attached to the FPGA is a Numonyx N25Q128A11B1240E or equivalent. It pro-
vides non-volatile storage for use by the FPGA. It may not be used for FPGA conguration stor-
age. The System Flash is used to store FPGA “boot” congurations.
The Flash / FPGA pin mappings are shown in the table below.
Flash Pin FPGA Pin
C W1
S V3
DQ0 W3
DQ1 T4
DQ2 / WT3
DQ3 / HOLD U4
LEDs
There are eight LEDs on the XEM6310 in addition to the power LED. Each is wired directly to the
FPGA according to the pin mapping tables at the end of this document.
The LED anodes are connected to a pull-up resistor to +3.3VDD and the cathodes wired directly
to the FPGA on Bank 2 with a bank I/O voltage of 1.8v. To turn ON an LED, the FPGA pin should
be brought low. To turn OFF an LED, the FPGA pin should be at logic ‘1’.
Low-Jitter 100 MHz Oscillator
A xed-frequency, 100 MHz, low-jitter oscillator is included on-board and outputs LVDS to the
FPGA. The Spartan-6 FPGA can produce a wide range of clock frequencies using the on-chip
DCM and PLL capabilities. The pin mappings are as follows:
Oscillator Pin FPGA Pin
LVDS_P Y11
LVDS_N AB11
DDR2 SDRAM
The Micron DDR2 SDRAM is connected exclusively to the 1.8-v I/O on Bank 3 of the FPGA. The
tables below list these connections.

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DDR2 Pin FPGA Pin
CK H4
CK H3
CKE D2
CS C3
RAS K5
CAS K4
WE F2
LDQS L3
LDQS L1
UDQS T2
UDQS T1
LDM L4
UDM M3
ODT J6
A0 H2
A1 H1
A2 H5
A3 K6
A4 F3
A5 K3
A6 J4
A7 H6
A8 E3
DDR2 Pin FPGA Pin
A9 E1
A10 G4
A11 C1
A12 D1
BA0 G3
BA1 G1
BA2 F1
D0 N3
D1 N1
D2 M2
D3 M1
D4 J3
D5 J1
D6 K2
D7 K1
D8 P2
D9 P1
D10 R3
D11 R1
D12 U3
D13 U1
D14 V2
D15 V1
Clock Conguration (Source Synchronous)
The DDR2 clocking is designed to be source-synchronous from the FPGA. This means that the
FPGA sends the clock signal directly to the SDRAM along with control and data signals, allowing
very good synchronization between clock and data.
Memory Controller Blocks
Spartan-6 has integrated memory control blocks to communicate with the external DDR2 mem-
ory on the XEM6310. This is instantiated using the Xilinx Core Generator (memory interface
generator, or MIG) to create a suitable memory controller for your design. You should read and
become familiar with the DDR2 SDRAM datasheet as well as MIG and the core datasheet. Al-
though MIG can save a tremendous amount of development time, understanding all this informa-
tion is critical to building a working DDR2 memory interface.
The XEM6310 provides 1.2v as Vccint. According to the memory controller block documenta-
tion, the Spartan-6, -2 speed grade can operate memory to 312.5 MHz with this internal voltage.
MIG Settings
The following are the settings used to generate the MIG core for our RAMTester sample using
Xilinx Core Generator. These settings were used with ISE 12.2 and MIG 2.3. Note that settings
may be slightly different for different versions of ISE or MIG.

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Frequency 312.5 MHz
Memory Type Component
Memory Part MT47H64M16XX-3 (1Gb, x16)
Data Width 16
Enable DQS Enable CHECKED
High-temp self-refresh DISABLED
Output drive strength Reducedstrength
RTT(nominal) 50 ohms [default]
DCI for DQ/DQS CHECKED
DCI for address/control CHECKED
ZIO pin Y2
RZQ pin K7
Calibrated Input Selection Yes
Class for address/control Class II
Debug signals Your option
System clock Differential
JTAG
The JTAG connections on the FPGA are wired directly to the expansion connector JP2 on the
XEM6310 to facilitate FPGA conguration and ChipScope usage using a Xilinx JTAG cable. The
BRK6110 has these signals connected to a 2-mm header compatible with the Xilinx JTAG cable.
Key Memory Storage (LX150 only)
The Spartan-6 FPGA supports design security using AES decryption logic and provides two
methods for encryption key memory storage. The rst is a volatile memory storage supported
by an external battery backup supply voltage (Vbatt). The second is a one-time programmable
eFUSE. The XEM6310 design supports both types of key storage with user-modication re-
quired.
For quantity purchases of 50 or more units, please contact Opal Kelly ([e-mail]) to
discuss factory installation of these components.
Volatile Encryption Key Storage (Vbatt)
A small lithium rechargeable battery and three support components can be installed to provide
Vbatt to the FPGA when the XEM is unpowered. This will preserve the contents of the FPGA’s
volatile key storage so long as Vbatt remains over the threshold specied in the Spartan-6 docu-
mentation. Please see the Xilinx Spartan-6 FPGA Conguration User Guide (UG380) for more
details. Alternatively, Vbatt may be provided through JP2-3. In this case, BT1 should not be
installed.
The applicable schematic section and components required to support this functionality are
shown below.
RefDes Manufacturer Manufacturer P/N Comment
BT1 Seiko Instruments MS412FE-FL26E 3V, 1mAh lithium battery
D10 Micro Commercial BAS40-04-TP Schottky Diode, SOT23
C150 Generic 0.1 μF, SM-0402 Decoupling
R43, R44 Generic 4.7 kΩ, 5%, SM-0402
R41 Generic 0 Ω, SM-0402 Connects Vbatt to JP2-3

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Non-Volatile Encryption Key Storage (eFUSE)
Non-volatile storage of the encryption key is also possible by programming the Spartan-6 eFUSE
via JTAG. Please see the Xilinx Spartan-6 FPGA Conguration User Guide (UG380) for more
details.
To program the eFUSE, you must rst install the components listed in the table below. You must
also provide an external resistor (RFuse) between JP2-12 and GND. The value of this resistor is
specied in the Xilinx Spartan-6 Datasheet (DS162) between 1129 Ω and 1151 Ω.
RefDes Manufacturer Manufacturer P/N Comment
C149 Generic 0.1 μF, SM-0402 Decoupling
R7 Generic 0 Ω, SM-0402 Connects FPGA VFs to +3.3v
R42 Generic 0 Ω, SM-0402 Connects FPGA RFuse to JP2-12
Expansion Connectors
Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly
FPGA integration modules. It provides additional information on pin capabilities, pin character-
istics, and PCB routing. Additionally, Pins provides a tool for generating constraint les for place
and route tools. Pins can be found at the URL below.
http://www.opalkelly.com/pins
JP1
JP1 is an 80-pin high-density connector providing access to FPGA Banks 0, 1, and 2. Several
pins (42, 44, 59, 61, 64, 66, 77, and 79) of this connector are wired to global clock inputs on the
FPGA and can therefore be used as inputs to the global clock network.

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Pin mappings for JP1 are listed at the end of this document in the “Quick Reference” section. For
each pin, the corresponding board connection is listed. For pins connected to the FPGA, the
corresponding FPGA pin number is also shown. Finally, for pins routed to differential pair I/Os
on the FPGA, the FPGA signal names and routed track lengths have been provided to help you
equalize lengths on differential pairs.
Note that JP1 pins 8, 10, 12 are attached to FPGA Bank 2 which is powered as a 1.8v bank. This
may not be changed.
JP2
JP2 is an 80-pin high-density connector providing access to FPGA Bank 1 (except for pin JP2-11
which is on Bank 2). Several pins (38, 40, 54, 58, 59, 61, 77, and 79) of this connector are wired
to global clock inputs on the FPGA and can therefore be used as inputs to the global clock net-
work.
Pin JP2-10 is connected to the VReF pins of Bank 1.
Pin mappings for JP2 are listed at the end of this document in the “Quick Reference” section.
For each pin, the corresponding board connection is listed. For pins connected to the FPGA, the
corresponding FPGA pin number is also shown. Finally, for pins routed to differential pair I/Os
on the FPGA, the FPGA signal names and routed track lengths have been provided to help you
equalize lengths on differential pairs.
Note that JP2 pin 11 is attached to FPGA Bank 2 which is powered as a 1.8v bank. This may not
be changed.
Setting I/O Voltages
The Spartan-6 FPGA allows users to set I/O bank voltages in order to support several different
I/O signalling standards. This functionality is supported by the XEM6310 by allowing the user to
connect independent supplies to the FPGA VCCO pins on two of the FPGA banks.
By default, ferrite beads have been installed that attach each VCCO bank to the +3.3VDD supply.
If you intend to supply power to a particular I/O bank, you MUST remove the appropriate ferrite
beads. Power can then be supplied through the expansion connectors.
The table below lists details for user-supplied I/O bank voltages
I/O Bank Expansion Pins Ferrite Bead
0 JP1-36, 56 FB1
1 JP2-35, 55 FB2
Considerations for Differential Signals
The XEM6310 PCB layout and routing has been designed with several applications in mind,
including applications requiring the use of differential (LVDS) pairs. Please refer to the Xilinx
Spartan-6 datasheet for details on using differential I/O standards with the Spartan-6 FPGA.
Note: LVDS output on the Spartan-6 is restricted to banks 0 and 2. LVDS input is available on
all banks. For more information, please refer to the Spartan-6 FPGA SelectIO Resources User
Guide from Xilinx.

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FPGA I/O Bank Voltages
In order to use differential I/O standards with the Spartan-6, you must set the VCCO voltages for
the appropriate banks to 2.5v according to the Xilinx Spartan-6 datasheet. Please see the sec-
tion above entitled “Setting I/O Voltages” for details.
Characteristic Impedance
The characteristic impedance of all routes from the FPGA to the expansion connector is approxi-
mately 50-Ω.
Differential Pair Lengths
In many cases, it is desirable that the route lengths of a differential pair be matched within some
specication. Care has been taken to route differential pairs on the FPGA to adjacent pins on the
expansion connectors whenever possible. We have also included the lengths of the board routes
for these connections to help you equalize lengths in your nal application. Due to space con-
straints, some pairs are better matched than others.
Reference Voltage Pins (VReF)
The Xilinx Spartan-6 supports externally-applied input voltage thresholds for some input signal
standards. The XEM6310 supports these VReF applications for banks 0 and 1:
For Bank 0, the four VReF pins are routed to expansion connector JP1 on pins 48, 51, 62, and 65.
Note that all four must be connected to the same voltage for proper application of input thresh-
olds. Please see the Xilinx Spartan-6 documentation for more details.
For Bank 1, the four VReF pins are connected to a single pin on expansion connector JP2, pin 10.
BRK6110 Breakout Board
The BRK6110 is a simple two-layer “breakout board” which can be used to evaluate or transition
to the XEM6310. It provides standard 2-mm thru-hole connections to the 0.8-mm high-density
connectors on the XEM6310 and a DC power connector (2.1mm/5.5mm, center positive) for pro-
viding +VDC to the XEM6310. Please visit the Pins reference for the XEM6310 for pin mapping
details.
Pins
Opal Kelly Pins is an interactive online reference for the expansion connectors on all Opal Kelly
FPGA integration modules. It provides additional information on pin capabilities, pin character-
istics, and PCB routing. Additionally, Pins provides a tool for generating constraint les for place
and route tools. Pins can be found at the URL below.
http://www.opalkelly.com/pins
Toolbar
The toolbar at the top of a Pins product page has a number of features. Explore a bit; you won’t
break it.

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Pin Lists
As the primary reference for Opal Kelly integration module expansion connectors, Pin Lists con-
tain a comprehensive table of the FPGA-to-Connector data including connector pin, FPGA pin,
signal description, routed length (when applicable), breakout board pin mapping, FPGA I/O bank,
and other properties.
By default, not all data columns are visible. Click on the “Toggle Filters” icon at the top-left to se-
lect which columns to show. Depending on the specic module, several additional columns may
be shown. The data in these columns is always exported when you export the pin list to CSV.
Filters
You can hide or show the additional information associated with each signal by clicking on the
icon at the top left (“Toggle Filters”). Use these lters to limit the visible pin listing to particular
subsets of signals you are interested in.
Search
You can search the pin list using the search entry at the top-right. Click on the magnifying glass
drop-down to adjust the function of the search to one of:
• Highlight - Highlights search results only.
• Hide Matching - Hides rows where search matches are found.
• Show Only Matching - Shows only rows where a search match is found.
Export (PDF, CSV, Constraints Files)
The export button near the search entry allows you to export the pin list in several formats. PDFs
can be viewed or printed. CSV can be loaded into a spreadsheet application or manipulated with
scripts. Constraints les can be used as inputs to Xilinx and Altera synthesis and mapping tools.

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The constraints les include additional mapping information for other peripherals on the module
such as memory, clock oscillators, and LEDs.
Peripherals
A Pins Peripheral is a project denition where you can enter your top-level HDL design nets to
have Pins generate a complete constraint le for you.
When you create a Peripheral, you will select a target integration module. The Peripheral is
paired to this module so that the design parameters match the features and expansion capabili-
ties of the module.
Specifying Net Names
The Pin List view for a Peripheral includes three additional, editable columns:
• Design Net - The name of the signal as it appears in your top-level HDL.
• Constraints - Text that is inserted into the constraints le for that signal.
• Comment - Additional comment text that is added to the constraints le.
These additional data are merged with the default Pin List constraints le prior to export. The re-
sult is a constraints le complete with net names that can be used with your FPGA development
ow.
Export Features
Enable the specic module features you
would like to appear in the exported con-
straints le. When a feature is enabled,
Pins will export the constraints appropri-
ate to that feature such as pin locations.
When a feature is disabled, Pins will skip
that portion.
The User Lead In and User Lead Out
sections allow you to add custom pay-
loads (your own constraints) that will be
added to the exported constraints le.
Additional timing constraints or com-
ments can be added here.