Opal Kelly XEM6010 User manual

Opal Kelly
A compact (75mm x 50mm) integration board featuring
the Xilinx Spartan-6 FPGA, High-Speed USB 2.0, and
on-board DDR2 memory.
XEM6010 User’s Manual
The XEM6010 is a compact USB 2.0 FPGA integration module featuring the Xilinx Spartan-6 FPGA, 1
Gb (64 Mx16-bit) DDR2 SDRAM, high-efciency switching power supplies, and two high-density 0.8-mm
expansion connectors. The high-speed USB 2.0 interface provides fast conguration downloads and
PC-FPGA communication as well as easy access with our popular FrontPanel application and SDK. A
exible, multiple-output PLL is also provided on-board..

Software, documentation, samples, and related materials are
Copyright © 2010-2012 Opal Kelly Incorporated.
Opal Kelly Incorporated
Portland, Oregon
http://www.opalkelly.com
All rights reserved. Unauthorized duplication, in whole or part, of this document by any means except for brief
excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated.
Opal Kelly, the Opal Kelly Logo, and FrontPanel are trademarks of Opal Kelly Incorporated.
Linux is a registered trademark of Linus Torvalds. Microsoft and Windows are both registered trademarks of
Microsoft Corporation. All other trademarks referenced herein are the property of their respective owners and no
trademark rights to the same are claimed.
Revision History:
Date Description
20110301 Initial release.
20110317 Minor updates.
20110406 Added note and reference regarding LVDS output restriction for Spartan-6.
20110818 Fix minor typo in pinout table. L59N_1 changed to L49N_1
20110926 Added sections on MUXSEL and I2C_SCL / I2C_SDA treatment.
20120216 Added another table to the BRK6110 connections section.

Contents
Introducing the XEM6010 ......................5
PCB Footprint .....................................5
BRK6110 Breakout Board.........................5
Functional Block Diagram............................6
FPGA ...........................................6
Power Supply .....................................6
DC Power Connector ............................7
High-Speed USB 2.0 Interface ........................7
On-board Peripherals ...............................7
Cypress CY22393 PLL...........................7
128-MByte Word-Wide DDR2 Synchronous DRAM . . . . 7
SerialFlashMemory ............................7
LEDs.........................................7
ExpansionConnectors..............................7
FrontPanel Support.................................8
Programmer’s Interface ..........................8
ApplyingtheXEM6010 ........................9
Powering the XEM6010 .............................9
Power Budget ..................................9
Example XEM6010-LX150 FPGA Power Consumption. . 10
Supply Heat Dissipation (IMPORTANT!!).............10
Host Interface .....................................11
MUXSEL......................................11
I2CConnections................................11
SPI Flash ........................................11
FlashLoader Sample ............................12
LEDs ............................................12
DDR2SDRAM....................................12
Clock Conguration (Source Synchronous) ...........13
Memory Controller Blocks ........................13
MIG Settings...................................13
JTAG ............................................14
ExpansionConnectors..............................14
JP2 ..........................................14
JP3 ..........................................14
Setting I/O Voltages .............................15
Considerations for Differential Signals...............15
BRK6110 Breakout Board ............................16
Migrating from the XEM3010 to the XEM6010 ............17
Four I/O Banks → Two I/O Banks. . . . . . . . . . . . . . . . . . . 17
32 MiB SDR SDRAM → 128 MiB DDR2 SDRAM ......17
Two Pushbuttons → No Pushbuttons................17
Expansion Connector Differences ..................17
JTAGConnectivity..............................17
Migrating from the XEM3050 to the XEM6010 ............18
Four I/O Banks → Two I/O Banks. . . . . . . . . . . . . . . . . . . 18

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64 MiB SDR SDRAM → 128 MiB DDR2 SDRAM ......18
Synchronous SRAM Removed . . . . . . . . . . . . . . . . . . . . 18
Expansion Connector Differences ..................18
JTAGConnectivity..............................18
XEM6010 Mechanical Drawing ..................20
BRK6110 Mechanical Drawing...................21
XEM6010 Quick Reference ..................... 22
XEM6010 Quick Reference ..................... 23

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The XEM6010 is a compact FPGA board featuring the Xilinx Spartan-6 FPGA and high-speed
USB 2.0 connectivity. Designed as a full-featured integration system, the XEM6010 provides ac-
cess to over 110 I/O pins on its 484-pin Spartan-6 device and has a 128-MiByte DDR2 SDRAM
available to the FPGA. The XEM6010 is designed for medium-sized FPGA designs with a wide
variety of external interface requirements.
PCB Footprint
A mechanical drawing of the XEM6010 is shown at the end of this manual. The PCB is 75mm
x 50mm with four mounting holes (M2 metric screws) spaced as shown in the gure. These
mounting holes are electrically isolated from all signals on the XEM6010. The two connectors
(USB and DC power) overhang the PCB by approximately 4mm in order to accommodate mount-
ing within an enclosure.
The XEM6010 has two high-density 80-pin connectors on the bottom side which provide access
to many FPGA pins, power, and JTAG.
BRK6110 Breakout Board
A simple breakout board (the BRK6110) is provided as an optional accessory to the XEM6010.
This breakout board provides DC power and easy access to the high-density connectors on the
XEM6010 by routing them to lower-density 2mm-spaced thru-holes. The breakout board also
provides a convenient reference for building boards that will mate to the XEM6010.
Opal Kelly reserves the right to change the form-factor and possibly pinout of the BRK6110.
Therefore, unlike the XEM6010, it is not intended or recommended for production integration.
Introducing the XEM6010

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Full schematics and Gerber artwork les for the BRK6110 are provided free of charge. If your
application depends on the existing form-factor, you may reproduce this board from these docu-
ments.
A mechanical drawing of the BRK6110 is also shown at the end of this document.
Functional Block Diagram
USB Micro
(CY68013A)
Spartan-6 FPGA
XC6SLX45-2FGG484
or
XC6SLX150-2FGG484
Samtec Expansion Connector
Samtec Expansion Connector
PLL
(CY22393)
Host Interface
Bus
60 I/O60 I/O
3 PLL CLKs
USB 2.0
8 LEDs
DDR2 SDRAM
128 MiB
Flash
32 Mib
1 PLL CLK
1 PLL CLK
FPGA
The XEM6010 is offered in two variants. These two variants are identical except for the FPGA
provided. The table below lists some of the differences between the two devices. Please consult
the Xilinx documentation for a more thorough comparison.
Feature XEM6010-LX45 XEM6010-LX150
FPGA XC6SLX45-2FGG484C XC6SLX150-2FGG484C
Slice Count 6,822 23,038
D Flip-Flops 54,576 184,304
Distributed RAM 401 Kib 1,355 Kib
Block RAM 2,088 Kib 4,824 Kib
DSP Slices 58 180
Clock Management Tiles 4 6
Power Supply
The XEM6010 is designed to be operated from a 5-volt power source supplied through the DC
power jack on the device or the expansion connectors on the bottom of the device. This provides
power for the three high-efciency switching regulators on-board to provide 3.3v, 1.8v and 1.2v.
0.9v is derived from the 3.3-volt supply using a small low-dropout (LDO) regulator for use as a
DDR2 termination voltage. Each of the three switching regulators can provide up to 2A of cur-
rent.

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DC Power Connector
The DC power connector on the XEM6010 is part number PJ-102AH from CUI, Inc. It is a stan-
dard “canon-style” 2.1mm / 5.5mm jack. The outer ring is connected to DGND. The center pin is
connected to +VDC.
High-Speed USB 2.0 Interface
The XEM6010 uses a Cypress CY7C68013A FX2LP USB microcontroller to make the XEM a
USB 2.0 peripheral. As a USB peripheral, the XEM is instantly recognized as a plug and play
peripheral on millions of PCs. More importantly, FPGA downloads to the XEM happen blazingly
fast, virtual instruments under FrontPanel update quickly, and data transfers are much faster than
the parallel port interfaces common on many FPGA experimentation boards.
On-board Peripherals
The XEM6010 is designed to compactly support a large number of applications with a small num-
ber of on-board peripherals. These peripherals are listed below.
Cypress CY22393 PLL
A multi-output, triple-PLL clock generator can provide up to ve clocks, three to the FPGA and
another two to the expansion connectors JP2 and JP3. The PLL is driven by a 48-MHz signal
output from the USB microcontroller. The PLL can output clocks up to 150-MHz and is congured
through the FrontPanel software interface or the FrontPanel API.
128-MByte Word-Wide DDR2 Synchronous DRAM
The XEM also includes a 128-MiByte DDR2 SDRAM with a full 16-bit word-wide interface to the
FPGA. This SDRAM is attached exclusively to the FPGA and does not share any pins with the
expansion connector. The maximum clock rate of the SDRAM is 333 MHz. With the -2 speed
grade of the Spartan-6, the maximum clock rate is 312.5 MHz for a supported peak memory
bandwidth of 10 Gb/s.
The DDR2 SDRAM is a Micron MT47H64M16HR-3:G (or compatible).
Serial Flash Memory
A 32 Mib serial ash device (Numonyx M25P32-VME6G or equivalent) provides on-board con-
guration memory for the FPGA as well as general non-volatile storage for your design.
LEDs
Eight LEDs and are available for general use as debug outputs.
Expansion Connectors
Two high-density, 80-pin expansion connectors are available on the bottom-side of the XEM6010
PCB. These expansion connectors provide user access to several power rails on the XEM6010,
the JTAG interface on the FPGA, and 124 non-shared I/O pins on the FPGA, including several
GCLK inputs.
The connectors on the XEM6010 are Samtec part number: BSE-040-01-F-D-A. The table below
lists the appropriate Samtec mating connectors along with the total mated height.

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Samtec Part Number Mated Height
BTE-040-01-F-D-A 5.00mm (0.197”)
BTE-040-02-F-D-A 8.00mm (0.315”)
BTE-040-03-F-D-A 11.00mm (0.433”)
BTE-040-04-F-D-A 16.10mm (0.634”)
BTE-040-05-F-D-A 19.10mm (0.752”)
FrontPanel Support
The XEM6010 is fully supported by Opal Kelly’s FrontPanel Application. FrontPanel augments
the limited peripheral support with a host of PC-based virtual instruments such as LEDs, hex
displays, pushbuttons, toggle buttons, and so on. Essentially, this makes your PC a recongu-
rable I/O board and adds tremendous value to the XEM6010 as an experimentation or prototyp-
ing system.
Programmer’s Interface
In addition to complete support within FrontPanel, the XEM6010 is also fully supported by the
FrontPanel SDK, a powerful C++ class library available to Windows, Mac OS X, and Linux pro-
grammers allowing you to easily interface your own software to the XEM.
In addition to the C++ library, wrappers have been written for C#, Java, and Python making the
API available under those languages as well. Sample wrappers are also provided for Matlab and
LabVIEW.
Complete documentation and several sample programs are installed with FrontPanel.

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Applying the XEM6010
Powering the XEM6010
The XEM6010 requires that this supply be clean, ltered, and within the range of 4.5v to 5.5v.
This supply must be delivered through the +VDC pins on the two device’s two expansion connec-
tors or the DC power connector..
The expansion bus has several power supply pins, described below:
• +VDC is provided by an external device to the XEM6010. It must be a clean, filtered sup-
ply within the range of +4.5 volts and +5.5 volts.
• +3.3v is the output of a 2-Amp switching regulator on the XEM6010.
• +1.8v is the output of a 2-Amp switching regulator on the XEM6010.
• +1.2v is the output of a 2-Amp switching regulator on the XEM6010.
• +VCCO0 is the bank-0 I/O voltage to the FPGA. Factory default is +3.3v
• +VCCO1 is the bank-1 I/O voltage to the FPGA. Factory default is +3.3v
Power Budget
The table below can help you determine your power budget for each supply rail on the XEM6010.
All values are highly dependent on the application, speed, usage, and so on. Entries we have
made are based on typical values presented in component datasheets or approximations based
on Xilinx power estimator results. Shaded boxes represent unconnected rails to a particular
component. Empty boxes represent data that the user must provide based on power estimates.
The user may also need to adjust parameters we have already estimated (such as FPGA Vc c o
values) where appropriate.

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Component(s) 1.2v 1.8v 3.3v
USB 2.0, PLL 320 mW
DDR2 600 mW 250 mW
FPGA Vc c i n t
FPGA Vc c a u x 250 mW
FPGA Vc c o 3(DDR2), est. 250 mW
FPGA Vc c o 2(USB), est. 250 mW
FPGA Vc c o 0,1
Total:
Available: 2,400 mW 3,600 mW 6,600 mW
Example XEM6010-LX150 FPGA Power Consumption
XPower Estimator version 12.3 was used to compute the following power estimates for the Vc-
c i n t supply. These are simply estimates; your design requirements may vary considerably. The
numbers below indicate approximately 70% to 80% utilization.
Component Parameters Vc c i n t
Clock 150 MHz GCLK - 70,000 fanout 384 mW
Clock 100 MHz GCLK - 70,000 fanout 256 mW
Logic (DFF) 150 MHz, 70,000 DFFs 380 mW
Logic (DFF) 100 MHz, 70,000 DFFs232 mW
Logic (LUT) 150 MHz, 32,000 Combinatorial, 1,000 SR, 1,000 RAM 287 mW
Logic (LUT) 100 MHz, 32,000 Combinatorial, 1,000 SR, 1,000 RAM 191 mW
BRAM 18-bit, 100 @ 150 MHz, 100 @ 100 MHz 237 mW
DSP 150 MHz, 140 slices 78 mW
MCB 150 MHz 85 mW
Misc. DCM, PLL, etc. 100 mW
Total: 2,230 mW
Available: 2,400 mW
Supply Heat Dissipation (IMPORTANT!!)
Due to the limited area available on the small form-factor of the XEM6010 and the density of logic
provided, heat dissipation may be a concern. This depends entirely on the end application and
cannot be predicted in advance by Opal Kelly. Heat sinks may be required on any of the devices
on the XEM6010. Of primary focus should be the FPGA (U10) and SDRAM (U11). Although the
switching supplies are high-efciency, they are very compact and consume a small amount of
PCB area for the current they can provide.
If you plan to put the XEM6010 in an enclosure, be sure to consider heat dissipation in your
design.

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Host Interface
There are 26 pins that connect the on-board USB microcontroller to the FPGA. These pins com-
prise the host interface on the FPGA and are used for conguration downloads. After congura-
tion, these pins are used to allow FrontPanel communication with the FPGA.
If the FrontPanel okHost module is instantiated in your design, you must map the interface pins to
specic pin locations using Xilinx LOC constraints. This may be done using the Xilinx constraints
editor or specifying the constraints manually in a text le. Please see the sample projects includ-
ed with your FrontPanel installation for examples.
MUXSEL
MUXSEL is a signal on the XEM6010 which selects the signal path to the FPGA programming
signals D0 and CCLK. When low (deasserted), the FPGA and USB microcontroller are connect-
ed. When high (asserted), the FPGA and PROM are connected.
In normal USB-programmed operation, JP5 is in the USB position connecting the FPGA and
USB microcontroller at all times. This allows USB-based programming of the FPGA and subse-
quent USB communication with the FPGA design after conguration.
In order to allow the SPI to congure the FPGA, JP5 must be in the PROM position.. In order
to deassert MUXSEL post-conguration, your design must deassert MUXSEL. This allows the
FPGA design to properly startup and allows for communication over USB even after the PROM
has congured it.
The end result is that your FPGA design should tie HI_MUXSEL to 0. This is the case regardless
of how the design was congured (via PROM or USB). For example, in Verilog:
assign hi_muxsel = 1’b0;
I2C Connections
The FPGA on the XEM6010 is attached to the I2C lines from the USB microcontroller. In order
to avoid contention with the I2C bus, these lines should be set to high-impedance within your
design. If this is not done, FrontPanel may timeout or hang when trying to communicate with the
XEM6010, particularly when programming the on-board PLL.
The following lines in your UCF (contraints) le will attach pull-ups to the I2C lines:
NET “i2c_sda” LOC = “AB9” | IOSTANDARD=”LVCMOS33” | PULLUP;
NET “i2c_scl” LOC = “Y9” | IOSTANDARD=”LVCMOS33” | PULLUP;
In addition, you will need to set these signals to high-impedance in your HDL. Here is an exam-
ple of how to do this in Verilog:
assign i2c_sda = 1’bz;
assign i2c_scl = 1’bz;
SPI Flash
The SPI ash on the module is a Numonyx M25P32-VME6G or equivalent. It can be pro-
grammed (using the FlashLoader sample) with an FPGA conguration bitle to congure the

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FPGA on boot. To boot the FPGA from ash, the switch JP5 must be slid to the “PROM” posi-
tion. To boot the FPGA using FrontPanel, the switch must be slid to the “USB” position. In both
cases, FrontPanel communication is available after conguration completes.
Flash Pin FPGA Pin
CW12
S T5
D AB15
Q Y15
FlashLoader Sample
The FlashLoader sample is installed with your FrontPanel installation. It is a simple command-
line utility that you can use to program the SPI ash with an FPGA conguration le. Please see
the Samples directory for more information.
You can also load a conguration le to the Flash using your own HDL, of course. There is noth-
ing special about the way our FlashLoader sample loads the conguration le into the Flash.
LEDs
There are eight LEDs on the XEM6010. Each is wired directly to the FPGA according to the pin
mapping tables at the end of this document.
The LED anodes are connected to a pull-up resistor to +3.3VDD and the cathodes wired directly
to the FPGA on Bank 2 with a bank I/O voltage of 3.3v. To turn ON an LED, the FPGA pin should
be brought low. To turn OFF an LED, the FPGA pin should be at logic ‘1’.
DDR2 SDRAM
The Micron DDR2 SDRAM is connected exclusively to the 1.8-v I/O on Bank 3 of the FPGA. The
tables below list these connections.

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DDR2 Pin FPGA Pin
CK H4
CK H3
CKE D2
CS C3
RAS K5
CAS K4
WE F2
LDQS L3
LDQS L1
UDQS T2
UDQS T1
LDM L4
UDM M3
ODT J6
A0 H2
A1 H1
A2 H5
A3 K6
A4 F3
A5 K3
A6 J4
A7 H6
A8 E3
DDR2 Pin FPGA Pin
A9 E1
A10 G4
A11 C1
A12 D1
BA0 G3
BA1 G1
BA2 F1
D0 N3
D1 N1
D2 M2
D3 M1
D4 J3
D5 J1
D6 K2
D7 K1
D8 P2
D9 P1
D10 R3
D11 R1
D12 U3
D13 U1
D14 V2
D15 V1
Clock Conguration (Source Synchronous)
The DDR2 clocking is designed to be source-synchronous from the FPGA. This means that the
FPGA sends the clock signal directly to the SDRAM along with control and data signals, allowing
very good synchronization between clock and data.
Memory Controller Blocks
Spartan-6 has integrated memory control blocks to communicate with the external DDR2 mem-
ory on the XEM6010. This is instantiated using the Xilinx Core Generator (memory interface
generator, or MIG) to create a suitable memory controller for your design. You should read and
become familiar with the DDR2 SDRAM datasheet as well as MIG and the core datasheet. Al-
though MIG can save a tremendous amount of development time, understanding all this informa-
tion is critical to building a working DDR2 memory interface.
The XEM6010 provides 1.2v as Vc c i n t . According to the memory controller block documenta-
tion, the Spartan-6, -2 speed grade can operate memory to 312.5 MHz with this internal voltage.
MIG Settings
The following are the settings used to generate the MIG core for our RAMTester sample using
Xilinx Core Generator. These settings were used with ISE 12.2 and MIG 2.3. Note that settings
may be slightly different for different versions of ISE or MIG.

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Frequency 312.5 MHz
Memory Type Component
Memory Part MT47H64M16XX-3 (1Gb, x16)
Data Width 16
Enable DQS Enable CHECKED
High-temp self-refresh DISABLED
Output drive strength Reducedstrength
RTT(nominal) 50 ohms [default]
DCI for DQ/DQS CHECKED
DCI for address/control CHECKED
ZIO pin Y2
RZQ pin K7
Calibrated Input Selection Yes
Class for address/control Class II
Debug signals Your option
System clock Differential
JTAG
The JTAG connections on the FPGA are wired directly to the expansion connector JP2 on the
XEM6010 to facilitate FPGA conguration and ChipScope usage using a Xilinx JTAG cable. The
BRK6110 has these signals connected to a 2-mm header compatible with the Xilinx JTAG cable.
Expansion Connectors
JP2
JP2 is an 80-pin high-density connector providing access to FPGA Bank 1. Several pins (38, 40,
54, 58, 59, 61, 77, and 79) of this connector are wired to global clock inputs on the FPGA and can
therefore be used as inputs to the global clock network.
Pin JP2-10 is connected to the Vr e F pins of Bank 1.
Pin mappings for JP2 are listed at the end of this document in the “Quick Reference” section.
For each pin, the corresponding board connection is listed. For pins connected to the FPGA, the
corresponding FPGA pin number is also shown. Finally, for pins routed to differential pair I/Os
on the FPGA, the FPGA signal names and routed track lengths have been provided to help you
equalize lengths on differential pairs.
JP3
JP3 is an 80-pin high-density connector providing access to FPGA Banks 0 and 1. Several pins
(42, 44, 59, 61, 64, 66, 77, and 79) of this connector are wired to global clock inputs on the FPGA
and can therefore be used as inputs to the global clock network.
Pin mappings for JP3 are listed at the end of this document in the “Quick Reference” section.
For each pin, the corresponding board connection is listed. For pins connected to the FPGA, the
corresponding FPGA pin number is also shown. Finally, for pins routed to differential pair I/Os
on the FPGA, the FPGA signal names and routed track lengths have been provided to help you
equalize lengths on differential pairs.

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Setting I/O Voltages
The Spartan-6 FPGA allows users to set I/O bank voltages in order to support several different
I/O signalling standards. This functionality is supported by the XEM6010 by allowing the user to
connect independent supplies to the FPGA VCCO pins on two of the FPGA banks.
By default, ferrite beads have been installed that attach each VCCO bank to the +3.3VDD supply.
If you intend to supply power to a particular I/O bank, you MUST remove the appropriate ferrite
beads. Power can then be supplied through the expansion connectors.
The table below lists details for user-supplied I/O bank voltages
I/O Bank Expansion Pins Ferrite Bead
0 JP3-36, 56 FB2
1 JP2-35, 55 FB1
Considerations for Differential Signals
The XEM6010 PCB layout and routing has been designed with several applications in mind,
including applications requiring the use of differential (LVDS) pairs. Please refer to the Xilinx
Spartan-6 datasheet for details on using differential I/O standards with the Spartan-6 FPGA.
Note: LVDS output on the Spartan-6 is restricted to banks 0 and 2. LVDS input is available on
all banks. For more information, please refer to the Spartan-6 FPGA SelectIO Resources User
Guide from Xilinx.
FPGA I/O Bank Voltages
In order to use differential I/O standards with the Spartan-6, you must set the VCCO voltages for
the appropriate banks to 2.5v according to the Xilinx Spartan-6 datasheet. Please see the sec-
tion above entitled “Setting I/O Voltages” for details.
Characteristic Impedance
The characteristic impedance of all routes from the FPGA to the expansion connector is approxi-
mately 50-Ω.
Differential Pair Lengths
In many cases, it is desirable that the route lengths of a differential pair be matched within some
specication. Care has been taken to route differential pairs on the FPGA to adjacent pins on the
expansion connectors whenever possible. We have also included the lengths of the board routes
for these connections to help you equalize lengths in your nal application. Due to space con-
straints, some pairs are better matched than others.
Reference Voltage Pins (Vr e F )
The Xilinx Spartan-6 supports externally-applied input voltage thresholds for some input signal
standards. The XEM6010 supports these Vr e F applications for banks 0 and 1:
For Bank 0, the four Vr e F pins are routed to expansion connector JP3 on pins 48, 51, 62, and 65.
Note that all four must be connected to the same voltage for proper application of input thresh-
olds. Please see the Xilinx Spartan-6 documentation for more details.
For Bank 1, the four Vr e F pins are connected to a single pin on expansion connector JP2, pin 10.

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BRK6110 Breakout Board
The BRK6110 is a simple two-layer “breakout board” which can be used to evaluate or transition
to the XEM6010. It provides standard 2-mm thru-hole connections to the 0.8-mm high-density
connectors on the XEM6010 and a DC power connector (2.1mm/5.5mm, center positive) for pro-
viding +VDC to the XEM6010.
What follows is a detailed description of how the BRK6110 pins connect to the XEM6010. The
description belies the simplicity of this interconnect. It should be pretty obvious just by looking at
the traces on the BRK6110. You may download the schematics and layout for the BRK6110 from
our website:
http://www.opalkelly.com/download/
The corresponding connections to the XEM6010 are labelled in silkscreen on the BRK6110. The
BRK6110 connectors essentially mirror the connections on the XEM6010. For example, the JP2
connector on the XEM6010 mates to JP1 on the BRK6110 and is electrically connected to JP1A
and JP1B on the BRK6110 according to the table below.
Note that the pins on JP1 (the Samtec connector) are routed to two headers denoted as JP1A
and JP1B. JP1A pins are numbered 1-40. JP1B pins are numbered 41-80. This is to map them
to the single Samtec connector.
BRK6110 XEM6010
JP1A-1 JP2-1
JP1A-2 JP2-2
JP1A-3 JP2-3
JP1A-4 JP2-4
... ...
JP1B-78 JP2-78
JP1B-79 JP2-79
JP1B-80 JP2-80
BRK6110 XEM6010
JP2A-1 JP3-1
JP2A-2 JP3-2
JP2A-3 JP3-3
JP2A-4 JP3-4
... ...
JP2B-78 JP3-78
JP2B-79 JP3-79
JP2B-80 JP3-80

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Migrating from the XEM3010 to the XEM6010
The XEM6010 was designed to be as compatible as possible with our XEM3010 in order to facili-
tate customer design migration with minimal changes. The physical dimentions and connector
footprints are identical. The differences between these two products are highlighted below.
Four I/O Banks → Two I/O Banks
The Spartan-3 device used on the XEM3010 has eight I/O banks, four of which are routed to
the expansion connectors. Each of these four has selectable I/O bank voltages. The Spartan-6
device on the XEM6010 only has four total I/O banks, two of which are routed to the expansion
connectors. This is a consideration in designs where multiple I/O bank voltages were used.
Note: LVDS output on the Spartan-6 is restricted to banks 0 and 2. LVDS input is available on
all banks. For more information, please refer to the Spartan-6 FPGA SelectIO Resources User
Guide from Xilinx.
32 MiB SDR SDRAM → 128 MiB DDR2 SDRAM
The XEM3010 has 32 MiB of on-board single-data-rate SDRAM. The XEM6010 replaces this
with a faster, higher-capacity 128-MiB double-data-rate SDRAM. The Spartan-6 also has an
internal memory control block (MCB) which provides a DDR2 controller to designs without con-
suming signicant FPGA fabric.
Two Pushbuttons → No Pushbuttons
Due to space constraints, the XEM6010 does not have on-board pushbuttons.
Expansion Connector Differences
The following table lists the expansion connector differences:
XEM3010 XEM6010
JP2-3 is +2.5VDD JP2-3 is a no-connect
JP2-10 is a no-connect JP2-10 is VREF_BANK1
JP2-35 is +VCCO3 JP2-35 is +VCCO1
JP2-55 is +VCCO2 JP2-55 is +VCCO1
JP3-7 is a no-connect JP3-7 is +1.8VDD
JP3-36 is +VCCO6 JP3-36 is +VCCO0
JP3-56 is +VCCO7 JP3-56 is +VCCO0
JTAG Connectivity
The XEM3010 has a header for connecting the Xilinx JTAG Platform Cable. Boards attached
to the XEM3010 expansion connectors see TCK, TMS, TDI as inputs and TDO as an output.
Therefore, from the perspective of the attached board, the XEM3010 is the JTAG controller.
The XEM6010 does not have a header for the Xilinx Platform Cable. This role has been migrated
to the BRK6110 or other attached board. Boards attached to the XEM6010 provide TCK, TMS,
TDI as outputs to the XEM6010 and receive TDO as an input from the XEM6010. Therefore,
from the perspective of the attached board, the XEM6010 is a JTAG device.

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Migrating from the XEM3050 to the XEM6010
The XEM6010 was designed to be as compatible as possible with our XEM3010 in order to
facilitate customer design migration with minimal changes. As a result, the XEM6010 is also
positioned to replace the XEM3050 in many applications. Depending on logic requirements, the
XEM6010-LX45 or XEM6010-LX150 could replace the XEM3050.
Four I/O Banks → Two I/O Banks
The Spartan-3 device used on the XEM3050 has eight I/O banks, four of which are routed to
the expansion connectors. Each of these four has selectable I/O bank voltages. The Spartan-6
device on the XEM6010 only has four total I/O banks, two of which are routed to the expansion
connectors. This is a consideration in designs where multiple I/O bank voltages were used.
Note: LVDS output on the Spartan-6 is restricted to banks 0 and 2. LVDS input is available on
all banks. For more information, please refer to the Spartan-6 FPGA SelectIO Resources User
Guide from Xilinx.
64 MiB SDR SDRAM → 128 MiB DDR2 SDRAM
The XEM3050 has 64 MiB of on-board single-data-rate SDRAM available as two 32 MiB de-
vices. The XEM6010 replaces this with a faster, higher-capacity 128-MiB double-data-rate
SDRAM. The Spartan-6 also has an internal memory control block (MCB) which provides a
DDR2 controller to designs without consuming signicant FPGA fabric.
Synchronous SRAM Removed
The XEM6010 does not have the 9 MiB synchronous SRAM that is on the XEM3050.
Expansion Connector Differences
The following table lists the expansion connector differences:
XEM3050 XEM6010
JP2-3 is +2.5VDD JP2-3 is a no-connect
JP2-10 is a no-connect JP2-10 is VREF_BANK1
JP2-35 is +VCCO3 JP2-35 is +VCCO1
JP2-55 is +VCCO2 JP2-55 is +VCCO1
JP3-7 is a no-connect JP3-7 is +1.8VDD
JP3-36 is +VCCO6 JP3-36 is +VCCO0
JP3-56 is +VCCO7 JP3-56 is +VCCO0
JTAG Connectivity
The XEM3050 has a header for connecting the Xilinx JTAG Platform Cable. Boards attached
to the XEM3050 expansion connectors see TCK, TMS, TDI as inputs and TDO as an output.
Therefore, from the perspective of the attached board, the XEM3050 is the JTAG controller.
The XEM6010 does not have a header for the Xilinx Platform Cable. This role has been migrated
to the BRK6110 or other attached board. Boards attached to the XEM6010 provide TCK, TMS,
TDI as outputs to the XEM6010 and receive TDO as an input from the XEM6010. Therefore,
from the perspective of the attached board, the XEM6010 is a JTAG device.

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2.50
0
3.00
31.43 67.56 72.00 13.00 75.00
0 9.99 16.69
0
12.90
24.90
30.00
39.00
47.00
50.00
3.00
2.33
42.33
8.75
11.75
0
25.50 72.00 75.00 78.87
0
5.00
45.00
50.00
6.50
0
1.57
8.10
12.60
All dimensions in mm
XEM6010 Mechanical Drawing