Opal Kelly XEM6010 User manual

Opal Kelly
A compact (75mm x 50mm) integration board featuring
the Xilinx Spartan-6 FPGA, High-Speed USB 2.0, and
on-board DDR2 memory.
XEM6010 User’s Manual
The XEM6010 is a compact USB 2.0 FPGA integration module featuring the Xilinx Spartan-6 FPGA, 1
Gb (64 Mx16-bit) DDR2 SDRAM, high-efciency switching power supplies, and two high-density 0.8-mm
expansion connectors. The high-speed USB 2.0 interface provides fast conguration downloads and
PC-FPGA communication as well as easy access with our popular FrontPanel application and SDK. A
exible, multiple-output PLL is also provided on-board..

Software, documentation, samples, and related materials are
Copyright © 2010-2012 Opal Kelly Incorporated.
Opal Kelly Incorporated
Portland, Oregon
http://www.opalkelly.com
All rights reserved. Unauthorized duplication, in whole or part, of this document by any means except for brief
excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated.
Opal Kelly, the Opal Kelly Logo, and FrontPanel are trademarks of Opal Kelly Incorporated.
Linux is a registered trademark of Linus Torvalds. Microsoft and Windows are both registered trademarks of
Microsoft Corporation. All other trademarks referenced herein are the property of their respective owners and no
trademark rights to the same are claimed.
Revision History:
Date Description
20110301 Initial release.
20110317 Minor updates.
20110406 Added note and reference regarding LVDS output restriction for Spartan-6.
20110818 Fix minor typo in pinout table. L59N_1 changed to L49N_1
20110926 Added sections on MUXSEL and I2C_SCL / I2C_SDA treatment.
20120216 Added another table to the BRK6110 connections section.

Contents
Introducing the XEM6010 ......................5
PCB Footprint .....................................5
BRK6110 Breakout Board.........................5
Functional Block Diagram............................6
FPGA ...........................................6
Power Supply .....................................6
DC Power Connector ............................7
High-Speed USB 2.0 Interface ........................7
On-board Peripherals ...............................7
Cypress CY22393 PLL...........................7
128-MByte Word-Wide DDR2 Synchronous DRAM . . . . 7
SerialFlashMemory ............................7
LEDs.........................................7
ExpansionConnectors..............................7
FrontPanel Support.................................8
Programmer’s Interface ..........................8
ApplyingtheXEM6010 ........................9
Powering the XEM6010 .............................9
Power Budget ..................................9
Example XEM6010-LX150 FPGA Power Consumption. . 10
Supply Heat Dissipation (IMPORTANT!!).............10
Host Interface .....................................11
MUXSEL......................................11
I2CConnections................................11
SPI Flash ........................................11
FlashLoader Sample ............................12
LEDs ............................................12
DDR2SDRAM....................................12
Clock Conguration (Source Synchronous) ...........13
Memory Controller Blocks ........................13
MIG Settings...................................13
JTAG ............................................14
ExpansionConnectors..............................14
JP2 ..........................................14
JP3 ..........................................14
Setting I/O Voltages .............................15
Considerations for Differential Signals...............15
BRK6110 Breakout Board ............................16
Migrating from the XEM3010 to the XEM6010 ............17
Four I/O Banks → Two I/O Banks. . . . . . . . . . . . . . . . . . . 17
32 MiB SDR SDRAM → 128 MiB DDR2 SDRAM ......17
Two Pushbuttons → No Pushbuttons................17
Expansion Connector Differences ..................17
JTAGConnectivity..............................17
Migrating from the XEM3050 to the XEM6010 ............18
Four I/O Banks → Two I/O Banks. . . . . . . . . . . . . . . . . . . 18

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64 MiB SDR SDRAM → 128 MiB DDR2 SDRAM ......18
Synchronous SRAM Removed . . . . . . . . . . . . . . . . . . . . 18
Expansion Connector Differences ..................18
JTAGConnectivity..............................18
XEM6010 Mechanical Drawing ..................20
BRK6110 Mechanical Drawing...................21
XEM6010 Quick Reference ..................... 22
XEM6010 Quick Reference ..................... 23

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The XEM6010 is a compact FPGA board featuring the Xilinx Spartan-6 FPGA and high-speed
USB 2.0 connectivity. Designed as a full-featured integration system, the XEM6010 provides ac-
cess to over 110 I/O pins on its 484-pin Spartan-6 device and has a 128-MiByte DDR2 SDRAM
available to the FPGA. The XEM6010 is designed for medium-sized FPGA designs with a wide
variety of external interface requirements.
PCB Footprint
A mechanical drawing of the XEM6010 is shown at the end of this manual. The PCB is 75mm
x 50mm with four mounting holes (M2 metric screws) spaced as shown in the gure. These
mounting holes are electrically isolated from all signals on the XEM6010. The two connectors
(USB and DC power) overhang the PCB by approximately 4mm in order to accommodate mount-
ing within an enclosure.
The XEM6010 has two high-density 80-pin connectors on the bottom side which provide access
to many FPGA pins, power, and JTAG.
BRK6110 Breakout Board
A simple breakout board (the BRK6110) is provided as an optional accessory to the XEM6010.
This breakout board provides DC power and easy access to the high-density connectors on the
XEM6010 by routing them to lower-density 2mm-spaced thru-holes. The breakout board also
provides a convenient reference for building boards that will mate to the XEM6010.
Opal Kelly reserves the right to change the form-factor and possibly pinout of the BRK6110.
Therefore, unlike the XEM6010, it is not intended or recommended for production integration.
Introducing the XEM6010

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Full schematics and Gerber artwork les for the BRK6110 are provided free of charge. If your
application depends on the existing form-factor, you may reproduce this board from these docu-
ments.
A mechanical drawing of the BRK6110 is also shown at the end of this document.
Functional Block Diagram
USB Micro
(CY68013A)
Spartan-6 FPGA
XC6SLX45-2FGG484
or
XC6SLX150-2FGG484
Samtec Expansion Connector
Samtec Expansion Connector
PLL
(CY22393)
Host Interface
Bus
60 I/O60 I/O
3 PLL CLKs
USB 2.0
8 LEDs
DDR2 SDRAM
128 MiB
Flash
32 Mib
1 PLL CLK
1 PLL CLK
FPGA
The XEM6010 is offered in two variants. These two variants are identical except for the FPGA
provided. The table below lists some of the differences between the two devices. Please consult
the Xilinx documentation for a more thorough comparison.
Feature XEM6010-LX45 XEM6010-LX150
FPGA XC6SLX45-2FGG484C XC6SLX150-2FGG484C
Slice Count 6,822 23,038
D Flip-Flops 54,576 184,304
Distributed RAM 401 Kib 1,355 Kib
Block RAM 2,088 Kib 4,824 Kib
DSP Slices 58 180
Clock Management Tiles 4 6
Power Supply
The XEM6010 is designed to be operated from a 5-volt power source supplied through the DC
power jack on the device or the expansion connectors on the bottom of the device. This provides
power for the three high-efciency switching regulators on-board to provide 3.3v, 1.8v and 1.2v.
0.9v is derived from the 3.3-volt supply using a small low-dropout (LDO) regulator for use as a
DDR2 termination voltage. Each of the three switching regulators can provide up to 2A of cur-
rent.

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DC Power Connector
The DC power connector on the XEM6010 is part number PJ-102AH from CUI, Inc. It is a stan-
dard “canon-style” 2.1mm / 5.5mm jack. The outer ring is connected to DGND. The center pin is
connected to +VDC.
High-Speed USB 2.0 Interface
The XEM6010 uses a Cypress CY7C68013A FX2LP USB microcontroller to make the XEM a
USB 2.0 peripheral. As a USB peripheral, the XEM is instantly recognized as a plug and play
peripheral on millions of PCs. More importantly, FPGA downloads to the XEM happen blazingly
fast, virtual instruments under FrontPanel update quickly, and data transfers are much faster than
the parallel port interfaces common on many FPGA experimentation boards.
On-board Peripherals
The XEM6010 is designed to compactly support a large number of applications with a small num-
ber of on-board peripherals. These peripherals are listed below.
Cypress CY22393 PLL
A multi-output, triple-PLL clock generator can provide up to ve clocks, three to the FPGA and
another two to the expansion connectors JP2 and JP3. The PLL is driven by a 48-MHz signal
output from the USB microcontroller. The PLL can output clocks up to 150-MHz and is congured
through the FrontPanel software interface or the FrontPanel API.
128-MByte Word-Wide DDR2 Synchronous DRAM
The XEM also includes a 128-MiByte DDR2 SDRAM with a full 16-bit word-wide interface to the
FPGA. This SDRAM is attached exclusively to the FPGA and does not share any pins with the
expansion connector. The maximum clock rate of the SDRAM is 333 MHz. With the -2 speed
grade of the Spartan-6, the maximum clock rate is 312.5 MHz for a supported peak memory
bandwidth of 10 Gb/s.
The DDR2 SDRAM is a Micron MT47H64M16HR-3:G (or compatible).
Serial Flash Memory
A 32 Mib serial ash device (Numonyx M25P32-VME6G or equivalent) provides on-board con-
guration memory for the FPGA as well as general non-volatile storage for your design.
LEDs
Eight LEDs and are available for general use as debug outputs.
Expansion Connectors
Two high-density, 80-pin expansion connectors are available on the bottom-side of the XEM6010
PCB. These expansion connectors provide user access to several power rails on the XEM6010,
the JTAG interface on the FPGA, and 124 non-shared I/O pins on the FPGA, including several
GCLK inputs.
The connectors on the XEM6010 are Samtec part number: BSE-040-01-F-D-A. The table below
lists the appropriate Samtec mating connectors along with the total mated height.

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Samtec Part Number Mated Height
BTE-040-01-F-D-A 5.00mm (0.197”)
BTE-040-02-F-D-A 8.00mm (0.315”)
BTE-040-03-F-D-A 11.00mm (0.433”)
BTE-040-04-F-D-A 16.10mm (0.634”)
BTE-040-05-F-D-A 19.10mm (0.752”)
FrontPanel Support
The XEM6010 is fully supported by Opal Kelly’s FrontPanel Application. FrontPanel augments
the limited peripheral support with a host of PC-based virtual instruments such as LEDs, hex
displays, pushbuttons, toggle buttons, and so on. Essentially, this makes your PC a recongu-
rable I/O board and adds tremendous value to the XEM6010 as an experimentation or prototyp-
ing system.
Programmer’s Interface
In addition to complete support within FrontPanel, the XEM6010 is also fully supported by the
FrontPanel SDK, a powerful C++ class library available to Windows, Mac OS X, and Linux pro-
grammers allowing you to easily interface your own software to the XEM.
In addition to the C++ library, wrappers have been written for C#, Java, and Python making the
API available under those languages as well. Sample wrappers are also provided for Matlab and
LabVIEW.
Complete documentation and several sample programs are installed with FrontPanel.

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Applying the XEM6010
Powering the XEM6010
The XEM6010 requires that this supply be clean, ltered, and within the range of 4.5v to 5.5v.
This supply must be delivered through the +VDC pins on the two device’s two expansion connec-
tors or the DC power connector..
The expansion bus has several power supply pins, described below:
• +VDC is provided by an external device to the XEM6010. It must be a clean, filtered sup-
ply within the range of +4.5 volts and +5.5 volts.
• +3.3v is the output of a 2-Amp switching regulator on the XEM6010.
• +1.8v is the output of a 2-Amp switching regulator on the XEM6010.
• +1.2v is the output of a 2-Amp switching regulator on the XEM6010.
• +VCCO0 is the bank-0 I/O voltage to the FPGA. Factory default is +3.3v
• +VCCO1 is the bank-1 I/O voltage to the FPGA. Factory default is +3.3v
Power Budget
The table below can help you determine your power budget for each supply rail on the XEM6010.
All values are highly dependent on the application, speed, usage, and so on. Entries we have
made are based on typical values presented in component datasheets or approximations based
on Xilinx power estimator results. Shaded boxes represent unconnected rails to a particular
component. Empty boxes represent data that the user must provide based on power estimates.
The user may also need to adjust parameters we have already estimated (such as FPGA Vc c o
values) where appropriate.

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Component(s) 1.2v 1.8v 3.3v
USB 2.0, PLL 320 mW
DDR2 600 mW 250 mW
FPGA Vc c i n t
FPGA Vc c a u x 250 mW
FPGA Vc c o 3(DDR2), est. 250 mW
FPGA Vc c o 2(USB), est. 250 mW
FPGA Vc c o 0,1
Total:
Available: 2,400 mW 3,600 mW 6,600 mW
Example XEM6010-LX150 FPGA Power Consumption
XPower Estimator version 12.3 was used to compute the following power estimates for the Vc-
c i n t supply. These are simply estimates; your design requirements may vary considerably. The
numbers below indicate approximately 70% to 80% utilization.
Component Parameters Vc c i n t
Clock 150 MHz GCLK - 70,000 fanout 384 mW
Clock 100 MHz GCLK - 70,000 fanout 256 mW
Logic (DFF) 150 MHz, 70,000 DFFs 380 mW
Logic (DFF) 100 MHz, 70,000 DFFs232 mW
Logic (LUT) 150 MHz, 32,000 Combinatorial, 1,000 SR, 1,000 RAM 287 mW
Logic (LUT) 100 MHz, 32,000 Combinatorial, 1,000 SR, 1,000 RAM 191 mW
BRAM 18-bit, 100 @ 150 MHz, 100 @ 100 MHz 237 mW
DSP 150 MHz, 140 slices 78 mW
MCB 150 MHz 85 mW
Misc. DCM, PLL, etc. 100 mW
Total: 2,230 mW
Available: 2,400 mW
Supply Heat Dissipation (IMPORTANT!!)
Due to the limited area available on the small form-factor of the XEM6010 and the density of logic
provided, heat dissipation may be a concern. This depends entirely on the end application and
cannot be predicted in advance by Opal Kelly. Heat sinks may be required on any of the devices
on the XEM6010. Of primary focus should be the FPGA (U10) and SDRAM (U11). Although the
switching supplies are high-efciency, they are very compact and consume a small amount of
PCB area for the current they can provide.
If you plan to put the XEM6010 in an enclosure, be sure to consider heat dissipation in your
design.