
ChromaCast 82C205
®
915-2000-084
Revision 1.0 Page v
Allocating the DRAM space to each buffer..................................................................................................29
VGA Frame Buffer.......................................................................................................................................30
TV Frame Buffers ........................................................................................................................................30
OSD Buffer ..................................................................................................................................................31
Display Read Out from Frame Buffers ........................................................................................................31
CPU Scratch RAM.......................................................................................................................................32
TESTING AND DEBUGGING..................................................................................................................................33
INTERNAL TEST PATTERNS ...................................................................................................................................33
SOFTWARE RESETS AND DISABLES.......................................................................................................................33
REVISION NUMBER...............................................................................................................................................34
FIFO STATUS ......................................................................................................................................................34
SIGNATURE ANALYZERS .......................................................................................................................................34
CPU MEMORY READ BUFFER...............................................................................................................................34
MEMORY SUBSYSTEM STATUS..............................................................................................................................35
MISCELLANEOUS..................................................................................................................................................35
TV MODE SETUP ....................................................................................................................................................37
SELECTING BETWEEN 8-BIT AND 16-BIT TV DECODER INTERFACE ...........................................................................37
DETERMINING IF TV PHASE IS CORRECT ...............................................................................................................37
REQUIRED SYNCHRONIZATION SIGNALS FROM THE TV DECODER............................................................................37
ENABLING TV MODE.............................................................................................................................................37
PROGRAMMING THE CRTC FOR TV MODE............................................................................................................38
PROGRAMMING THE SCALERS FOR TV MODE ........................................................................................................38
IP CONVERSION...................................................................................................................................................38
Bob Mode ....................................................................................................................................................38
CPU INTERFACE.....................................................................................................................................................41
CPU ACCESS TO THE REGISTERS.........................................................................................................................41
CPU ACCESS TO THE DRAM BUFFER ..................................................................................................................41
INTERRUPTS.........................................................................................................................................................42
Enabling an event to generate an interrupt.................................................................................................42
The interrupt/event status register...............................................................................................................42
Clearing an interrupt/event..........................................................................................................................43
POWER MANAGEMENT FOR CHROMACAST 82C205 .......................................................................................45
TIMER..................................................................................................................................................................45
Setting the timer interval..............................................................................................................................45