ORTEC 2126 User manual

11
M
P
i
3
I
i
Model 2126
Constant Fraction Discriminator
User's Manual
9231701A 8/93
ISO 9001
m
M

]
J
J
J
J
J
]
]
3
Table of Contents
]
3
3
3
3
J
"i
J
Page
1. INTRODUCTION i
2. CONTROLS, CONNECTORS AND INDICATORS
2.1 Front Panel 2
3. SETUP INFORMATION
3.1 Attenuator Module 3
3.2 Fraction Module 3
3.3 Count Rate Range 3
3.4 Operating Mode 3
3.5 Output Width Range 6
3.6 Standard/Alternate Power Supplies 6
3.7 Standard Setup 6
4. OPERATION
4.1 Power Supply 6
4.2 Input Signals 6
4.3 Operating Mode 6
4.4 Delay Cable 7
4.5 Walk Trim 7
4.6 Threshold Adjustment 7
4.7 Outputs and Width Control 7
5. CIRCUIT DESCRIPTION
5.1 Power Supply 9
5.2 Constant Fraction and Threshold Circuits 9
APPENDIX A
SPECIFICATIONS
A.I Inputs
A.2 Outputs
A.3 Controls - Front Panel
A.4 Controls - Internal
A.5 Performance
A.6 Typical Cable Lengths
A.7 Power Requirements . ,
A.8 Physical
FIGURE LISTING
Figure 2.1 Front Panel
Figure 3.1
Internal Controls
Figure 3.2 Options for Attenuator Module
Figure 3.3 Constant Fraction Module
. 5
Figure 3.4
Leading Edge Module
Figure 4.1
Typical Input Signal
Figure 4.2 Walk Inspect Wave Form Using Plastic Detectors ..
. 8
Figure 4.3 Walk Inspect Wave Form for Slow Detectors
. 8
Figure 4.4 Typical Negative Output Pulses
8
Figure 5.1 Timing Signals
. 10

]
]
Section 1.
Introduction
I
I
The Model 2126 is a 200 MHz Constant Fraction Discrimi
nator in a single width NIM. it has independent controls for
threshold, walk, output pulse width, and operating mode,
and provides maximum flexibility for use in any timing
application.
The 2126 is fully dc coupled and provides two count rate
operating ranges for use over a wide range of input count
rates. In the standard count rate range, the 2126 operates
to 150 MHz with the front panel potentiometer controlling
both the output width and the internal dead time. Alterna
tively, a special high count rate range can be selected
which provides operation to 200 MHz (typically 250 MHz)
with fixed output width and deadtime.
The 50 ohm input of the 2126 accepts negative pulses with
amplitudes up to -5 V. Input protection is provided for
inputs outside the expected range. An internal jumper can
connect a X2 attenuator to the input to extend the input
range to -10 V. Three operating modes are provided. In
addition to its normal Constant Fraction (CF) timing mode,
the 2126 provides a Constant Fraction with Slow Risetime
Reject (SR) timing mode and a Leading Edge (LE) mode. A
fraction module is provided and set for 0.4; it can easily be
changed to another fraction, if desired. An alternate plug-
in module allows Leading Edge operation.
Two independent fast negative-timing outputs and two
independent positive-timing outputs are provided. This
provides maximum flexibility for most timing applications.
In addition, an LED is provided to indicate the presence of
input signals.
The 2126 can operate from NIM bins with the standard
± 12 V and ± 24 V power supplies. If a± 6 V power supply is
available, the 2126 can be configured to use that supply for
much of its power requirements.
I
1
I
]
1
]
1
"i
J

Section 2.
Controls, Connectors and Indicators
2.1 FRONT PANEL
THRESHOLD CONTROL
selects threshold for sig
nal acceptance from
-5 mV to -1 V.
INPUT accepts -5 mV to
-5 V linear pulses
(-10 mV to-10 V with X2
attenuator in place).
Zin = 50n.
OUTPUT LED indicates
2126 is processing
pulses
WALK ADJUST CON
TROL varies relative zero
cross timing to provide
minimum time walk
- OUTPUTS - Two inde
pendent outputs provide
-16 mA into 50 O ioads.
-t- OUTPUTS - Two inde
pendent outputs provide
-I- 5 V nominal into high
impedance loads
COHSTA
PISCRIHMATOR
® 2126 ®
IWESHDU)
INPUT
ADJUST INSPECT
OUTPUTS
MODE SWITCH deter
mines timing mode. SR =
Slow Reject, OF = Con
stant Fraction, LE =
Leading Edge
WALK INSPECT OUT
PUT displays output of
Constant Fraction com
parator. Attenuated ECL
leveis, -85 mV and
-190 mV.
DELAY CONNECTORS
accept external delay
cables. Cable length
determines delay.
WIDTH CONTROL varies
width of outputs and sets
channel dead time in NO
(Normal) range. Disabled
in HR (High Rate) range.
Figure 2.1
Front Panel

Section 3.
Setup Information
This section describes the function of the various jumpers
and modules mounted on the printed circuit board of the
2126. Any adjustments should be made prior to installing
the 2126 in a NIM bin or connecting the 2126 to a power
source. Remove the left cover of the 2126 to expose the
circuit board.
3.1 ATTENUATOR MODULE
The 2126 is provided with an input attenuator module. This
module provides the choice of no attenuation or X2 atten
uation of the input signal. The input range of the 2126 is
-5 mV to -5 v. If the peak input signal is expected to be -5 V
or less, no attenuation should be selected. For applications
where the peak input signal is between -5 V and -10 V, the
X2 attentuation should be selected. The attenuator module
is a small assembly containing two resistors and a short
jumper wire mounted near the front of the 2126 (Figure
3.1). The attenuation factor can be changed by removing
the module from the socket, rotating it 180 degrees, and
replacing it in the socket. See Figure 3.2 which illustrates
the two choices of attenuation provided by the attenuator
module. The attenuator module is shipped from the factory
in the no attenuation position.
3.2 FRACTION MODULE
In timing experiments, one of the important variables to
consider is the fraction of the input signal used to derive
the constant fraction function. Most applications provide
optimum timing with a fraction of 0.4. This fraction is pro
vided by the 2126. However, the 2126 offers the user an
easy means to change the fraction. The fraction module is
located immediately below the attenuator module near the
front of the 2126. The user can change the desi red fraction
in two ways. Figure 3.3 illustrates the fraction module and
lists values for two resistors that can be changed by the
user to implement different values for the fraction. Alter
nately, contact the factory regarding other values of frac
tion modules available on special order.
3.3 COUNT RATE RANGE (NOrmal/HIgh Rate)
Two count rate ranges are provided on the 2126. The user
can select the desired count rate range by moving a jumper
mounted on the circuit board. NOrmal range (NO) is
intended for most uses of the 2126. It provides for count
rates up to 150 MHz. In the NOrmal range, the front panel
WIDTH potentiometer controls the width of the negative
and positive timing outputs and the internal deadtime of
the 2126.
In certain extremely high rate applications, the user should
select the High Rate range (HR). This range provides for
usable count rates of greater than 200 MHz. However,
certain precautions should be observed in using the HR
range of the 2126. In this range, the front panel WIDTH
potentiometer is inactive. The width of the negative timing
outputs and the internal deadtime of the 2126 channel are
internally set at approximately 2 ns. The input signal
should be approxirnately 2 ns in width and show a clean
return to the baseline in order to fully utilize the speed of
the HR mode of the 2126.
In addition, the user should verify that companion NIM
modules used with the 2126 in its HR range are capable of
accepting negative NIM inputs of 2 ns width. The NO/HR
jumper is located just to the right of A2 on the 2126. See
Figure 3.1. NO is the upper position of the jumper. HR is the
lower position of the jumper. The 2126 is shipped in the NO
position.
3.4 OPERATING MODE (Constant Fraction/Slow Reject/
Leading Edge)
The 2126 provides three operating modes: Constant Frac
tion (OF), Constant Fraction with Slow Reject (SR), and
Leading Edge (LE). See Section 4.3 for a description of
these operating modes.
3.4.1 The Constant Fraction Mode
The Constant Fraction (CF) mode is intended for use with
detectors such as fast plastic detectors which exhibit fast
rise time outputs with little risetime variation. The Constant
Fraction with Slow Risetime (SR) mode is often used with
Germanium detectors which exhibit a wide range of rise
time variation. The Leading Edge mode is used with detec
tors which provide fast outputs with little amplitude or
risetime variation.
3.4.2 Constant Fraction and Constant Fraction with Slow
Reject Modes
Both Constant Fraction (CF) and Constant Fraction with
Slow Reject (SR) modes use the internal fraction module
supplied with the 2126. To use either mode, verify that the
fraction module is properly installed in its socket near the
front of the 2126 circuit board. Figure 3.3 shows the proper
installation of the fraction module. With the fraction module
installed, the front panel Mode Switch allows selection of
Constant Fraction (CF) mode or Constant Fraction with
Slow Reject (SR).
3.4.3 Leading Edge Mode
To select the Leading Edge Mode, the user should remove
the fraction module from its socket near the front of the
board and replace it with the Leading Edge module. A
socket is provided near the bottom of the circuit board to
hold the unused module. The front panel Mode Switch
should be set to Leading Edge (LE) to use the Leading
Edge mode. Figure 3.4 shows the proper installation of the
Leading Edge module. Table 3.1 summarizes the module
and switch settings for the three operating modes.

Figure 3.1 shows the Internal layout of the 2126. The func
tion of the internal controls and their normal configuration
is illustrated.
Table 3.1
Operating Mode Summary
Operating
Mode
Constant Fraction
Constant Fraction
with Slow Reject
Leading Edge
Module
Fraction
Fraction
Leading Edge
Front Panel
Switch
CF
SR
LE
PC Board
Attenuator Module
NOrmal or High Hate
Jumper Plug
HR «
Fraction Module
tgcn
X5 X1
Input power selection
Jumper Plug
A = ±12 V operation
8 = ± 6 V operation
E
Leading Edge
Module in spare
position
Output Width Range
Jumper Plug
Figure 3.1
internal Controls

}
J
J
J
JP1
JP1
<Z3>-
-CII>
5in Kl
loofi K)
0 0
0 0
(R5)
(R6)
PIN1
P.C. BOARD
TOP
JP2
-CID-
H h
H h
-cn>-
0-
0
(KiooQj4^
(KEEl
. (R5)
'(R6)
• P.C. BOARD
SIDE
P1N1
RN1
P.C. BOARD
TOP
JP2
(a.) NO ATTENUATION
(b.) X 2 ATTENUATION
- P.C. BOARD
EDGE
FRONT_
PANEL
I
Figure 3.2
Options for Attenuator Module
JP1
icon HI
MMi20o|^
P.C. BOARD
• P.C. BOARD
SIDE
f,
R7 a 51fi
R8 a 5in
R9 = 50a/f
Rl0 = 50Q«f
± ^ ElO
.1 510 4.7
.2 240 10
.4 120 20
a.) STANDARD MODULE
(f = .4) INSTALLED
b.) R9& RIO VALUES FOR
ALTERNATE FRACTIONS
Figure 3.3
Constant Fraction Module, Including Resistor
Values for Field Changes
JP1
j
]
P.C. BOARD
TOP
0 0
0 0
-r-D-
0 0
H f-
0 0
P1N1
H H
T
1
oJ
l
0
0
A
fr TsiHTn
PIN1
JP2
LEADING EDGE MODULE
IN JP2 POSITION
n-TTrnmHl
0-CSE3-0
OCMDO
(KIBZEH)
PIN1
FRACTION MODULE IN
SPARE POSITION
P.C. BOARD
.EDGE
/
Figure 3.4
Leading Edge Module

3.5 OUTPUT WIDTH RANGE (X1/X5)
Two ranges of adjustment are provided for tfie front panel
WIDTH potentiometer. Since the WIDTH potentiometer
controls the output widths as well as the internal deadtime
of the 2126, the proper range for the WIDTH adjustment
should be selected. Use XI for fast plastic detectors and
most sodium iodide detectors. Detectors that provide input
signals of 100 ns width or greater, or that cause baseline
perterbations extending longerthan 100 ns, should use the
X5 range. The X1/X5 jumper is located below A2. See
Figure 2.2. XI is to the right and X5 is to the left. The X1/X5
jumper is shipped in the XI position.
3.6 STANDARD/ALTERNATE POWER SUPPLIES
The 2126 can operate from Nlf^ bins equipped with the
standard ± 12V and + 24 V power supplies as well as those
with the optional ± 6 V power supply. Since the 2126 draws
current is excess of the single-width NIfvl module limit
when connected to a ±12 V supply, operation of the 2126
from ± 6 V will reduce the current drawn to within the
single-width module limits. If a ± 6 V power supply is
available, set the input power jumpers to the 6 V position,
otherwise use the 12 V position. See Figure 3.1. The 6 V
position for both jumpers is towards the bottom of the
module and is labeled "B". The 12V position is towards the
top of the module and is labeled "A".
3.7 STANDARD SETUP
The following can be considered a standard setup and is
shipped from the factory in this configuration:
Attenuator module
Fraction module
Timing range
Operating mode
Output width range
Power supply
XI (no attenuation)
Constant Fraction, f = 0.4
NO (NOrmal)
OF (Constant Fraction)
XI (2-100 ns)
±12V
Section 4.
Operation
4.1 POWER SUPPLY
The 2126 is intended to be operated in a NIM bin equipped
with a power supply providing ± 12 V and ± 24 V. Alter
nately, a N11^ bin providing ± 12 V.± 24 V and± 6 V can be
used. See Section 3.6. For lab bench testing, a NIM power
supply extension cable may be used. However, excessive
voltage drops in the extension cable may be encountered
due to the relatively high current requirements of the 2126.
For use in experiments, secure installation in a NIM bin is
recommended. The NIM bin power supply should be off
when the 2126 orother NIM are installed or removed from
the NIM bin.
4.2 INPUT SIGNALS
Typical input signals to the 2126 are generated by scintilla
tion detectors utilizing photomultiplier tubes or solid state
detectors with a charge sensitive preamp and timing filter
amplifier. Such signals are negative, going from a baseline
of ground. Rise times can vary from 1 ns to greater than 100
ns, and widths from 1 ns to greater than 500 ns. For labora
tory test bench, a logic pulser can be used as an input to the
2126. See Figure4.1 foratypical inputsignal produced bya
logic pulser.
4.3 OPERATING MODE
Selection of operating mode depends on the requirements
of the given experiment. Some general compromises
worth considering are discussed in the following
paragraphs.
4.3.1 Constant Fraction (OF) Mode
In the Constant Fraction (OF) mode, timing is derived from
a comparison between a fixed ratio (40% in the 2126) and
the peak amplitude of each successive pulse. This instan
taneous self-reference yields a time mark that is theoreti
cally independent of the pulse height, as contrasted to the
behavior of the leading edge mode. In the 2126, the ratio
reference signal is taken internally, and the full amplitude
pulse is delayed for the comparison by an external cable
connected between the two front panel DELAY connectors.
When the length of this external cable is chosen to gener
ate a time delay less than the rise time of the input pulse,
the resulting time mark is stabilized for both amplitude and
rise time variations of that pulse. This is the basis for ARC
(Amplitude and Rise time Compensated) timing. The com
promise in Constant Fraction (and,also ARC) timing is the
ability to provide proper delays for the rise time of the input
pulse considering either rate and pile-up effects or the
distortions introduced by varying wavefront shapes due to
charge collection deficit, ballistic effects, or trapping
effects in the detector. It is these accommodations that
lead to empirical determinations of the optimum delay
cable length for a given detector and setup.
4.3.2 Constant Fraction With Slow Reject (SR) Mode
In the Constant Fraction with Slow Rise time reject (SR)
mode, a further accommodation is offered for the longer
rise times of solid state detectors. The timing mark for the
Constant Fraction is derived from the slightly delayed
pulse, with the presumption that the THRESHOLD level
has been set quite low and this level is exceeded prior to the
derivation of the timing mark. In the case of solid state
detectors, where long varying wavefronts of the input pulse
are common, a relatively short delay cable is frequently
used and the above timing premise may not be satisfied. In
that case, the amplitude discriminator keyed to the
THRESHOLD setting may switch late, and the resulting
timing will represent some mix of the intended Constant
Fraction timing with Leading Edge timing. This effect
causes either tailing or a satellite peak in a time spectrum.
In the SR mode, a logic alternation causes rejection of
pulses which do not exceed the THRESHOLD prior to the
derived Constant Fraction timing mark. The result is
enhanced timing resolution due to elimination of the Lead
ing Edge errors, but with some loss of counting efficiency.

J
J
1
]
]
1
4.3.3 Leading Edge (LE) Mode
The Leading Edge mode Is used less often than the two
Constant Fraction modes. It Is typically used for detectors
with fast risetlmes and little amplitude variation. Since the
Constant Fraction function Is disabled when the 2126 Is
used In Leading Edge mode, amplitude and risetlme varia
tion can Introduce timing walk. If the Input signals are all
essentially of the same amplitude and risetlme, the Leading
Edge mode can offer good timing performance.
4.4 DELAY CABLE
The delay cable used to set the Constant Fraction timing
mark should provide a delay less than the known rise time
of the applied input pulse for full compensation of both
amplitude and rise time variations (for a fixed shape). For
fast and moderately fast detector pulses (up to 10 ns rise
time) a delay of nominally 75% of the rise time is most
effective. For solid state detectors, a delay of 40% of the
pulse rise time Is commonly used for the reasons given
above.
The Internal delay of the 2126 is 0.3 ns. and this must be
corrected by picking a suitable cable. For example. If the
detector rise time Is 4 ns. a 3 ns delay would be recom
mended. The external cable length, estimated on the basis
of 4.8 ns per meter for RG-58 cable, would be:
External Delay Total delay - Internal Delay
L =
4.8
3.0 - 0.3 ns
4.8 ns/m
4.8
56.3 cm or about 22 Inches
4.5 WALK TRIM
The adjustment of the amplitude sensitive variation of the
timing mark (time walk) In the Constant Fraction and CFRR
modes remains a less exact procedure. Proper adjustment
is possible only when the do offset present on the Input to
the 2126 Is less than ± 6 mV do. Thus detector leakage or
dark current errors must be minimized before attempting
adjustment.
Laboratory trimming of the unit can be demonstrated by
using a suitable pulse generator with a known fast, clean
wavefront and a delay chosen as discussed above. A very
broadband 50 ohm attenuator such as the Hewlett Packard
HP-3496. or one whose time walk Is very precisely known,
should be used. An externally triggered oscilloscope capa
ble of displaying at least 1 ns/dlvlslon Is also necessary.
Step attenuations should be then yield a stable time posi
tion of the 2126's output signal when starting from a refer
ence -5 V peak pulse Input. Care must be taken that the
pulse generator offset Is small and does not change for
different attenuator settings. The WALK ADJUST trimming
potentiometer can be used to find the best adjustment of
the finite time walk over a narrower amplitude range as
desired.
When the 2126 Is used with the Intended detector, timing
resolution may be trimmed experimentally by successive
measurements In the setup at hand. A qualitative monitor
ing Is available by monitoring the front panel INSPECT
output with an oscilloscope. For fast detectors, the output
should Indicate an attenuated logic low ECL level (approx.
-0.19 V dc. Into500)'where noise just disappears Into this
level and pulses are seen as transitions to logic high ECL
(approx. -0.085 V dc into 50 fi ). Reference Figure 4.2. For
slower detectors, a noise band between the ECL levels may
be seen, with transitions to ECL logic high and low of about
equal intensity. Reference Figure 4.3.
4.6 THRESHOLD ADJUSTMENT
The 2126 threshold adjustment can be used as a lower level
control to select the threshold above which Input pulses
will generate an output signal. A front panel test point Is
provided to allow easy measurement of the selected thre
shold voltage. As a general rule of thumb, select a thre
shold voltage as high as possible while not excluding Input
signals of Interest. Unless experimental conditions dictate
otherwise, do not use minimum settings of the threshold,
since Input signals often show ringing or baseline perter-
batlons which may generate unwanted outputs.
4.7 OUTPUTS AND WIDTH CONTROL
The 2126's negative logic outputs are Intended to drive 50
ohm loads through any reasonable length of suitable 50
ohm coaxial cable (such as RG-58). Figure 4.4 shows the
typical negative output pulse shapes Into 50 ohm loads,
with the WIDTH control set to minimum. For optimum
performance, terminate unused negative outputs In
50 ohms.
Since the WIDTH control also sets the DEAD TIME follow
ing a given pulse In the NOrmal count rate range, the user
should set this control consistent with the pulse rate
requirements of the given experiment. In the minimum
(fully counterclockwise) position of the WIDTH control, a
count rate In excess of 150 MHz can be expected for the
NOrmal mode of the 2126. The WIDTH control of the2126
is Inoperative In the High Rate mode.
The 2126's positive logic outputs are designed to drive
relatively high Impedance loads with logic levels of nomi
nally 0 and -t- 5 V. Since this type of output Is inherently
slower than current mode outputs (the negative outputs),
the positive outputs may not provide proper logic transi
tions at the high count rates the 2126 is capable of.
]
J
]

1
5nS
0.2V i
■v^
Figure 4.1
Typical Input Signal
Produced by a Logic Pulser
Figure 4.2
Walk Inspect Wave Form
Using Plastic Detectors
1
5nS—-
0.2V t
V
Figure 4.3
Walk Inspect Wave Form
for Slow Detectors
Figure 4.4
Typical Negative Output Pulses into
50 ohms Load

Section 5.
Circuit Description
The 2126 is a high performance Constant Fraction Discrim
inator in a single width NlM. lt also includes a power supply
circuit to provide logic power to the unit. This section
describes the operation of both the power supply and the
Constant Fraction Discriminator.
5.1 POWER SUPPLY
The 2126 consists primarily of ECL logic which uses a
supply voltage of -5.2 V. In addition, a TTL supply voltage
of -f 5.0 V is required. Two methods of obtaining these
voltages are provided, selectable by a jumper plug. When
the 2126 is used in a NIM bin with the standard supply
voltages of ± 12 V and ± 24 V, the logic supply voltages of
-5.2 and + 5.0 V are provided by adjustable three-terminal
regulators. Q1 and Q2, together with their associated cir
cuitry, provide stable well-regulated logic voltages. If a
± 6 V NIM power supply is available, the 2126 board-
mounted jumpers can be set to provide the required logic
voltages directly from the ± 6 V supplies. In each case, a
diode (D1 for + 6 V, D2 for -6 V) drops the power supply
voltages to the logic voltages required by the 2126. In either
case, the -2 V ECL pull-down voltage is provided by an
additional three-terminal regulator (Q3), operating from
the -5.2 V logic supply.
5.2 CONSTANT FRACTION AND
THRESHOLD CIRCUITS
The input signal is applied directly to pin 10 of the thresh
old comparator. D1 provides a temperature compensated
voltage which is divided to produce-1 V across the thresh
old potentiometer (RV1). The wiper voltage of RV1, which
varies from -5 mV to -1 V, is applied to pin 10 of the
threshold comparator.
The constant frac'i .Ti 'unction is implemented at the inputs
of the ultrafast comparator A4b. The input attenuator
module is a X2 attenuator that maintains the proper
50 ohm input impedance. It can be rotated to provide no
attenuation (short between the input and pin 5 of the frac
tion module) or X2 attenuation (100 ohms between the
input and pin 5 of the fraction module). The fraction
module serves to attenuate both the prompt and delayed
inputs to the constant fraction comparator (A4b) while
providing the proper 50 ohm input impedance. The prompt
input to A4b (pin 8) is attenuated more than the delayed
input (pin 7) resulting in the fraction f = 0.4. This combina
tion of attenuation and delay provides the following signals
at the inputs of the constant fraction comparator:
pin 8': 0.3 input amplitude, prompt
pin 7: 0.67 input amplitude, delayed by cable selected
See Figure 5.1 which illustrates the signals associated with
the constant fraction and threshold comparators.
Prior to the application of an input signal, the inverting
output of A4b (pin 2) can be in either logic state depending
on the offset voltage applied to A4b pin 8 by the WALK
ADJUST potentiometer. Upon application of an input sig
nal, A4b pin 8 initially is lower than A4b pin 7, driving the
inverting output A4b pin 2 to a logic high. When the
delayed signal arrives at A4b pin 7, it causes this pin to
become more negative than A4b pin 8 which causes the
inverting output (A4b pin 2) to fall to a logic low. The timing
of this low-going sign al is input amplitude independent.
The inverting output of the threshold comparator (A4a pin
15) is normally a logic high. When an input signal is ap
plied, the inverting output of A4a goes to a logic low when
the input signal crosses the selected threshold voltage.
This logic transition occurs ahead of the output from the
constant fraction comparator since the input to the con
stant fraction output is delayed by the front panel delay
cable. Thus, the 10H209 OR/NOR (A3b) gate has a high
input from the threshold comparator and an indeterminant
input from the constant fraction comparator prior to the
application of an input signal. When an input is applied,
A3b pin 7 goes low if the threshold is crossed. Shortly later,
A3b pin 5 goes low due to the constant fraction compara
tor. The inverting output of A3b (pin 3) goes high when the
constant fraction comparator fires if the threshold was
crossed. This logic signal is the clock to the ultra fast
11C70D flip-flop A2.
When the 2126 is used in the Constant Fraction mode, the
D input of A2 (pin 11) is held at a logic low by A3a pin 14.
After the preceding signal was processed, A2 was left in the
SET state with the Q output high and the Qbar output low.
When the clock signal arrives at A2 pin 7 from A3 pin 3, the
D flip-flop is RESET by clocking in the low at A2 pin 11, the
outputs are ac'iv -,d the channel is unable to process
further inputs. A2 is SET via the HR or NO jumper, thus
terminating the outputs and the internal deadtime. In the
NOrmal mode of operation, the Q output of A2 is pulled
down by the current source consisting of Q9 and asso
ciated bias resistors. The line driver/receiver Ala senses
the falling edge of A2 pin 2 and drives the SET input of A2
high, thereby SETting A2 and terminating the output. The
front panel WIDTH potentiometer varies the current source
Q9 and thus varies the rate of fall of A2 pin 2. Thus, the
width of the one-shot formed from A2 is varied. In the High
Rate mode, the current source Q9 and Ala are bypassed.
The rising edge of A2 Qbar is coupled directly to the SET
input of A2. Thus, the propigation delays associated with
A2 determine the output widths and the internal deadtime.

In the Slow Reject mode, the circuit functions virtually the
same. The D input of A2 is driven by A3a pin 14, which now
has a low going logic signal driven by the threshold com
parator through A3a. A slight delay is provided by R14 and
C7. For fast risetime signals, the D input of A2 is low before
the clock drives pin 7 high. However, slow risetime signals
cause the threshold comparator to fire slightly later. For
these slow risetime signals, the falling edge of the signal at
A2 pin 11 arrives after the clock at pin 7 and a high is
clocked into to flip-flop. Since the flip-flop is already SET,
no change occurs at its output and the input signal is
ignored.
In the Leading Edge mode, the Constant Fraction compar
ator (A4b) is disabled in a state that permits the Leading
Edge comparator (A4a) to generate the clock for flip-flop
A2.
The line driver/receiver A1 b is driven by the Qbar output of
A2 and serves to drive the two independent negative out
puts differentially. It also toggles A1 c, the one-shot driving
the front panel LED. The negative output transistors are
conventional differential switches with the collectors driv
ing the 50 ohm outpUts directly.
\
A4pin8 0.5V t
A4pin7 O.svf
A4 pin15 1.0V I
A4pin2 1.0V {
2ns
Figure 5.1
Timing Signals
10

Appendix A.
Specifications
A.1 INPUTS
INPUT - Accepts -5 mV to -5 V (-10 mV to -10 V with
internal X2 attenuator) linear pulses; rise time > 1 ns; Z|n =
50 ohms, dc coupled; front panel BNC connector protected
to ± 100 V (duration limited).
DELAY-Two BNC connectors between which a delay
cable is connected to form the internal constant fraction
signal. Recommended lengths are based upon RG-58
cable propagation delay of=4.8 ns/m to provide a delay of
= 0.2 trise for germanium detectors and = 0.8 tnse for most
other detector types.
A.2 OUTPUTS
WALK INSPECT - Displays output signal of zero crossing
discriminator for use in trimming time walk; Zout=50 ohms.
NEGATIVE OUTPUTS - 2 independent negative current
outputs, each providing -16 mA into 50 ohms, rise time =
1 ns; dc coupled front panel BNC connectors; pulse width
controlled by WIDTH potentiometer in Normal mode; 2 ns
nominal in High Rate mode.
POSITIVE OUTPUTS - 2 independent positive voltage
outputs, each providing 2 V minimum into 50 O, 4 V min
imum into high impedance, rise time 10 ns or less; dc
coupled front panel BNC connectors; pulse width con
trolled by WIDTH potentiometer in Normal mode, unde
fined in High Rate mode.
A.3 CONTROLS - FRONT PANEL
THRESHOLD - Front panel 10-turn potentiomenter to set
acceptance threshold for input pulses; range -5 mV to
-1 V.
WALK ADJUST - Front panel potentiometer to compen
sate walk of the internal zero crossing discriminator.
WIDTH - Front panel 10-turn potentiometer to vary inter
nal deadtime and width of negative outputs in Normal
mode. Range = 2-100 ns or= 10-500 ns as determined by
internal jumper. Inoperative in High Rate mode.
A.4 CONTROLS - INTERNAL
ATTENUATION - Board mounted DIP jumper selects no
attenuation or X2 attenuation of input signal.
FRACTION - Board mounted DIP jumper selects value of
constant fraction; 0.4 standard, other values available by
special order.
TIMING MODE - Board mounted jumper selects Constant
Fraction (CF) or Constant Fraction with Slow Risetime
Reject (SR) timing mode.
OPERATING MODE - Board mounted jumper selects
Normal (NO), or High Rate (HR) operating mode.
OUTPUT WIDTH RANGE - Board mounted jumper se
lects = 2-100 ns (XI) or 10-500 ns (X5) output WIDTH
range.
POWER SUPPLY - Board mounted jumpers select ± 12 V
or ± 6 V as input power for 2126 logic.
A.S PERFORMANCE
DYNAMIC RANGE - 1000;1
WALK - < 100 ps for a 1 ns rise-time pulse over a 100:1
dynamic range (referenced to -5 V) in the CF mode.
COUNTING RATE - Normal mode to 150 MHz, as limited
by deadtime; High Rate mode to 200 MHz.
PULSE PAIR RESOLUTION - Normal mode < 7 ns as
limited by deadtime; High Rate mode < 5 ns.
THRESHOLD STABILITY - Better than ± 0.02%/° C (±200
ppm/°C)
TEMPERATURE RANGE - 0°C to + 50°C
THRESHOLD LINEARITY - ± 0.25% integral
A.6 TYPICAL CABLE LENGTHS (RG-58)
For plastic, Nal, and silicon detectors - 0.3 to 1.0 m (1.0 to
3.3 ft.)
For Planar Ge Detectors - 1.0 to 2.0 m (3.3 to 6.6 ft.)
For Coaxial Ge Detectors - 2.0 to 4.0 m (6.6 to 13 ft.)
A.7 POWER REQUIREMENTS
Power jumpers set to ±12 V:
+12 Vdc — 130 mA
-12Vdc —350 mA*
Power jumpers set to ± 6 V:
+12 Vdc— 20 mA +6 Vdc—130 mA
-12 Vdc —120 mA -6 Vdc —250 mA
* Exceeds the NIM power allotment for a single-width
module.
A.S PHYSICAL
SIZE - Single width NIM module 3.43 X 22.12 cm (1.35X
8.71 in.) perTID-20893 (rev.)
NET WEIGHT - 0.9 kg (2.0 lbs.)
SHIPPING WEIGHT - 1.8 kg (4.0 lbs.)
11