ORTEC 409 User manual

PRECISION
INSTRUMENTATION
FOR RESEARCH
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Oak Ridge
Techiiical Enterprises
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OAK RIDGE, TENNESSEE
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INSTRUCTION MANUAL
MODEL 409
LINEAR GATE
AND SLOW COINCIDENCE

INSTRUCTION MANUAL
MODEL 409
LINEAR GATE
AND SLOW COINCIDENCE
Serial No.
Purchaser
Date Issued
OAK RIDGE TECHNICAL ENTERPRISES CORPORATION
p. O. BOX C
OAK RIDGE, TENNESSEE
Telephone [phone]
TWX 810-572-1078
> Oak Ridge Technical Enterprises Corporation 1966 Printed in U.S.A.

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TABLE OF CONTENTS
1. DESCRIPTION
1.1 General Description
1.2. Description of Basic Function
1.2.1 Linear Gate
1.2.2 Slow Coincidence
2. SPECIFICATIONS
2.1 General
2.2 Linear
2.3 Slow Coincidence
3. INSTALLATION
3.1 General Installation Considerations
3.2 Connection to Power— Nuclear Standard Bin ORTEC Model 401 /402
3.3 Input Signal Connection to Linear Gate
3.4 Logic Inputs to the Slow Coincidence
4. OPERATING INSTRUCTIONS
4.1 Front Panel Controls
4.2 Initial Testing and Observation of Pulse Waveforms
4.3 Connector Data
4.4 Typical Operating Considerations
5. CIRCUIT DESCRIPTION, Linear Gate and Slow Coincidence (Etched Board 409-0201)
5.1 Linear Gate
5.2 Slow Coincidence
6. MAINTENANCE
6.1 Testing Performance of Linear Gate and Slow Coincidence
6.2 Adjustment of Slow Coincidence Output Pulse Width
6.3 Adjustment of Linear Gate Pedestal
6.4 Tabulated Test Point Voltages
6.5 Conversion of Anticoincidence Input D for Coincidence Operation
6.6 Suggestions for Troubleshooting
7. BLOCK DIAGRAMS AND SCHEMATICS
409-0201 A-Bl Model 409 Linear Gate and Slow Coincidence Block Diagram
409-0201 A-Sl Model 409 Linear Gate and Slow Coincidence Schematic
409-01 01 A-Sl Model 409 Chassis Wiring Schematic

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STANDARD WARRANTY FOR ORTEC ELECTRONIC INSTRUMENTS
DAMAGE IN TRANSIT
Shipments should be examined immediately upon receipt for evidence of external or con
cealed damage. The carrier making delivery should be notified immediately of any such damage,
since the carrier is normally liable for damage in shipment. Packing materials, waybills, and other
such documentation should be preserved in order to establish claims. After such notification to the
carrier, notify ORTEC of the circumstances so that we may assist in damage claims and in providing
replacement equipment when necessary.
WARRANTY
ORTEC warrants its electronic products to be free from defects in workmanship and materials,
other than vacuum tubes and semiconductors, for a period of twelve months from date of ship
ment, provided that the equipment has been used in a proper manner and not subjected to abuse.
Repairs or replacement, at ORTEC option, will be made without charge at the ORTEC factory.
Shipping expense wil l be to the account of the customer except in cases of defects discovered upon
initial operation. Warranties of vacuum tubes and semiconductors, as made by their manufacturers,
will be extended to our customers only to the extent of the manufacturers' liability to ORTEC.
Specially selected vacuum tubes or semiconductors cannot be warranted. ORTEC reserves the right
to modify the design of its products without incurring responsibility for modification of previously
manufactured units. Since installation conditions are beyond our control, ORTEC does not assume
any risks or liabilities associated with the methods of installation, or installation results.
QUALITY CONTROL
Before being approved for shipment, each ORTEC instrument must pass a stringent set of
quality control tests designed to expose any flaws in materials or workmanship. Permanent records
of these tests are maintained for use in warranty repair and as a source of statistical information
for design improvements.
REPAIR SERVICE
ORTEC instruments not in warranty may be returned to the factory for repairs or checkout at
modest expense to the customer. Standard procedure requires that returned instruments pass the
same quality control tests as those used for new production instruments. Please contact the factory
for instructions before shipping equipment.

K
ORTEC
MODEL 409
LINEAR GATE
AND
SLOW COINCIDENCE
IN
IN
OUT OUT
IN
OUT
COINCIDENCE CONTROLS
' COINCIDENCE INPUT 1
E INpyy
antlcoinc.-
INPUT
linear
GATE
-^OUIPUT
OUTPUT
MODEL 409 LINEAR GATE AND SLOW COINCIDENCE

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1-1
MODEL 409
LINEAR GATE AND SLOW COINCIDENCE
1. DESCRIPTION
1.1 General Description
Model 409 Linear Gate and Slow Coincidence is a dual-purpose module incor
porating both a linear gate and a slow coincidence circuit. The operation of
the linear gate is controlled by the slow coincidence circuit. The linear gate is
useful in applications that require inhibiting a linear signal according to
chosen coincidence requirements, e.g., reducing the counting rate in sub
sequent linear analysis equipment. In addition to controlling the linear gate,
the slow coincidence circuit has an output for uses independent of the linear
gate.
Three coincidence inputs are normally provided, each with an IN/OUT control
switch. Provision is included for a fourth coincidence input if desired. (Refer
to Section 6.5 of this manual.) Each input control switch set to IN must have a
coincidence input pulse in order to produce an output from the slow coinci
dence. The slow coincidence output enables the linear gate. Two anticoinci
dence inputs, one dc- and one ac-coupled, are also provided. An input to
either one will inhibit the output of the slow coincidence and the linear gate.
The instrument is designed to meet the recommended interchangeability
standards outlined in USAEC Report TID-20893. ORTEC Model 401/402 Nu
clear Standard Bin and Power Supply provides all necessary power through
the rear module power connector. All signal levels and impedances are com
patible with other modules in the ORTEC 400 Series.
1.2 Description of Basic Function
1.2.1 Linear Gate
The input to the linear gate will accept all pulse shapes existing in the
ORTEC 400 Series linear function modules. If the input signal is bipolar,
the negative portion will not be passed through the linear gate. The
input impedance is greater than 5000 ohms, ac-coupled as normally
sent from the factory, but can be dc coupled if desired. (Refer to
Section 4.4.1.) A dc restoration network at the input reduces baseline
shift at high counting rates. The restoration network works on both
unipolar and bipolar input pulse shapes. The linear gate proper, a
series-parallel saturated transistor switch, incorporates an adjust
ment that allows the linear gate to operate with no pedestal. It is
activated by a transistor-pair current switch, which in turn is activated
by the gate control pulse that is generated when the slow coincidence
circuit produces an output pulse. The output of the linear gate circuit
is fed into a cascode emitter-follower cable driver.
1.2.2 Slow Coincidence
The slow coincidence circuit is of the "overlap" type; i.e., there is no
regeneration of the input signals within the slow coincidence unit. The

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1-2
result is a 2t resolving time for the unit equal to the sum of the two
longest, i.e., widest, input signals. The slow coincidence unit can also
be described as an AND circuit. The unit normally is supplied with
three dc-coupled coincidence inputs and two anticoincidence inputs,
one ac-coupled and the other dc-coupled, although both can be either
ac or dc coupled as desired. (Refer to Sections 4.4.2 and 5.2.) The
timing diagram in Section 4.4.2 will serve to illustrate the nature of the
coincidence and anticoincidence functions on the various combinations
of input signals.
The output of the slow coincidence is a standardized pulse; i.e., the
same output pulse shape occurs for every coincidence event. The
width of this output pulse is adjustable from approximately 0.5 to
3 microseconds. The width also dictates the period the linear gate is
open as the slow coincidence output enables the linear gate section of
the module. The anticoincidence input causes the output of the slow
coincidence to be inhibited, thus causing the inhibit action of the linear
gate. The slow coincidence circuit has IN/OUT control switches for
each of the coincidence inputs. These switches allow the coincidence
module to be programmed as a one-fold, two-fold, or three-fold co
incidence requirement without actually removing the input coaxial
connections. There are no control switches on the anticoincidence
inputs.
Complete provisions are provided on the etched board to allow the
the anticoincidence input D to be converted from anticoincidence
operation to coincidence operation; the details are given in Section
6.5.

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2-1
2. SPECIFICATIONS
2.1 General
Model 409 is housed in o Nuclear Stondord Module; it is two modules wide
and weighs 5.3 pounds. It contains no internal power supply and therefore
obtains necessary operating power from the Nuclear Standard Bin and Power
Supply, ORTEC Model 401/402. All signals in and out of the module are on
front panel BNC connectors, and input power is via the standard connector on
the rear panel.
2.2 Linear Gate
Input Unipolar or bipolar, with positive por
tion leading. Rated range is 0.2V to
lOV, 12V maximum.
Input Impedance Greater than 5000 ohms
Gain Unity
Linearity Integral nonlinearity less than 0.2%
from 0.2V to 8V, 0.3% to lOV
Gate Width Continuously variable from 0.5 to 3
jjLsec
Pulse Feedthrough Less than 10 mV with an 8-volt input
pulse
Output Pedestal Output pedestal adjustable to less
than 1 mV
Output 0.2V to 1OV positive rated output range,
12V maximum
Output Impedance Less than 10 ohms, short-circuit pro
tected
Temperature Stability Gain shift less than 0.02% per °C
Operating Temperature Range 0 to 50°C
2.3 Slow Coincidence
Input Coincidence inputs: Positive IV mini
mum, 30V maximum
Anticoincidence inputs: Positive 2V
minimum, 15V maximum
Coincidence and anticoincidence input
pulses both should be greater than
50 nsec wide.
Input Impedance 1000 ohms
Resolving Time The resolving time between two input
pulses is equal to the sum of the two
input pulse widths. The slow coinci
dence unit does not regenerate the
input signals.
Output Positive 6V with fwhm adjustable from
0.5 to 3 fxsec

2-2
Output Impedance Less than 10 ohms
Power Requirements +24V 34 mA
-I-12V 6 mA
-12V 33 mA
-24V 40 mA
AAechanical Two modules wide and designed to
meet recommended interchange-
ability standards set out in AEC Re
port TID-20893; 2.7 inches wide,
8.75 inches high, and 9.75 inches
long
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3-1
INSTALLATION
3.1 General Installation Considerations
Model 409, used in conjunction with a Model 401/402 Bin and Power Supply,
is intended for rock mounting and therefore it is necessary to ensure that
vacuum tube equipment operating in the same rack have sufficient cooling
air circulating to prevent any localized heating of the all-transistor circuitry
used throughout the Model 409. The temperature of equipment mounted in
racks can easily exceed the recommended maximum unless precautions are
taken. Model 409 should not be subjected to temperatures in excess of 1 20°F
(50°C).
3.2 Connection to Power—Nuclear Standard Bin, ORTEC Model 401/402
Model 409 contains no internal power supply and therefore must obtain oper
ating power from the Nuclear Standard Bin and Power Supply (ORTEC Model
401/402). It is recommended that the bin power supply be turned off when in
serting or removing modules. The ORTEC 400 Series is designed so that it is
not possible to overload the bin power supply with a full complement of
modules in the Bin; however, this may not be true when the Bin contains mod
ules other than those of ORTEC design, and in such instances power supply
voltages should be checked after the insertion of modules. ORTEC Model
401/402 has test points on the power supply control panel to monitor the dc
voltages.
When using Model 409 outside the Model 401/402 Bin and Power Supply,
be sure that the jumper cable used properly accounts for the power supply
grounding circuits provided as per the recommended AEC standards of TID-
20.893. Both clean and dirty ground connections are provided to ensure proper
reference voltage feedback into the power supply, and these must be pre
served in remote cable installations. Care must also be exercised to avoid
ground loops when the module is not physically in the Bin.
3.3 Input Signal Connection to Linear Gate
The input to the linear gate section of the Model 409 is on the front panel BNC
connector; it is directly compatible with the output of all linear amplifiers,
biased amplifiers, pulse stretchers, delay amplifiers, and all linear circuitry
found in the ORTEC 400 Series. The linear gate passes only positive unipolar
signals and/or the positive portion of bipolar signals. This must be kept in
mind when putting in linear signals from units other than those of ORTEC de
sign. The input to the Model 409 linear gate is ac coupled as normally sup
plied but may be dc coupled if desired.
If the Model 409 linear gate is driven from a low impedance source such as
the ORTEC Model 410 output, the input should be terminated in the charac
teristic impedance of the connecting coaxial cable.
3.4 Logic Inputs to the Slow Coincidence
The input pulses to the slow coincidence may come from any source of logic
pulses. The input impedance of the slow coincidence inputs is 1000 ohms, and

3-2
some care must be given to ensure that reflections do not occur in the driv
ing transmission cable. This probably can best be avoided by terminating the
driving cable at the slow coincidence inputs with the characteristic impedance
of the driving cable. The amplitude and width of the input signals are speci
fied in Section 2.3.
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Linear Output Signal Connections and Terminating Impedance Considerations
The source impedance of the 0-10 volt standard linear outputs of most 400
Series modules is approximately 1 ohm. Interconnection of linear signals
is, thus, non-critical since the input impedance of circuits to be driven is
not important in determining the actual signal span, e.g., 0-10 volts, de
livered to the fol lowing circuit. Paralleling several loads on a single out
put is therefore permissible while preserving the 0-10 volt signal span.
Short lengths of interconnecting coaxial cable(up to approximately 4 feet)
need not be terminated. However, if a cable longer than approximately
4 feet is necessary on a linear output, it should be terminated in a resistive
load equal to the cable impedance. Since the output impedance is not
purely resistive, and is slightlydifferent for each individual module, when
a certain given length of coaxial cable is connected and is not terminated
in the characteristic impedance of the cable, oscillations will generally
be observed. These oscillations can be suppressed for any length of cable
by properly terminating the cable either in series at the sending end or in
shunt at the receiving end of the line. To properly terminate the cable
at the receiving end, it maybe necessary to consider the input impedance
of the driven circuit, choosing an additional parallel resistor to make the
combination produce the desired termination resistance. Series terminating
the cable at the sending end may be preferable in some cases where re
ceiving and terminating is notdesirable or possible. When series terminat
ing at the sending end, full signal span, i.e., amplitude, isobtainedat
the receiving end only when it is essentially unloaded or loaded with an
impedance many times that of the cable. This may be accomplished by
inserting a series resistor equal to the characteristic impedance of the ca
ble internally in the module between the actual amplifier output on the
etched board and the output connector. It must be remembered that this
impedance is in series with the input impedance of the load being driven,
and in the case where the driven load is900 ohms, a decrease in the signal
span of approximately 10% will occur for a 93-ohm transmission line. A
more serious loss occurs when the driven load is 93ohms and the transmis
sion system is 93 ohms. In this case, a50% loss will occur. BNCconnec
tors with internal terminators are available from a number of connector
manufacturers in nominal values of 50, 100, and lOOOohms. ORTEC stocks
in limited quantity both the 50 and 100 ohm BNC terminators. The BNC
terminators are quite convenient to use in conjunction with a BNC tee.

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4-1
4. OPERATING INSTRUCTIONS
4.1 Front Panel Controls
IN/OUT (COINCIDENCE INPUT Control Switches A, B, and C)
These three switches allow the input signals to the coincidence circuit to be
disabled without the necessity of actually removing the input coaxial cables.
They effectively cause the coincidence circuit to be either one-fold, two-fold,
or three-fold, as may be desired, by operating the front panel switches.
4.2 Initial Testing and Observation of Pulse Waveforms
Refer to Sections 6.1 and 6.2 for information on testing performance and ob
serving waveforms.
4.3 Connector Data
PGl - LINEAR GATE INPUT (BNC)
PGl is the ac-coupled linear gate input. It has input impedance of greater than
5000 ohms. The rated input voltage range is 0.2 to 10 volts, and maximum
input 12 volts. To minimize reflections when driving from low impedance
sources into this connector, a terminator equal to the characteristic impedance
of the driving cable should be shunted from this connector to ground.
PG2-COINCIDENCE INPUTA(BNC)
PG2 is the dc-coupled coincidence input. It has input impedance of 1000
ohms, and requires a positive input signal greater than 1 volt.
PG3-COINCIDENCE INPUT B (BNC)
The characteristics for PG3 are the same as those for PG2.
PG4-COINCIDENCE INPUT C (BNC)
The characteristics for PG4 are the same as those for PG2.
PG5-ANTI-COINC. INPUT D (BNC)
PG5 is the dc-coupled anticoincidence input. It has input impedance of 1000
ohms, and requires a positive input signal greater than 2 volts.
PG6-ANTI-COINC. INPUT E (BNC)
PG6 is the ac-coupled anticoincidence input. It has input impedance of 1000
ohms, and requires a positive input signal greater than 2 volts.
PG7-OUTPUT (BNC)
PG7 is the dc-coupled coincidence output. It provides a positive 6-volt output
signal whose width is continuously adjustable from 0.5 to 3 microseconds. Out
put impedance is less than 10 ohms.
PG8- LINEAR GATE OUTPUT (BNC)
PG8 is the ac-coupled Linear Gate output. Output impedance is less than 10
ohms. It provides positive output signals only, with a rated range of 0.2 to 10
volts, and a maximum output of 12 volts.
TPl —Coincidence Output Test Point
TPl is the oscilloscope test point for monitoring a signal on the coincidence
output BNC connector, PG7. This test point has a 470-ohm series resistor con
necting it to PG7.
TP2 — Linear Gate Output Test Point
TP2 is the oscilloscope test point for monitoring a signal on the linear gate

4-2
output BNC connector, PG8. This test point also has a 470-ohm series resistor
connecting it to PG8.
Power Connector
The Nuclear Standard Module Power Connector is an AMP #202515-3.
4.4 Typical Operating Considerations
4.4.1 Linear Gate
The Linear Gate is enabled by the output pulse of the slow coincidence
section of the Model 409. Normally, the width of this pulse is continu
ously variable from 0.5 to 3 microseconds; for other pulse widths refer
to Section 6.2 of this manual.
Figure 4.1 illustrates the gating action of the Linear Gate. Notice that
only the positive portion of the input signal is passed through the
Linear Gate.
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I
I
1
;+!>+■
444t
++++
-H-H- ' 1 ! ! M i M M j M 1
/
\ ^
(a) Linear Gate Input
(b) Linear Gate Output
Figure 4.1
The Linear Gate has an internal pedestal adjustment that allows the
pedestal to be reduced to a negligible value. (Refer to Section 6.2 for
adjustment procedure.) Figure 4.2 shows the output of the Linear Gate
with the pedestal a) properly adjusted and b) improperly adjusted.
If it is desired to have the input dc coupled, a short jumper wire can
be connected from pin 2 to pin 4 on the etched board connector.
4.4.2 Slow Coincidence
The Slow Coincidence circuit is of the "overlap" type in that there is
no regeneration of the input signals within the coincidence recogni
tion circuit. This circuit can also be described as an AND circuit. After
coincidence has been recognized, regeneration of the coincidence
recognition output occurs, and this regenerated signal constitutes
the Linear Gate enable input and the Slow Coincidence output.
Since there is no reshaping of the input pulses, the 2t resolving time
of two input signals is controlled directly by the pulse width of the
input signals. Figure 4.3 presents some timing diagrams illustrating
input and output waveforms from the Model 409 coincidence section.

4-3
1
1
■-H-H-
=H-H-
444+-
+444:
_H 1 ! 1 1 t 1 1 ! *
"t"! 1 t
w
>
(a) Linear Gate Output showing
pedestal properly adjusted.
Scale; 100 mV/cm
500 nsec/cm
{ j } 1
MM
4
(b) Linear Gate Output showing
pedestal improperly adjusted.
Scale: 100 mV/cm
500 nsec/cm
Figure 4.2
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If the input pulse that causes coincidence is longer than the pulse
width normally generated by the Slow Coincidence circuit, the Slow
Coincidence output pulse will be as long as the duration of the input
pulse. This is normally not a problem since the inputs to the Slow Co
incidence unit have been reshaped by a preceding logic function.
4-
i "1
j
—f H
! n i 1 1 1 n H-hH-
1 H if' 1
h-—1 ' 1
-tr l l : n It-H-H-
^ 1 ^
- - —r - 1
-1 r+ M ! i
(a) Coincidence Input A
(b) Coincidence Input B
(c) Coincidence Output
1
I
rm
FFtT
MI I f M i I n I itTT
i lmih
(a) Anticoincidence Input D
(b) Coincidence Input A 11
(c) Coincidence Input B
(d) Coincidence Output
' (a) Coincidence Input A
. (b) Anticoincidence Input D m
. (c) Coincidence Input B
, (d) Coincidence Output
Figure 4.3

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5-1
5. CIRCUIT DESCRIPTION, Linear Gate and Slow Coincidence (Etched Board 409-
0201)
5.1 Linear Gate
The input to the Linear Gate can be either ac or dc coupled. (See Drawings
409-0201-51, 409-0201-Bl, and 409-0101-51.) The ac-coupled signal is fed
in on pin 2 of the etched board and then into the baseline recovery network
consisting of diodes D1 through D4 and resistors R1 and R2. The dc restoration
network works as follows: With the application of a positive input signal at
pin 2, it is coupled through capacitor C1 to the junction of D4 and R2. As the
junction of D4-R2 increases in the positive direction, the current through D1
increases due to the current flow out of capacitor C1 through R2. The current
flow out of C1 and through R2 is that current necessary to maintain the ampli
tude of the input voltage at the junction of D4 and R2. With the removal of the
input pulse, the quiescent current flow through D1 is available to recharge
capacitor C1 back to its steady-state value, since the current through D1 can
be reduced to zero and the current through D4 can increase in magnitude to
a value of 21. Therefore, the potential at the junction of D4 and R2 will be re
stored to its steady-state value in a period of time approximately equal to
the pulse width of the incoming pulse. The Linear Gate will gate through posi
tive signals or the positive part of bipolar signals. The input signals are
coupled through emitter-follower Q1 to the collector of Q2, the series section
of a series-shunt Linear Gate. The positive part of the input signal back-biases
diode D6, while the negative parts of bipolar signals are blocked by D5. In
the steady-state condition Q2 is normally off, since the current switch, Q3 and
Q5, is requiring a current through R9 of approximately 4 milliamperes. Q3 of
the current switch is normally on, and the current required in the emitter cir
cuit of the current switch is drawn from diode D7 and resistor R8. With the
heavy conduction of Q3, the base current for Q2 is zero; therefore, the series
resistance of the collector to the emitter of Q2 is very high. Conversely, tran
sistor Q4 has a constant-current base drive through R13 of approximately 1
milliampere, and diode D8 is back biased, causing shunt transistor Q4 to be
heavily saturated.
With the application of a positive signal to the collector of Q2, and with the
absence of a signal to the current switch, transistors Q3 and Q5, the series-
shunt gate is closed for input signals to pin 2 or 4. The Linear Gate is opened
by the application of a positive signal to the base of Q5, which causes the
current switch to switch its emitter current from Q3 to Q5. When Q5 conducts
the emitter current of the current switch, the base drive to Q2 is available via
R8, and concurrently, base current for Q4 becomes negligible, since the col
lector of Q5 requires approximately 4 milliamperes. With the current switch
conducting current in Q5, it is seen that Q2, the series element, is in heavy
saturation, with the base drive current supplied from R8 flowing into the base
through the emitter and back through diode D9 to the emitter follower, Ql.
Also, Q4, the shunt element in the Linear Gate, is now back biased and pre
sents a high shunt impedance to signals flowing through the series element,
Q2. With the series-shunt Linear Gate in the open position, i.e., Q2 saturated

5-2
and Q4 bock biased, the output signals of emitter-follower Q1 are presented
to emitter-follower Q6 and then to the coscode emitter follower consisting of
Q7 and Q8. The output of the coscode emitter follower is taken from the emit
ter of Q7 to pin 22, the output of the Linear Gate.
Notice that with the Slow Coincidence front panel controls all switched to the
OUT position, the current available through the common emitter resistor, R48,
will flow through Q15, causing the current switch to conduct current through
transistor Q5. With Q5 conducting current in the steady-state condition, the
Linear Gate will be normally open. With the Linear Gate operating in the
normally open mode, the application of an anticoincidence signal to either
Q13 or Q14 will result in the closing of the Linear Gate for the duration of the
anticoincidence signal, since the current through Q15 will be transferred to
Q16 and will enable the current switch, Q3 and Q5, to switch states.
5.2 Slow Coincidence
The Slow Coincidence circuit has provisions for three coincidence input sig
nals and two anticoincidence input signals. The three coincidence signals
are dc coupled and come from inputs A, B, and C. The anticoincidence inputs
are fed in on inputs D and E, and may be either dc or ac coupled. All inputs are
fed in via the front panel BNC connectors. The three coincidence inputs may
be switched IN and OUT; i.e., the control of the input pulses may be disabled
by operation of the front panel switches.
The Slow Coincidence circuit consists of a three-transistor AND circuit with an
inhibit circuit controlling the output of the AND circuit. The output of the AND
circuit triggers an output pulse shaper which feeds an output emitter follower.
The coincidence AND circuit consists of transistors Q9, QIO, and Q11. These
transistors have their common collectors connected in parallel to a coincidence
line which feeds into the output shaper, trigger pair Q15,Q16, and Q1 7. Tran
sistors Q9, QIO, and Q1 1 operate in the switching mode and are either
switched off or are in hard saturation. Operation of the front panel coincidence
control switches determines the mode of these transistors. When the control
switches are placed to IN, base current is drawn through the 20K-ohm base
resistor, saturating the transistor; e.g., Q9 will be saturated due to the base
current flowing through R28. If the control switch associated with COINCI
DENCE INPUT A is placed to OUT, a lOK-ohm resistor, R25, is connected from
the base of 09 to the +24V supply. This back-biases 09 and disables coin
cidence input A. A similar operation occurs for coincidence inputs B and C.
The anticoincidence function, i.e., inhibit, is performed with transistors 012,
013, and 014. The collector of 012 is connected in parallel with the collectors
of input transistors 09, OlO, and Oil. Transistor 012 functions as a switch
and is normally off, back-biased by approximately 0.3 volts by resistors R41,
R44, and R46. 012 is switched from its OFF state to its ON state by saturation
of either 013 or 014. Both 013 and 014 are normally off and are pulled into
saturation with the application of an anticoincidence input pulse to the base
of 013 via R39, or 014 via R42.

5-3
An output pulse from the Slow Coincidence unit is generated when the three
coincidence input transistors Q9, QIO, and Q11, and the anticoincidence con
trol transistor, Q12, are turned off, either by application of input pulses or by
operation of the coincidence control switches. When these transistors are all
turned off, the coincidence line connected to the base of Q15 moves from its
steady-state value towards —1.3V. This negative-going waveshape causes the
current through R48 to be switched from Q16, which is normally on, to Q15,
resulting in regeneration of the input pulse. Trigger-pair Q15 and Q16 gen
erate a pulse whose width is controlled by C16, R53, and R54. Emitter-follower
Q17 provides a low impedance discharge path for capacitor C16, which re
duces the trigger pair dead time. Emitter-follower Q18 provides a low im
pedance output driver for the Slow Coincidence output pulse.
K

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6-1
MAINTENANCE
6.1 Testing Performance of Slow Coincidence and Linear Gate
6.1.1 introduction
The following paragraphs are Intended as an aid in the installation
and checkout of Model 409. These instructions present information on
front panel controls, waveforms at test points and output connectors.
6.1.2 Test Equipment
The following, or equivalent, test equipment is needed:
(1) ORTEC Model 419 Pulse Generator
(2) Tektronix Model 580 Series Oscilloscope
(3) 100-ohm BNC terminators
(4) Vacuum tube voltmeter
(5) ORTEC Model 410 Multimode Amplifier
(6) ORTEC Model 415 Sum-Delay Amplifier
(7) ORTEC Model 407 Crossover Pickoff
(8) ORTEC Model 416 Gate and Delay Generator
(9) Schematic and block diagrams for Model 409 Linear Gate and
Slow Coincidence
6.1.3 Preliminary Procedures
(1) Visually check module for possible damage due to shipment.
(2) Connect ac power to Nuclear Standard Bin, ORTEC Model 401/402.
(3) Plug module into Bin and check for proper mechanical alignment.
(4) Switch ac power on and check dc power supply voltages at test
points on the Model 401 power supply control panel.
6.1.4 Slow Coincidence
(1)a. Connect Model 419 Pulse Generator, Model 410 Multimode Am
plifier, and Model 407 Crossover Pickoff so that an output pulse
from the Model 407 is observed.
b. Using a tee, feed the output of the Model 407 into COINCIDENCE
INPUT connectors A and B.
c. Set the COINCIDENCE CONTROLS switches as follows:
A. . .IN, B. . .IN,C. . .OUT
(2)a. Observe the coincidence output at TPl (PG7); the pulse should
be positive 7.0 ± 0.6 volts in amplitude.
b. Adjust the trimpot at the rear of the board over its entire range
and observe the minimum and maximum pulse duration. The
minimum should be 0.6 microsecond or less and the maximum
should be 3.0 microseconds or greater.
c. Observing the coincidence output, adjust the trimpot at the rear
of the etched board until the fwhm of the coincidence output
pulse is 1.5 microseconds, or as desired.

6-2
(3) Loading PG7, the coincidence OUTPUT, with 100 ohms should
reduce the output, but not to less than 4V.
(4)a. Switch COINCIDENCE CONTROL C to IN. The coincidence out
put should disappear.
b. Return CONTROL C to OUT.
c. Switching CONTROL A or CONTROL B to OUT should not cause
the coincidence output to disappear.
d. Switching both CONTROL A and CONTROL B to OUT should
cause the coincidence output to disappear.
e. Link COINCIDENCE INPUT B to COINCIDENCE INPUT C with a 4-
foot piece of RG-62/A. Switching CONTROL C to IN should not
cause the coincidence output to cease.
f. Switch CONTROL A and CONTROL B to OUT. The coincidence
output should not disappear.
(5)a. Remove link from INPUT B and INPUT C.
b. Set COINCIDENCE CONTROLS switches as follows:
A. . .IN, B. . .OUT, C. . .OUT
c. Connect the output of Model 407 directly to ANTI-COINC. INPUT D.
d. Connect ANTI-COINC. INPUT D to COINCIDENCE INPUT A
through 100 feet of RG-62/A. Terminate the RG-62 at COINCI
DENCE INPUT A. Note the reference time of the coincidence
output pulse.
e. Removing the input to ANTI-COINC. INPUT D should cause the
coincidence output to advance in time 400 ± 100 nanoseconds.
f. Reconnecting the output of Model 407 to ANTI-COINC. E should
delay the coincidence output 400 ± 100 nanoseconds from its
reference location noted in step e above,
g. Reconnect the output of Model 407 to COINCIDENCE INPUT A
and B. Set COINCIDENCE CONTROLS switches A and B to IN
and C to OUT.
6.1.5 Linear Gate
(l)a. Feed the output of Model 419 into a Model 410. Feed the BI
POLAR OUTPUT of the Model 410 into a Model 407. Feed the
OUTPUT from the Model 407 into the INPUT of the Model 416.
Set the Model 410 pulse shaping mode to Double RC (DRC),
i.e., INTEGRATION and 1st and 2nd DIFFERENTIATION to .2
(//.sec).
b. Feed the BIPOLAR OUTPUT of the Model 410 into the DELAYING
INPUT A of a Model 415 Sum-Delay Amplifier. The output of the
Model 410 should be approximately 2 volts.
c. Delay the output of the Model 416 until the positive pulse from
the Model 416 starts 200 nanoseconds before the start of the
output pulse from the Model 415. The output from the Model
416 should be at least positive 2V and 400 nanoseconds fwhm.