Panasonic CF-2700 User manual

ORDER NO. IED84113035C2
Service Manual
MSX
Personal Computer
CF-2700
Specifications
Microprocessor . Z-80A
Memory . ROM 32 K bytes (MSX-BASIC)
Main RAM 64K.bytes
Video RAM 16K bytes
Video system
Controller .
Number of displayable characters
Number of displayable dots .
Output signals .
Sound system
Controller .
Functions .
Keyboard .
Cassette tape interface
System .
Transfer rate .
I/O ports
Slot .
Printer port .
General port .
Sound output ..
Dimensions and Weight (Main unit)
Power requirements
Voltage .
Power consumption .
TMS 9929A
32 characters x 24 lines
8 (H) x 8 (W) dots/character mode
40 characters x 24 lines
8 (H) x 6 (W) dots/character mode
256 (H) x 192 (V) dots
Video output, RF output
AY-3-8910A
8 octave, 3 chord output
73 keys
FSK
1200/2400 baud
2 (comforms to MSX specifications)
1, 14-pin
2, 9-pin each
1
436 (W) x 245 (D) x 90 (H) mm
approx. 3.6 kg
220 V, 50 Hz
(Only for UK 240 V, 50 Hz)
28 W
Design and Specifications are subject to change without notice.
Panasonic
Matsushita Electric Trading Co., Ltd.
P.O. Box 288, Central Osaka Japan

CONTENTS
Location of Controls and Components . 3
Memory Map . 5
I/O Map . 5
General for Peripheral Circuit . 7
Display Screen, Character Codes . 20
Self Test . 21
Block Diagram . 33
Disassembly Instructions . 34
Adjustment . 39
Connector Pin Connection . 40
Wiring Connection Diagram . 42
Schematic Diagram (Main Board) . 43
Printed Circuit Board (Main Board) . 47
Schematic Diagram & Printed Circuit Board (Power Source) . 49
Schematic Diagram (Video Board) . 50
Printed Circuit Board (Video Board) . 51
Printed Circuit Board (Keyboard) . 52
IC Block Diagram . 53
Parts Location . 62
Parts Location (Keyboard) . 63
Packing Instruction . 64
Replacement Parts List . 64
Copyright Matsushita Electric Industrial
Co., Ltd. 1984
The EE3 system realizes software
compatibility between personal
computers. is a trademark of
Microsoft Corporation.
IMPORTANT (FOR U.K.)
The wires in the mains lead are coloured
in accordance with the following codes:
Blue: Neutral Brown: Live
As the colours of the wires in the mains
lead of this apparatus may not
correspond with the coloured markings
identifying the terminals in your plug,
proceed as follows:
•The wire which is coloured blue must be
connected to the terminal which is
marked with the letter N or coloured
black.
•The wire which is coloured brown. must
be connected to the terminal which is
marked with the letter L or coloured
red.
Notes:
•Disconnect the mains plug from the
supply socket when not in use.
•Do not remove cover. Live parts inside.

(located on
the left side)
I fctr-i
ON POWER
o
OFF

(T^Function keys
Key used for easy inputs of pre¬
defined character strings.
( 2 )Power indicator
Lights when the power switch is
turned on and goes out when the
power is turned off.
(14) Sound output jack
Audio (sound) signal
Connects to the TV
terminal.
output
audio
jack.
input
(l5) Video output jack
Video signal output jack. Connects
to the TV video input terminal.
(3) S pecial keys
Keys used to select, correct, and
edit input characters, and control
program execution.
(16) RF output jack
RF signal output jack,
the TV antenna terminal.
Connects
to
( 4 )Space bar
Bar used to input a space between
characters.
(3) Character keys
Keys used to input characters.
(17) Channel adjust trimmer
After connecting the TV and
computer, turn on the power switch.
Set the TV to UHF channels 35-37.
Insert the adjustment screwdriver
into the channel adjust trimmer and
adjust for a clear picture.
(6)Cursor keys
Keys used to move the cursor.
(7) (¥) General port 1, General port 2
Connectors used to connect
joysticks, tablets, etc.
(18) Power switch
Power turns on when set to "ON" and
the power indicator lights up. Power
turns off when set to "OFF".
, 9;(10) Slot 1. Slot 2
Slots for MSX cartridges.
(ll)Printer connector
Connector used to connect a printer,
plotter, etc.
(l2) C assette Input/Output Connector
Connector used to connect a cassette
tape recorder.
(13) P ower cord
- 4 -

Memory Map (when using BASIC)
Address in hexadecimal
0000
ROM
area
8000
User
area
RAM
area
F380
FFFF
MSX BASIC
ROM
Program area
(text area)
Variable area
Array variable area
Free area
Stack area
Character string area
File control block
(User reserve area)
Work area
(system area)
I/O Map
Area storing the program to which line
numbers have been added.
Area for variables. For character
variables, this area stores the
pointer which points to the character
string (string descriptor).
Area for array variables. If the array
variables are of the character type,
this area stores the pointer which
points to the string in the string area.
This area is allocated when the DIM
statement is executed and an array with
a subscript of 10 or less is used.
The free area is an unused area. The
size of the free area is the size of
the user area minus the sizes of the
character area, stack area, variable
area, and program area. The size of
the free area can be obtained by the
FRE function.
Stack area storing the return address
for BASIC when the FOR-NEXT statement
or GOSUB statement is executed.
Area storing the strings contained in
the character variables and array
variables. The size of the string area
is as specified in the CLEAR
statement. If no size is specified in
the CLEAR statement, an area of 200
bytes is allocated.
Area used during the input and output
of files. This area is allocated
according to the number specified in
the MAXFILES statement.
The high limit address can be set in
the CLEAR statement to F380 or below
so that an area (such as for machine
language subroutines) can be allocated
up until the work area for free use by
the user.
Work area used by BASIC.
Port Bit I/O
Signal Name
Description
A
0
ffH
IB
Specifies the slot number for addresses
1
&H0-&H3FF
mm
Specifies the slot number for addresses
&H4000-&H7FFF
■
Specifies the slot number for addresses
5
&H8000-&H8FFF
6
Specifies the slot number for addresses
7
MB
'If • &HC000-&HFFFF
B
||
Keyboard return signal
C
SK
KB0, KB1
KB2, KB3
Keyboard scan signal
Cassette control (ON when L)
5
Cassette write signal
6
CAPS lamp signal (lights when L)
7
SOUND
Software controlled sound output
- 5 -

I/O Address Assignment
I/O address
(hexadecimal)
00
80
90
98
AO
A8
BO
CO
DO
D8
FF
■ RS-232C
Printer
VDP
(9929A)
PSG
(AY-3-8910A)
PP1
(8255)
I/O address
R/W
Contents Remarks
&H98
W
Data write to the video
RAM
R
Data read from the video
RAM
&H99
W
Command, address set
R
Status read
&HA0 W
Address latch
&HA1 w
Data write
&HA2
R Data read
&HA8
W Port A data write
R
Port A data read
&HA9
W Port B data write
R Port B data read
&HAA W Port C data write
R Port C data read
&HAB W Mode set
&H90 W
Strobe output (bO)
Latch output
R
Status input (bl)
"l” when busy
&H91
W
Print data
Latch output
•The I/O address with the ■ mark are provided to optional equipment.
•For details on the VDP, PSG, and PPI, see their respective manuals.
•Addresses &H40-&HFF represent the system reserve area.
PSG Bit Assignment
Port Bit
I/O
Bit 6 at Port B
Connector Pin Number
A 0
Input
Low level
High level
Port 1 pin 1
Port 2 pin 1
1
Low level
High level
Port 1 pin 2
Port 2 pin 2
2
Low level
High level
Port 1 pin 3
Port 2 pin 3
3
Low level
High level
Port 1 pin 4
Port 2 pin 4
4
Low level
High level
Port 1 pin 6
Port 2 pin 6
5
Low level
High level
Port 1 pin 7
Port 2 pin 7
6
Keymatrix assignment input (low level)
7 CSAR (Read signal of the cassette tape)
B
0
Output
Port 1 pin 6
1
Port 1 pin 7
_
► Note 2
2 Port 2 pin 6
3
Port 2 pin 7 J
4
Port 1 pin 8
5 Port 2 pin 8
6 Input select of port A
7
Note 1: Either port 1 or 2 is selected by the output level of bit 6 at port B.
Writing a "1" to bit 6 at port B ■ + ■ high level output port 2 selected.
Writing a "0" to bit 6 at port B low level output port 1 selected.
Note 2: Be sure to output a high level at these pins if portB is to be used for input.
- 6 -

General for Peripheral Circuit
CPU (Central Processing Unit) Peripheral
Circuit
CPU Peripheral Circuit consists of CPU,
Clock Generator Circuit and Reset
Circuit.
Z80A (pPD780C-l, IC8) is used as CPU. An
interruption system is maskable inter¬
rupt, not non-maskable. AND signals of
VDP's INT and an external interrupt are
fed to INT terminal. In Ml cycle, 1 WAIT
is inserted, and external WAIT is ac¬
cepted asynchronously with CLOCK signal.
BUSRQ and BUSAK are not used, neither
DMA function.
Fig. 1 CPU Peripheral Circuit
The CLOCK Generator Circuit—Serial Os¬
cillation Circuit of 74HC04 (IC43)--
oscillates 10.6781522 MHz to generate
VDP CLOCK and, at the same time, gener¬
ates CPU CLOCK in the circuit of 74LS74
(IC42) and 74LS107 (IC47) which divides
VDP CLOCK by 3 to get 3.559384 MHz.
Moreover, CLOCK Generator Circuit di¬
vides CPU CLOCK into halves to get
1.779462 MHz by 74LS74 (IC39) and gen¬
erates PSG CLOCK.
CPU CLOCK -
3.55938MH!
IIC8.PIN6I
PSG CLOCK
1.77946 MHz
I1C 39. PIN 8: -
Fig. 2 CLOCK Waveform
The Reset Circuit utilizes the charge of
CR Circuit (C13 and R26), but it takes
too much time to raise RESET signal by
only the CR. So the circuit is compul¬
sively raised by Q10, when each end of C
becomes about 1.5 V. Therefore, RESET
signal changes "L" into "H" in 60 ms
after power source ON.
POWER SOURCE
RESET
A
I i i i—i—i—i—i—i—i—i-
0 50 100 (ms)
Fig. 3 RESET Signal
IROM ~~|
This system uses 32 K x 8 bits MASK ROM
(IC32, MN23257) which builds in the MSX
BASIC. CS is connected to SLTO, and 0E
to A15. Access time is available up to

Main Memory Peripheral Circuit
Main Memory Peripheral Circuit consists
of Main Memory and Memory Access Cir¬
cuit.
The Main Memory has a 64 KB memory space
by using eight 16 K x 8-bit DRAMs. Re¬
fresh is performed by RAS-ONLY REFRESH.
Because RAS pre-charge time in refresh¬
ing Ml cycle is ensured to be 100 ns by
Timing Chart, the access time of RAM
must be 150 ns. In the Memory Access
Circ uit, RAS is generated by MERQ or
RESH and CLOCK. The switchover of the
row address to the column address is
done by the multiplexer 74LS157 and CAS
is generated by being staggered the
time, with the condenser C35, when the
column address is outputted. C35 ensures
that the CAS will be "L", considering
differences of the output timing of
74LS157, after the switchover of the row
address to the column address.
WE is gen erated by BWR, and OE by BRD.
RAS, CAS, WE and OE protect from the
undershoot by being inserted a resist¬
ance for the damping.
All of Input/Output with external
equipment are done through I/O ports in
this system, and an access signal of
each port is generated in this circuit.
I/O Select Peripheral Circuit consists
of I/O Select Generator Circuit, Chip
Access Signal Generator Circuit and
Short Write Generating Circuit.
Fig. 6 I/O Select Peripheral Circuit
I/O Select Peripheral Circuit
- 8 -

I/O Select Generator Circuit generates
I/O Select signal according to the I/O
map. This signal is generated through
high-order five bits in low-order byte
of Address Bus and through BIORQ and
Multiplexer 74LS138 (IC25). In order to
ensure data stabilizing time when PSG is
engaged in WRITE, and to be considered
that the output delay time is 350 ns
when PPI is in WRITE, WRITE signal is
raised faster by Short Write Generator
Circuit.
Chip Access Generator Circuit ge nerates
CSW/CSR (VDP Access signals), P P IWR/
PPIRD (PPI Access signals) and BCl/BDIR
(PSG Access_signa ls) from I/O Select
signal and BWR/BRD/SWR.
Automatic refreshing function of VRAM
Composite video output, in PAL system
Interruptible in every frame
Automatic processing of the sprite
screen.
This system uses TI s TMS9929A as CRTC.
This LSI’s features are as follows.
. 256 x 192 pixels resolution
. Used 4,8 and 16 KB as VRAM (16 KB is
used in MSX.)
Table 1 Screen Mode of VDP.
A VDP's operation depends on values of 9 READ and WRITE, VDP resistor or VRAM. In
registers in VDP and a table on VRAM. "L", VRAM is the candidate. AO is con-
VDP has three control signals which are nected to MODE terminal. CSR i s gener-
CSW, CSR and MODE. MODE signal distin- ated by Inverted N AND of CSVDP and RD,
guishes which should be a candidate for and CSW is by OR of CSVDP and WR.
Fig. 7 VDP Peripheral Circuit Diagram
- 9 -

PSG (Programmable Sound Generator)
Peripheral Circuit
PSG Block consists of PSG and General
Port Circuit. This system uses GI's
AY-3-8910A as PSG, which makes it enable
to produce 8 octaves, triple chords and
noise-sound effects. This LSI builds in
a tone generator, a noise generator, an
envelope generator and 16 registers
whose each value decides the frequency
and the volume of the sound by software.
This LSI has also two I/O ports which
are available for Input/Output with
General Port, Keyboard Control and input
to a cassette tape recorder. In this
occasion, each bit in port A/B is
assigned as the following table.
'-'1
I/O
Function
Input
PORT 1-1 PORT 2-1
10 A1 PORT 1-2 PORT 2-2
10 A2
PORT 1-3 PORT 2-3
10 A3
PORT 1-4 PORT 2-4
10 A4 PORT 1-6 PORT 2-6
10 A5 PORT 1-7 PORT 2-7
10 A6
Input specifying the layout of Keyboard
10 A7
Read signal input from a cassette tape recorder
10 B0
Output
P0RT1
10 Bl
PORT1
10 B2
P0RT2
10 B3
P0RT2
10 B4 P0RT1
10 B5
PORT2
10 B6 Selecting input of PORT A "L"=P0RT 1 "H"=P0RT 2
10 B7
Table 2 Bit-Assignment in PSG Port
PSG has three control lines—BDIR, BC1 Input/Output are shown as the following
and BC2—, whose control signals in table.
BDIR
BC1
BC2 State
0
0 1
Not Selected
0
1 1
Readout from PSG
1
0
1
Writing in PSG
1
1 1
Address latch
Table 3 PSG Control Signal
- 10 -

In General Port Circuit, there are two
general ports (Input 4-bit, Output 1-bit
and I/O 2-bit) using multiplexer 74LS157
(IC28, 33) and open collector gate
74LS09 (IC37, 40).
Fig. 8 PSG Peripheral Circuit
CF-2700 uses AY-3-8910A whose maximum
access time is 200ns and minimum width
of write data pulse is 165ns.
PPI (Programmable Peripheral Interface)
Peripheral Circuit
PPI Block consists of PPI (using
yPD8255AC-5), Keyboard Control Circuit
and Slot Signal Generator Circuit.
CF-2700 adopts MODE 0 (ports A,C for
output, and port B for input). This LSI
is utilized for specifying the slot num¬
ber, controlling Keyboard, for output to
a cassette tape recorder and its control
and output of click sound. Bits of three
ports are assigned as the following
table.
Port
I/O Bit
Function
A
0^7
Specifying the Slot Number
B
0*7
Keyboard Return Signal
C Output
0^3 Keyboard Scan Signal
4
Controlling the motor of a cassette tape recorder 0=ON 1=0FF
5
Signal writing in a cassette tape recorder
6
Controlling Keyboard CAPS Lamp 0=LIGHTING
o
Output of Click Sound
Table 4 Port function in PPI
- 11 -

Fig. 9 PPI Peripheral Circuit
Slot signal is generated from a signal
which is set up in Port A by data selec¬
tor 74LS153 (IC10) and decoder 74LS139
(IC23).
[Cartridge ~|
Signals connected to Cartridge Slot are
described in the table 6 and explained
in the table 7.
Data bus is connected via Buffer 74LS245
(IC5). When I/O or Slot 0 is selected,
the mainframe and the slot are separated
and the bus is controlled to go to the
mainframe in READ and INTERRUPT
operations.
Port A is used for specifying the slot
number of address bank in units of 16
KB. Port A is preset for this operation
as the following table.
Bit of
Port A
Contents
PAl PAO
Slot Number of Page 0
PA3 PA2 Slot Number of Page 1
PA5 PA4
Slot Number of Page 2
PA7 PA6 Slot Number of Page 3
Table 5 Meaning of each bit in Port A
LS245
DATA BUS
BUFFER
Fig. 11 Data Bus/Buffer Circuit
CS1, CS2 and CS12 are generated
from A15 and A14 by decoder
74LS139.(IC23).
Keyboard Scan signals (0-3 bits) of Port
C are decoded by 74LS145 (IC46) and in¬
putted to Port B through Keyboard.
IC23 1C 22
LS139 LS08
DECODER AND GATES
IC10
LS153 1C 23 1C 22
DATA LS139 LS08
SELECTOR DECOCER AND GATES
Fig. 12 Chip Select Generator Circuit
Fig 10 Slot Signal Generator Circuit

Pin
Number
Name
I/O
Note 1
Pin
Number
Name
I/O
Note 1
1 CSI
0
2
CS2
0
3 C$T2
0
4
SLTSL
0
5
RESERVED
-
6
RFSH
0
7 WAIT
I 8
INT
I
9
HI
0
10
BUSDIR
I
11 IORQ
0 12
MERQ
0
13
WR
0 14
RD
0
15
RESET
0
16
RESERVED
17
A9
0 18
A15
0
19
All
0 20
A10
0
21
A7
0 22
A6
0
23
A12
0 24
A8
0
25
A14
0 26
A13
0
27 Al
0 28
AO
0
29 A3
0 30
A2
0
31 A5
0 32
A4
0
33 D1
I/O 34
DO
I/O
35 D3
I/O 36
D2
I/O
37
D5
I/O
38
D4
I/O
39 D7
I/O
40
D6
I/O
41
GND
-
42
CLOCK
0
43 GND
-
44
SW1
_
45 +5 V -
46
SW2
_
47 +5 V
-
48
+12 V
_
49
SUNDIN
I 50
-12 V
a) Note 1:The distinction of Input/Output is based on the mainframe.
b) Reserved terminals are forbidden using.
Table 6 Connected Signal Lines of
Cartridge Bus
- 13 -

Pin No. Name Contents
1 CS1 ROM 4000...7FFF Address Select Signal
2
CS2
ROM 8000...BFFF Address Select Signal
3 CS12
ROM 4000...BFFF Address Select Signal (256 K for ROM)
4 SLTSL
Slot Select Signal adds Select Signal peculiar to
each slot
5
RESERVED For Future use
6
RFSH
Refresh Cycle Signal
7
WAIT
WAIT Request Signal to CPU
8 INT
INTERRUPT Request Signal to CPU
9
Ml
CPU Fetch Cycle Signal
10 BUSDIR
Control Signal for direction of external Data Bus
Select a cartridge and outputs L level from each cartridge
except Memory at the same time when the data are outputted.
11 IORQ I/O Request Signal
12
MERQ
Memory Request Signal
13 WR
Write Timing Signal
14
RD
Read Timing Signal
15 RESET System Reset Signal
16
RESERVED
For furture use
17^32
A0^A15 Address Bus Signal
33^40
D(h»D7
Data Bus Signal
41
GND Ground
42
CLOCK CPU Clock 3.559 MHz
43
GND
Ground
44,46
SW1, SW2
For protect in Connect/Disconnet
45,47 +5 V Powr Source +5 V
48 +12 V Power Source +12 V
49 SUNDIN Sound Input Signal (-5 dbm)
50 -12 V Power Source -12 V
Table 7 Explanation of Signal Lines
- 14 -

MSX uses FSK method for recording, whose 2400 baud and the transfer waveform is
transfer rate supports 1200 baud and shown in the table 8.
Table 8 Data Waveform
Therefore, Interface Circuit must ensure
1200 Hz-4800 Hz transfer.
(i) Input Circuit
C44 o.oo 22 p Cassette I/O Port
5 CMTIN
IC41
UPC311C
COMPARATOR
Fig. 13 Cassette Input Circuit
Input terminal is terminated by the 150
0 resistance whose value is set for
adjusting to the amplifier’s character¬
istic on the cassette. This circuit has
the gain by using OP-Amp. and also the
characteristic as the filter, the wave¬
form characteristic at this time is as
follows.
This circuit uses a high-speed com¬
parator to ensure the reproducing of
4800 Hz waveform. The standard voltage
supplied to the comparator is set to
about 2.5 V by resistance-division. This
voltage is used in the bias voltage at
the © terminal. R54 and R55 let the
circuit have the hysteresis character¬
istic and increase the noise margin.
Fig. 14 Waveform Characteristic in Cas¬
sette Input Circuit
- 15 -

PSG Output
Sound Input Signal
Power Supply Circuit
This circuit using the DROPPER system is
to supply four kinds power of +5 V, -5V,
+12 V and -12 V.
In a primary circuit, there is a line
filter composed of condensers and coils
that is to prevent a malfunction due to
external noises and reduce useless radi¬
ation outward.
In a voltage-regulator circuit of a sec¬
ondary circuit, +5 V circuit consists of
discrete elements and +12 V, -5 V, -12 V
circuits are composed of general
constant-voltage regulator ICs.
(1) Operation of +5 V Voltage-Regulator
Circuit
A voltage that is rectified in full
wave by diodes (D7, D8) and flat¬
tened by electrolytic capacitor (C7)
is applied into a emitter (transis¬
tor Ql). The base current of the
transistor Ql is governed by a tran¬
sistor Q7. The stabilization of the
output voltage is achieved by varing
the base current of the transistor
Ql that is to change Vce of Ql.
This circuit produces a required
reference voltage by dividing +12 V
constant-voltage output with resist¬
ances R5, VR1 and R80, that is,
enables to vary an output voltage by
adjusting a value of VR1 (voltage-
dividing ratio).
The detection of errors between the
reference and output voltages is
made in a differential amplification
circuit of transistors Q8 and Q2.
This control method is as the
following.
®
@
©
+5 V output voltage ascends.
4 -
Base current of the transistor Q8 de¬
creases.
•4
Current flowing into the resistance R1
decreases.
*
Base current of the transistor Q7 de¬
creases.
*
(3;Base current of the transistor Ql de¬
creases.
*
(Dvce of the transistor Ql increase.
(7)Output voltage descends.
When the output voltage descends, the
contrary phenomena to the above
happens—the Vce of the transistor Ql
decreases and the output voltage
increases.
(2) Operation of +12 V Voltage-Regulator
Circuit
A voltage that is rectified in full
wave by diodes (D3, D5) and flat¬
tened by an electrolytic capacitor
CIO is inputted into an input ter¬
minal of a regulator IC (IC1). This
IC1, which is for the constant-
voltage power supply, outputs
stabilized +12 V into an output
terminal. Moreover, this IC can
control the output with an external
signal, but we will describe it in
details later.
18

Main Board
07 01 02,8
2SC1318-Q 2SA1061P 2SA722-S
(3) Operation of -12 V Voltage-Regulator
Circuit
A voltage that is rectified in full
wave by diodes (D4, D6) and flat¬
tened by an electrolytic capacitor
C6 is inputted into an input ter¬
minal of a regulator IC (IC2). This
IC2, which is for the constant-
voltage power, outputs stabilized
-12 V into an output terminal.
(4) Control of Output Voltage with
External Signal
The PSW terminal can control the
output of +5 V and +12 V. When the
PSW terminal is connected with GND,
each voltage is outputted normally,
and when it is open each voltage
becomes about 0 V. (-12 V and -5 V
are left as it is.)
This control is made by transistor
Q9 and IC1. Pin No. 4 in IC1 is a
terminal of which output voltage
becomes about 0 V when current more
than about 500 yA flows. If con¬
trolled this pin externally, it
enables to control +12 V output
voltage. The +5 V output is to be 0
V with +12 V being 0 V, because its
reference voltage is made by divid¬
ing +12 V, as described in (1).
The output voltage control by the Pin
No. 4 in IC1 is as the following.
(1) P SW terminal is connected with GND.
^ ir
(2) Transistor Q9 is cut off.
@ Current of Pin No. 4 in IC1 is near
about 0 V.
(4)Output voltage of IC1 is +12 V.
SW terminal in open:
(1) P SW terminal is opened.
(2) T ransistor Q9 is on.
(3) C urrent of Pin No. 4 in ICl flows.
(4) Output voltage of ICl is about 0 V.
R38 and C38 compose of a time constant
circuit that delays rising +5 V and +12
V. R37 is a resistance for an electric
discharge of C38.
19

Display Screen
Note the following points for an easy to
see screen._
•Depending on the type of TV, the left
and right edges may not be displayed
on the TV screen. This may result
because the display area of the TV and
that of the personal computer are dif¬
ferent. If this is the case, do not
use the shaded part shown in the il¬
lustration. In the text mode, set the
displayed columns using the WIDTH
command to 28-29 (see the "MSX-BASIC
manual"). (It is preset to 37 columns
when the power is turned on.) In the
graphic mode, do not use the 10-16
dots on the left and right sides when
writing a program.
/
p
m 1
1
I
p
1
9
D
■ 9
p
1 l
•
1 ft ♦
»
>=>
i—,—i
This part is cut off.
40-column text mode
8 dots
P #l
»ft
r
ft-
4 =
4 - -ft
s
•
■ f-
•
*
| |
*i!
,
_
32-column text mode
• Do not adjust the screen any brighter
than necessary.
• Exercise care in combining colors when
programming. The screen may be hard to
read due to blurred colors depending
on the combination of the foreground
color (color of characters, etc.) and
the background color. White on blue
(Color 15, 5) is a relatively easy to
distinguish combination. (Color 25, A,
A is set when the power is turned on.)
• The color and volume settings on the
TV for personal computer use are
slightly different from that for TV
broadcast reception. Adjust according¬
ly when switching from a TV broadcast
to the personal computer.
Note 1: Character patterns are displayed
as 8H x 6W dots/character in the
AO-column text display mode
(SCREEN 0). (8H x 8W dots/cha¬
racter in the 32-column text
display mode.) For this reason,
the right side of some graphic
symbols may be cut off when dis¬
played. (Letters and numbers are
always displayed as full charac¬
ters. )
Character Codes
High-order 4 bits (hexadecimal)_ Graphic characters Examples: The character code for A is
4
5
0
,B5
1 ©
- -
2
ft
1 -
3
f
-
4
♦
-
IT
*
r
-
6 ♦
7 • —
8
r
9
A
L
B
O’
T
C
9 x
D
J*
/
E
\
F
ft
+-
Reference: Correspondence between deci¬
mal and hexadecimal numbers.
&HAl=16xA+l=65 (Decimal)
Input and output of Graphic Symbols
Graphic symbols are input and output by
adding a graphic header (&H01).
For example, to input and output "EH"
the graphic header is used as follows.
Input from the keyboard: Two bytes, &H01
and &HAA, are input.
Output to the TV or printer: Two bytes,
&H01 and &HAA, are output.
Example: To output to a TV:
PRINT CHR$(1);CHR$ (&HAA);
Decimal
0—9 10 11 12 13
14
15 16 17 18 31 32 33
63
64
255
Hexadecimal 0-9 A B
° 1
D ' E
L
10 11 , IF 20
21
3F 40 FF
In other words, X 2 XJ (hexadecimal)
s^xlb+Xj (decimal).
Examples: &HlF=lxl6+15=31 (decimal)
&HFF=15x16+15=255 (decimal)
- 20 -

Self Test
|l. Outline of Self Test|
This Self Test Program is prepared for
the purpose of testing hardware func¬
tions of Personal Computer CF-2700. This
program is to start at the 8000H address
and materials in 16 KB ROM is supplied
through the slot.
|2. Self Test Program]
This program is made up of two main
CHECK parts.
1) The first CHECK part — for basic checks.
(1) Check the diagnostic program on.
Make sure that this program is
started correctly.
(2) VDP/VRAM basic check
Check if the interrupt flag is
correctly set or reset (between
CPU - VPD), and the Read/Write of
VRAM (CPU - VDP - VRAM) is done
correctly.
(3) Printer basic check
Check if the printer is connected
properly and can print out
checked results.
(4) RAM check
Check if data are correctly
written in a specified address.
(5) PSG check
Check if the Read/Write of PSG
register (CPU - PSG) and the data
input/output of I/O port (PSG -
PSG) are made correctly.
(6) Key input check
Check if the key input works correctly.
2) The second CHECK part — for checks
including external peripheral equipment.
(7) ROM check
Check if the interpreter operates
correctly.
(8) Screen display check
Check if the screen displays correctly.
(9) Cassette I/O check
Check if signals are inputted/
outputted correctly.
(10) Joystick input check
Check if the joystick sends its
signals correctly by operating it.
(11) Print out check
Check if the printer is sent the
correct print out data.
(12) Audio output check
Check if the audio sound is
outputted properly.
|3. Self Test Procedure 1
1) Equipment required
(1) Test Personal Computer,
Model No. : CF-2700. 1 unit
(2) Printer or Plotter
(designed for MSX). 1 unit
(3) Joystick
Model No.: CF-2201. 1 unit
(4) TV. 1 unit
(5) Test Cartridge
Part No.: DFWV95C0001. 1 pc.
(6) Cassette Tape Recorder. 1 unit
(7) Cassette Tape. 1 pc.
(1) Connection should be made as shown
above.
(2) Feed the paper into the printer.
C3) Use a printer designed for MSX. Any
printers and plotters can be
whichever conform to the Centronics
specifications. However, printers
not designed for MSX can not print
the MSX characters and symbols.
(4) Insert the Test ROM cartridge (facing
a label side to you) into the slot.
(5) Keep the cassette tape recorder away
from the TV (at least 30 cm).
Since regular cassette tape recor¬
ders are for audio use, some are not
suitable for the Self Test due to
different audio characteristics.
-21

-22
VRAM,
BUS
line
CPU
-
VDP
IBasic
check
on
Printer]
Printer
circuit,
terminals
cables,
and
printer