Panasonic CF-2700 User manual

ORDER NO. IED84113035C2
Service Manual
MSX
Personal Computer
CF-2700
Specifications
Microprocessor . Z-80A
Memory . ROM 32 K bytes (MSX-BASIC)
Main RAM 64K.bytes
Video RAM 16K bytes
Video system
Controller .
Number of displayable characters
Number of displayable dots .
Output signals .
Sound system
Controller .
Functions .
Keyboard .
Cassette tape interface
System .
Transfer rate .
I/O ports
Slot .
Printer port .
General port .
Sound output ..
Dimensions and Weight (Main unit)
Power requirements
Voltage .
Power consumption .
TMS 9929A
32 characters x 24 lines
8 (H) x 8 (W) dots/character mode
40 characters x 24 lines
8 (H) x 6 (W) dots/character mode
256 (H) x 192 (V) dots
Video output, RF output
AY-3-8910A
8 octave, 3 chord output
73 keys
FSK
1200/2400 baud
2 (comforms to MSX specifications)
1, 14-pin
2, 9-pin each
1
436 (W) x 245 (D) x 90 (H) mm
approx. 3.6 kg
220 V, 50 Hz
(Only for UK 240 V, 50 Hz)
28 W
Design and Specifications are subject to change without notice.
Panasonic
Matsushita Electric Trading Co., Ltd.
P.O. Box 288, Central Osaka Japan

CONTENTS
Location of Controls and Components . 3
Memory Map . 5
I/O Map . 5
General for Peripheral Circuit . 7
Display Screen, Character Codes . 20
Self Test . 21
Block Diagram . 33
Disassembly Instructions . 34
Adjustment . 39
Connector Pin Connection . 40
Wiring Connection Diagram . 42
Schematic Diagram (Main Board) . 43
Printed Circuit Board (Main Board) . 47
Schematic Diagram & Printed Circuit Board (Power Source) . 49
Schematic Diagram (Video Board) . 50
Printed Circuit Board (Video Board) . 51
Printed Circuit Board (Keyboard) . 52
IC Block Diagram . 53
Parts Location . 62
Parts Location (Keyboard) . 63
Packing Instruction . 64
Replacement Parts List . 64
Copyright Matsushita Electric Industrial
Co., Ltd. 1984
The EE3 system realizes software
compatibility between personal
computers. is a trademark of
Microsoft Corporation.
IMPORTANT (FOR U.K.)
The wires in the mains lead are coloured
in accordance with the following codes:
Blue: Neutral Brown: Live
As the colours of the wires in the mains
lead of this apparatus may not
correspond with the coloured markings
identifying the terminals in your plug,
proceed as follows:
•The wire which is coloured blue must be
connected to the terminal which is
marked with the letter N or coloured
black.
•The wire which is coloured brown. must
be connected to the terminal which is
marked with the letter L or coloured
red.
Notes:
•Disconnect the mains plug from the
supply socket when not in use.
•Do not remove cover. Live parts inside.

(located on
the left side)
I fctr-i
ON POWER
o
OFF

(T^Function keys
Key used for easy inputs of pre¬
defined character strings.
( 2 )Power indicator
Lights when the power switch is
turned on and goes out when the
power is turned off.
(14) Sound output jack
Audio (sound) signal
Connects to the TV
terminal.
output
audio
jack.
input
(l5) Video output jack
Video signal output jack. Connects
to the TV video input terminal.
(3) S pecial keys
Keys used to select, correct, and
edit input characters, and control
program execution.
(16) RF output jack
RF signal output jack,
the TV antenna terminal.
Connects
to
( 4 )Space bar
Bar used to input a space between
characters.
(3) Character keys
Keys used to input characters.
(17) Channel adjust trimmer
After connecting the TV and
computer, turn on the power switch.
Set the TV to UHF channels 35-37.
Insert the adjustment screwdriver
into the channel adjust trimmer and
adjust for a clear picture.
(6)Cursor keys
Keys used to move the cursor.
(7) (¥) General port 1, General port 2
Connectors used to connect
joysticks, tablets, etc.
(18) Power switch
Power turns on when set to "ON" and
the power indicator lights up. Power
turns off when set to "OFF".
, 9;(10) Slot 1. Slot 2
Slots for MSX cartridges.
(ll)Printer connector
Connector used to connect a printer,
plotter, etc.
(l2) C assette Input/Output Connector
Connector used to connect a cassette
tape recorder.
(13) P ower cord
- 4 -

Memory Map (when using BASIC)
Address in hexadecimal
0000
ROM
area
8000
User
area
RAM
area
F380
FFFF
MSX BASIC
ROM
Program area
(text area)
Variable area
Array variable area
Free area
Stack area
Character string area
File control block
(User reserve area)
Work area
(system area)
I/O Map
Area storing the program to which line
numbers have been added.
Area for variables. For character
variables, this area stores the
pointer which points to the character
string (string descriptor).
Area for array variables. If the array
variables are of the character type,
this area stores the pointer which
points to the string in the string area.
This area is allocated when the DIM
statement is executed and an array with
a subscript of 10 or less is used.
The free area is an unused area. The
size of the free area is the size of
the user area minus the sizes of the
character area, stack area, variable
area, and program area. The size of
the free area can be obtained by the
FRE function.
Stack area storing the return address
for BASIC when the FOR-NEXT statement
or GOSUB statement is executed.
Area storing the strings contained in
the character variables and array
variables. The size of the string area
is as specified in the CLEAR
statement. If no size is specified in
the CLEAR statement, an area of 200
bytes is allocated.
Area used during the input and output
of files. This area is allocated
according to the number specified in
the MAXFILES statement.
The high limit address can be set in
the CLEAR statement to F380 or below
so that an area (such as for machine
language subroutines) can be allocated
up until the work area for free use by
the user.
Work area used by BASIC.
Port Bit I/O
Signal Name
Description
A
0
ffH
IB
Specifies the slot number for addresses
1
&H0-&H3FF
mm
Specifies the slot number for addresses
&H4000-&H7FFF
■
Specifies the slot number for addresses
5
&H8000-&H8FFF
6
Specifies the slot number for addresses
7
MB
'If • &HC000-&HFFFF
B
||
Keyboard return signal
C
SK
KB0, KB1
KB2, KB3
Keyboard scan signal
Cassette control (ON when L)
5
Cassette write signal
6
CAPS lamp signal (lights when L)
7
SOUND
Software controlled sound output
- 5 -

I/O Address Assignment
I/O address
(hexadecimal)
00
80
90
98
AO
A8
BO
CO
DO
D8
FF
■ RS-232C
Printer
VDP
(9929A)
PSG
(AY-3-8910A)
PP1
(8255)
I/O address
R/W
Contents Remarks
&H98
W
Data write to the video
RAM
R
Data read from the video
RAM
&H99
W
Command, address set
R
Status read
&HA0 W
Address latch
&HA1 w
Data write
&HA2
R Data read
&HA8
W Port A data write
R
Port A data read
&HA9
W Port B data write
R Port B data read
&HAA W Port C data write
R Port C data read
&HAB W Mode set
&H90 W
Strobe output (bO)
Latch output
R
Status input (bl)
"l” when busy
&H91
W
Print data
Latch output
•The I/O address with the ■ mark are provided to optional equipment.
•For details on the VDP, PSG, and PPI, see their respective manuals.
•Addresses &H40-&HFF represent the system reserve area.
PSG Bit Assignment
Port Bit
I/O
Bit 6 at Port B
Connector Pin Number
A 0
Input
Low level
High level
Port 1 pin 1
Port 2 pin 1
1
Low level
High level
Port 1 pin 2
Port 2 pin 2
2
Low level
High level
Port 1 pin 3
Port 2 pin 3
3
Low level
High level
Port 1 pin 4
Port 2 pin 4
4
Low level
High level
Port 1 pin 6
Port 2 pin 6
5
Low level
High level
Port 1 pin 7
Port 2 pin 7
6
Keymatrix assignment input (low level)
7 CSAR (Read signal of the cassette tape)
B
0
Output
Port 1 pin 6
1
Port 1 pin 7
_
► Note 2
2 Port 2 pin 6
3
Port 2 pin 7 J
4
Port 1 pin 8
5 Port 2 pin 8
6 Input select of port A
7
Note 1: Either port 1 or 2 is selected by the output level of bit 6 at port B.
Writing a "1" to bit 6 at port B ■ + ■ high level output port 2 selected.
Writing a "0" to bit 6 at port B low level output port 1 selected.
Note 2: Be sure to output a high level at these pins if portB is to be used for input.
- 6 -

General for Peripheral Circuit
CPU (Central Processing Unit) Peripheral
Circuit
CPU Peripheral Circuit consists of CPU,
Clock Generator Circuit and Reset
Circuit.
Z80A (pPD780C-l, IC8) is used as CPU. An
interruption system is maskable inter¬
rupt, not non-maskable. AND signals of
VDP's INT and an external interrupt are
fed to INT terminal. In Ml cycle, 1 WAIT
is inserted, and external WAIT is ac¬
cepted asynchronously with CLOCK signal.
BUSRQ and BUSAK are not used, neither
DMA function.
Fig. 1 CPU Peripheral Circuit
The CLOCK Generator Circuit—Serial Os¬
cillation Circuit of 74HC04 (IC43)--
oscillates 10.6781522 MHz to generate
VDP CLOCK and, at the same time, gener¬
ates CPU CLOCK in the circuit of 74LS74
(IC42) and 74LS107 (IC47) which divides
VDP CLOCK by 3 to get 3.559384 MHz.
Moreover, CLOCK Generator Circuit di¬
vides CPU CLOCK into halves to get
1.779462 MHz by 74LS74 (IC39) and gen¬
erates PSG CLOCK.
CPU CLOCK -
3.55938MH!
IIC8.PIN6I
PSG CLOCK
1.77946 MHz
I1C 39. PIN 8: -
Fig. 2 CLOCK Waveform
The Reset Circuit utilizes the charge of
CR Circuit (C13 and R26), but it takes
too much time to raise RESET signal by
only the CR. So the circuit is compul¬
sively raised by Q10, when each end of C
becomes about 1.5 V. Therefore, RESET
signal changes "L" into "H" in 60 ms
after power source ON.
POWER SOURCE
RESET
A
I i i i—i—i—i—i—i—i—i-
0 50 100 (ms)
Fig. 3 RESET Signal
IROM ~~|
This system uses 32 K x 8 bits MASK ROM
(IC32, MN23257) which builds in the MSX
BASIC. CS is connected to SLTO, and 0E
to A15. Access time is available up to

Main Memory Peripheral Circuit
Main Memory Peripheral Circuit consists
of Main Memory and Memory Access Cir¬
cuit.
The Main Memory has a 64 KB memory space
by using eight 16 K x 8-bit DRAMs. Re¬
fresh is performed by RAS-ONLY REFRESH.
Because RAS pre-charge time in refresh¬
ing Ml cycle is ensured to be 100 ns by
Timing Chart, the access time of RAM
must be 150 ns. In the Memory Access
Circ uit, RAS is generated by MERQ or
RESH and CLOCK. The switchover of the
row address to the column address is
done by the multiplexer 74LS157 and CAS
is generated by being staggered the
time, with the condenser C35, when the
column address is outputted. C35 ensures
that the CAS will be "L", considering
differences of the output timing of
74LS157, after the switchover of the row
address to the column address.
WE is gen erated by BWR, and OE by BRD.
RAS, CAS, WE and OE protect from the
undershoot by being inserted a resist¬
ance for the damping.
All of Input/Output with external
equipment are done through I/O ports in
this system, and an access signal of
each port is generated in this circuit.
I/O Select Peripheral Circuit consists
of I/O Select Generator Circuit, Chip
Access Signal Generator Circuit and
Short Write Generating Circuit.
Fig. 6 I/O Select Peripheral Circuit
I/O Select Peripheral Circuit
- 8 -

I/O Select Generator Circuit generates
I/O Select signal according to the I/O
map. This signal is generated through
high-order five bits in low-order byte
of Address Bus and through BIORQ and
Multiplexer 74LS138 (IC25). In order to
ensure data stabilizing time when PSG is
engaged in WRITE, and to be considered
that the output delay time is 350 ns
when PPI is in WRITE, WRITE signal is
raised faster by Short Write Generator
Circuit.
Chip Access Generator Circuit ge nerates
CSW/CSR (VDP Access signals), P P IWR/
PPIRD (PPI Access signals) and BCl/BDIR
(PSG Access_signa ls) from I/O Select
signal and BWR/BRD/SWR.
Automatic refreshing function of VRAM
Composite video output, in PAL system
Interruptible in every frame
Automatic processing of the sprite
screen.
This system uses TI s TMS9929A as CRTC.
This LSI’s features are as follows.
. 256 x 192 pixels resolution
. Used 4,8 and 16 KB as VRAM (16 KB is
used in MSX.)
Table 1 Screen Mode of VDP.
A VDP's operation depends on values of 9 READ and WRITE, VDP resistor or VRAM. In
registers in VDP and a table on VRAM. "L", VRAM is the candidate. AO is con-
VDP has three control signals which are nected to MODE terminal. CSR i s gener-
CSW, CSR and MODE. MODE signal distin- ated by Inverted N AND of CSVDP and RD,
guishes which should be a candidate for and CSW is by OR of CSVDP and WR.
Fig. 7 VDP Peripheral Circuit Diagram
- 9 -

PSG (Programmable Sound Generator)
Peripheral Circuit
PSG Block consists of PSG and General
Port Circuit. This system uses GI's
AY-3-8910A as PSG, which makes it enable
to produce 8 octaves, triple chords and
noise-sound effects. This LSI builds in
a tone generator, a noise generator, an
envelope generator and 16 registers
whose each value decides the frequency
and the volume of the sound by software.
This LSI has also two I/O ports which
are available for Input/Output with
General Port, Keyboard Control and input
to a cassette tape recorder. In this
occasion, each bit in port A/B is
assigned as the following table.
'-'1
I/O
Function
Input
PORT 1-1 PORT 2-1
10 A1 PORT 1-2 PORT 2-2
10 A2
PORT 1-3 PORT 2-3
10 A3
PORT 1-4 PORT 2-4
10 A4 PORT 1-6 PORT 2-6
10 A5 PORT 1-7 PORT 2-7
10 A6
Input specifying the layout of Keyboard
10 A7
Read signal input from a cassette tape recorder
10 B0
Output
P0RT1
10 Bl
PORT1
10 B2
P0RT2
10 B3
P0RT2
10 B4 P0RT1
10 B5
PORT2
10 B6 Selecting input of PORT A "L"=P0RT 1 "H"=P0RT 2
10 B7
Table 2 Bit-Assignment in PSG Port
PSG has three control lines—BDIR, BC1 Input/Output are shown as the following
and BC2—, whose control signals in table.
BDIR
BC1
BC2 State
0
0 1
Not Selected
0
1 1
Readout from PSG
1
0
1
Writing in PSG
1
1 1
Address latch
Table 3 PSG Control Signal
- 10 -