Pentek 6230 User manual

Pentek Model 6230/6231 Operating Manual Page 1
Manual Part No: 800.62300 Rev: C.1 − October 23, 2006
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
(201) 818−5900
http://www.pentek.com
Copyright © 2006
OPERATING MANUAL
MODEL 6230/6231
32/16−Channel Digital Receiver VIM Module
for Pentek VIM Baseboards

Page 2 Pentek Model 6230/6231 Operating Manual
Manual Revision History
Warranty
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in mate−
rials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the
service conditions for which they were furnished.
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product
that in Pentek’s sole opinion proves to be defective within the scope of the warranty. Pentek must be notified in writing of the defect or
nonconformity within the warranty period and the affected product returned to Pentek within thirty days after discovery of such defect or
nonconformity.
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service. Pentek shall pay
for the return of products to buyer except for products returned from another country.
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect,
inadequate maintenance, or accident, or for any product that has been repaired or altered by anyone other than Pentek or its authorized
representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or
implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct, indi−
rect, special, incidental, or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any
other legal theory.
Copyrights
With the exceptionofthoseitems listed below, the contentsof this publication arecopyright©2006,Pentek,Inc.
All Rights Reserved. Contents of this publication may not be reproduced in any form without written permission.
Appendix B, AD6644 Datasheet, is the copyrighted property of Analog Devices, Inc., Norwood MA
Appendix C, Graychip GC4016 Datasheet, is the copyrighted property of Graychip, Inc., Palo Alto, CA
Appendix D, ADM1024 Datasheet, is the copyrighted property of Analog Devices, Inc., Norwood MA.
Trademarks
Pentek, GateFlow, ReadyFlow, and VIM are registered trademarks or trademarks of Pentek, Inc.
VxWorks is a registered trademark of Wind River Systems, Inc. Xilinx and Virtex are registered trademarks or trademarks of Xilinx, Inc.
Date Manual Rev Comments
6/8/01 Preliminary Initial product release.
1/31/02 A Added instructions for programming ADM1024, Sect 3.6. Added channel number coding
for Channel Tag in output format, Section 4.2, per KB Case 972. Added detailed installation
instructions for Option 102, Sect 2.3. Removed Virtex−E FPGA Appendix—data is in FPGA
Design Kit, Part #49530−250. Added Input Offset Error Specifications, per KB case 1016.
6/14/02 A.1 Added notes on Real mode output from GC4016s in DDR modes, Sect 4.2, per KBcase 1073.
9/26/02 A.2 Added note on Reset hold time, Sect 3.7, per KBcase 961.
12/16/02 A.3 Added board weight, Sect 1.11, per KBcase 1137. Corrected installation instructions, Sect 2.3,
per KBcase 1138. Corrected FPGA mating connector ERNI part #, Sect 2.4.5, per KBcase 1129.
2/24/03 A.4 Corrected Sync/Gate & FPGA connector part numbers, Sect 2.4.3 and 2.4.5, per KBcase 1155.
3/4/03 A.5 Corrected DDR Bypass mode descriptions, Sect 4.2.1 and 4.2.2.
5/21/03 B Added Option 105 information.
6/6/03 B.1 Corrected Configuration Data Register to Write Only, Sect 3.4.
7/15/03 B.2 Added VME baseboards, Sect 1.1, added Support Software Sect 1.11, corrected Model 4205
base addresses, Sect 3.2.
10/15/03 B.3 Corrected footnotes for register power−up states, Tables 3−5, 3−19, 3−20, 3−23, 3−26, 3−27.
Added comment that input channel data goes only to associated BIFO for Bypass modes,
Sect 4.2.1 & 4.2.2, per KBcase 1153. Moved Timing & Sync to new Chapter 5.
6/25/04 B.4 Added note about more samples than trigger length , Sect 3.11, per KBcase 1161.
1/14/05 C Updated Power Specifications, Sect 1.12.
10/23/06 C.1 Added Environmental Specifications, Sect 1.12. Updated ERNI conector part numbers, Sect
2.4.3 & 2.4.5, per KBCase 1308.
Printed in the United States of America.

Pentek Model 6230/6231 Operating Manual Page 3
Page
Table of Contents
Rev.: B.4
Chapter 1: Introduction
1.1 General Description..............................................................................................................................9
1.2 Features ..................................................................................................................................................9
1.3 Analog/Digital Conversion ..............................................................................................................10
1.4 Digital Receivers .................................................................................................................................10
1.5 Digital Interfaces.................................................................................................................................10
1.6 Timing and Synchronization.............................................................................................................11
1.7 Interrupts .............................................................................................................................................11
1.8 VIM Interface.......................................................................................................................................11
1.9 Block Diagrams ...................................................................................................................................12
igure 1−1: Model 6230 Block Diagram.........................................................................................12
igure 1−2: Model 6231 Block Diagram.........................................................................................12
igure 1−3: Model 6230 Block Diagram, with Option 105.........................................................13
igure 1−4: Model 6231 Block Diagram, with Option 105.........................................................13
1.9.1 Channels .............................................................................................................................14
1.10 FPGA Configuration ..........................................................................................................................15
1.10.1 Model 6230 .........................................................................................................................16
igure 1−5: Model 6230 PGA Interconnectivity .......................................................16
1.10.2 Model 6231 .........................................................................................................................17
igure 1−6: Model 6231 PGA Interconnectivity .......................................................17
1.11 Board Support Software ....................................................................................................................17
1.12 Specifications.......................................................................................................................................18
Chapter 2: Installation and Connections
2.1 Inspection.............................................................................................................................................21
2.2 Jumper Block Settings ........................................................................................................................21
2.2.1 Analog Input Filter Bypass Jumpers (without Option 105) .......................................21
Table 2−1: Analog Input ilter Bypass Jumpers.........................................................21
2.2.2 FPGA Configuration Data Source Jumper ....................................................................22
Table 2−2: PGA Configuration Data Source Jumper ..............................................22
2.2.3 External TTL Inputs Select Jumpers ..............................................................................22
Table 2−3: External TTL Inputs Select Jumpers .........................................................22
igure 2−1: Model 6230 PCB Assembly, Component Side ........................................................23
igure 2−2: Model 6231 PCB Assembly, Component Side ........................................................24
igure 2−3: Model 6231 Option 102 PCB Assembly, Component Side...................................24

Page 4 Pentek Model 6230/6231 Operating Manual
Page
Table of Contents
Rev.: B.4
Chapter 2: Installation and Connections (continued)
2.3 Installing the Model 6230/6231 on a VIM Baseboard................................................................... 25
igure 2−4: Typical VIM Baseboard − Connectors & Mounting Holes ................................. 26
2.3.1 Installing Model 6230, or Model 6231 without Option 102 ........................................ 27
igure 2−5: VIM−4 Panel Mounting & Shipping Screws ........................................ 27
igure 2−6: VIM Module Nylon Spacer....................................................................... 28
igure 2−7: VIM Baseboard Blank Panel Screws....................................................... 28
2.3.2 Installing Model 6231 with Option 102 ......................................................................... 30
igure 2−8: Model 6231 with Option 102 Shipping Assembly................................ 30
igure 2−9: VIM Module Nylon Spacer....................................................................... 31
igure 2−10: VIM Baseboard Blank Panel Screws..................................................... 31
igure 2−11: Option 102 ront Panel Assembly ......................................................... 32
igure 2−12: VIM Baseboard with Option 102 ront Panel Assembly.................. 33
igure 2−13: Option 102 Stacking Connectors on VIM Module............................. 33
igure 2−14: Option 102 PCB Mounted on VIM Module......................................... 34
2.4 Front Panel Connections ................................................................................................................... 35
2.4.1 Analog Input Connectors ................................................................................................ 35
2.4.2 Sample Clock Input Connector ...................................................................................... 35
igure 2−15: Models 6230 and 6231 ront Panels ........................................................................ 36
2.4.3 Sync/Gate Connector ...................................................................................................... 37
Table 2−4: SYNC/GATE Connector Pins..................................................................... 37
2.4.4 Sync/Gate Header ........................................................................................................... 37
Table 2−5: SYNC/GATE/TRG Header Pins ................................................................ 37
2.4.5 FPGA Connector .............................................................................................................. 38
Table 2−6: PGA Connector Pins.................................................................................. 38
2.5 Front Panel LEDs................................................................................................................................ 39
2.5.1 Clock (CLK) LED .............................................................................................................. 39
2.5.2 Over Temperature (TEMP) LED .................................................................................... 39
2.5.3 Master (MAS) LED ........................................................................................................... 39
2.5.4 Terminate (TRM) LED ..................................................................................................... 39
2.5.5 Overload (OVLD CHn) LEDs ......................................................................................... 39

Pentek Model 6230/6231 Operating Manual Page 5
Page
Table of Contents
Rev.: B.4
Chapter 3: Memory Maps and Register Descriptions
3.1 Overview..............................................................................................................................................41
3.2 Model 6230/6231 Memory Map.......................................................................................................41
Table 3−1: VIM Base Addresses for Models 4290 to 4295 VIM Baseboards ..........................41
Table 3−2: VIM Base Addresses for Model 4205 VIM Baseboards .........................................41
Table 3−3: Model 6230/6231 Memory Map ...................................................................................42
3.3 Virtex Config Register........................................................................................................................43
Table 3−4: Virtex Config Register ..................................................................................................43
3.3.1 RITE ................................................................................................................................43
3.3.2 BUSY ...................................................................................................................................43
3.3.3 INIT .....................................................................................................................................43
3.3.4 DONE .................................................................................................................................44
3.3.5 PRGM .................................................................................................................................44
3.3.6 LD SRC ...............................................................................................................................44
3.4 Virtex Config Data Register ..............................................................................................................44
Table 3−5: Virtex Config Data Register.........................................................................................44
3.5 ait States Register............................................................................................................................45
Table 3−6: Wait States Register.......................................................................................................45
3.6 Hardware Monitor Port Register......................................................................................................46
Table 3−7: Hardware Monitor Port Register ................................................................................46
Table 3−8: ADM1024 Registers.......................................................................................................47
3.7 Master Control Register.....................................................................................................................48
Table 3−9: Master Control Register................................................................................................48
3.7.1 RESET .................................................................................................................................48
3.7.2 SYNC SRC ..........................................................................................................................48
3.7.3 SYNC POL .........................................................................................................................49
3.7.4 EXT SYNC EN ...................................................................................................................49
3.7.5 MCLK DIVn .......................................................................................................................49
3.7.6 CLK SRC SEL ....................................................................................................................49
3.7.7 OSC DSBL ..........................................................................................................................49
3.7.8 EXT CLK ............................................................................................................................50
3.7.9 TERM ..................................................................................................................................50
3.7.10 MASTR ...............................................................................................................................50
3.8 Bypass Rate Divide Register .............................................................................................................51
Table 3−10: Bypass Rate Divide Register .....................................................................................51
3.9 Channel Enable Register....................................................................................................................52
Table 3−11: Channel Enable Register............................................................................................52
Table 3−12: Register Bit Channel Assignments...........................................................................52
3.10 Gate Control Register.........................................................................................................................53
Table 3−13: Gate Control Register..................................................................................................53
3.10.1 INT EDGE x .......................................................................................................................53
3.10.2 GATE POL .........................................................................................................................54
3.10.3 GATE SELn ........................................................................................................................54

Page 6 Pentek Model 6230/6231 Operating Manual
Page
Table of Contents
Rev.: B.4
Chapter 3: Memory Maps and Register Descriptions
3.10.4 GATE DISBL ..................................................................................................................... 54
3.10.5 GATE SRC ......................................................................................................................... 54
3.10.6 TRIG CLEAR ..................................................................................................................... 54
3.10.7 HOLD MODE ................................................................................................................... 55
3.10.8 GATE/TRIG ...................................................................................................................... 55
3.10.9 EXT GATE ......................................................................................................................... 55
3.11 Trigger Length Register..................................................................................................................... 56
Table 3−14: Trigger Length Register .............................................................................................56
3.12 Channel Control Register.................................................................................................................. 57
Table 3−15: Channel Control Register .......................................................................................... 57
3.12.1 RESET ................................................................................................................................. 57
3.12.2 DIV RST EN ...................................................................................................................... 57
3.12.3 FMTR EN ........................................................................................................................... 57
3.12.4 DAT MODEn .................................................................................................................... 58
3.13 Sync/Gate Generator Register ......................................................................................................... 59
Table 3−16: Sync/Gate Generator Register................................................................................... 59
3.13.1 FIFO GATE ........................................................................................................................ 59
3.13.2 SYNC .................................................................................................................................. 59
3.14 Interrupt Mask Register .................................................................................................................... 60
Table 3−17: Interrupt Mask Register.............................................................................................60
Table 3−18: Interrupt Register Bits................................................................................................ 61
3.15 Interrupt Flag Register ...................................................................................................................... 62
Table 3−19: Interrupt lag Register ............................................................................................... 62
3.16 Interrupt Status Register ................................................................................................................... 63
Table 3−20: Interrupt Status Register............................................................................................ 63
3.17 Semaphore Register ........................................................................................................................... 64
Table 3−21: Semaphore Register .................................................................................................... 64
3.18 I/O Direction 2 Register (Model 6231 only)................................................................................... 65
Table 3−22: I/O Direction 2 Register (Model 6231 Option 102 only) ...................................... 65
3.19 I/O Data 2 Register (Model 6231 only)........................................................................................... 66
Table 3−23: I/O Data 2 Register (Model 6231 Option 102 only) ............................................... 66
3.20 I/O Direction Register....................................................................................................................... 67
Table 3−24: I/O Direction Register ................................................................................................ 67
3.21 I/O Enable Register ........................................................................................................................... 68
Table 3−25: I/O Enable Register ..................................................................................................... 68
3.21.1 I/O EN1 ............................................................................................................................. 68
3.21.2 I/O EN2 ............................................................................................................................. 68
3.22 I/O Data Register............................................................................................................................... 69
Table 3−26: I/O Data Register ......................................................................................................... 69
3.23 Graychip 0 & 1 Registers................................................................................................................... 70
Table 3−27: Graychip 0 & 1 Registers............................................................................................70
Table 3−28: Processor/Graychip Register Sets............................................................................. 70

Pentek Model 6230/6231 Operating Manual Page 7
Page
Table of Contents
Rev.: B.4
Chapter : Data Formatting and Routing
4.1 Overview..............................................................................................................................................71
4.2 Data Routing and Formats ................................................................................................................71
4.2.1 DDR Bypass Mode, A/D Data, Unpacked (001) ..........................................................72
Table 4−1: Output Data ormat − DDR Bypass Mode, Unpacked .........................72
4.2.2 DDR Bypass Mode, A/D Data, Time Packed (010) .....................................................72
Table 4−2: Output Data ormat − DDR Bypass Mode, Time Packed ....................72
4.2.3 DDR Bypass Mode, A/D Data, Channel Packed (011) ...............................................73
Table 4−3: Output Data ormat − DDR Bypass Mode, Channel Packed ..............73
4.2.4 DDR Mode, 16−Bit, Unpacked I/Q, Tagged (100) .......................................................74
Table 4−4: Output Data ormat − DDR Mode, 16−bit, Unpacked I/Q, Tagged...74
4.2.5 DDR Mode, 24−Bit, Unpacked I/Q, Tagged (101) .......................................................75
Table 4−5: Output Data ormat − DDR Mode, 24−bit, Unpacked I/Q, Tagged...75
4.2.6 DDR Mode, 16−Bit, Packed I/Q (110) ...........................................................................76
Table 4−6: Output Data ormat − DDR Mode, 16−bit, Packed I/Q ........................76
4.2.7 DDR Mode, 24−Bit, Packed I/Q (111) ...........................................................................77
Table 4−7: Output Data ormat − DDR Mode, 16−bit, Packed I/Q ........................77
Chapter 5: Timing and Synchronization
5.1 Overview..............................................................................................................................................79
igure 5−1: Model 6230 Gate/Sync/Clock Logic ..........................................................................79
igure 5−2: Model 6231 Gate/Sync/Clock Logic ..........................................................................80
5.2 Sync.......................................................................................................................................................80
5.3 Clock.....................................................................................................................................................80
5.4 Gates .....................................................................................................................................................81

Page 8 Pentek Model 6230/6231 Operating Manual
Page
Table of Contents
Rev.: B.4
Appendix A: Configuration EEPROM Format
A.1 Introduction .....................................................................................................................................A−1
A.2 EEPROM Format Example ............................................................................................................A−1
Table A−1: VIM ID EEPROM Register......................................................................................A−1
Table A−2: EEPROM Example (Model 6230 shown)...............................................................A−2
Appendix B: Analog Devices AD66 A/D Converter
B.1 Introduction ..................................................................................................................................... B−1
Appendix C: Graychip GC 016 Digital Receiver
C.1 Introduction .....................................................................................................................................C−1
Appendix D: Analog Devices ADM102 System Hardware Monitor
D.1 Introduction .....................................................................................................................................D−1

Pentek Model 6230/6231 Operating Manual Page 9
Rev.: B.4
Chapter 1: Introduction
1.1 General Description
The Models 6230 and 6231 are general purpose, narrowband digital receiver VIM®
(Velocity Interface Mezzanine) modules that perform frequency down conversion,
low−pass filtering, and decimation of the digitized input signal. The Model 6230 is a
32−channel VIM−4 module that features four 14−bit, 65−MHz A/D converters, and can
be configured with up to 32 channels of narrowband receivers. The Model 6231 is a
16−channel VIM−2 module, with two 14−bit, 65−MHz A/D converters, and up to 16
channels of narrowband receivers.
The Models 6230 and 6231 attach directly to VIM−compatible baseboards, including the
Pentek Models 4205, and 4290 through 4295 Quad DSP (Digital Signal Processing)
boards.
1.2 eatures
Four 65−MHz, 14−bit A/D converters (Model 6230)
Two 65−MHz, 14−bit A/D converters (Model 6231)
32 channels of narrowband digital receivers (Model 6230)
16 channels of narrowband digital receivers (Model 6231)
All receivers can select any of the A/D inputs
DC to 90−MHz input range (standard models)
300−kHz to 150−MHz input range (Option 105)
DC to 32−MHz center frequency tuning with 0.02−Hz resolution
3.6−kHz to 1.6−MHz output bandwidths
Front panel clock and sync bus can synchronize multiple boards
Direct connection to each VIM processor with no shared bus bottlenecks
Compliant with VIM module specification
Note
In this manual, all specifications and use inst uctions a e p esented in efe ence to
the Model 6230. Whe e a diffe ence exists, the co esponding info mation fo the
Model 6231 is included in b ackets “[...]”.

Page 10 Pentek Model 6230/6231 Operating Manual
Rev.: B.4
1.3 Analog/Digital Conversion
The Model 6230 [Model 6231] accepts four [two] analog RF inputs on front panel SMA
connectors in the range of DC to 90 MHz to support direct IF undersampling. Each
input signal is buffered by an Analog Devices OPA642 amplifier. Low−pass anti−
aliasing filters for each input signal may be individually enabled or bypassed by on−
board jumpers. ith Option 105, the amplifier, filters, and bypass jumpers are
replaced by an RF transformer, and the RF input range is 300 kHz to 150 MHz.
An Analog Devices AD6644 14−bit, 65−MHz A/D converter then digitizes each of the
analog inputs. The A/D converter clock can be driven from an internal 64−MHz crys−
tal oscillator, from an external sample clock supplied through a front panel SMA con−
nector, or from the front panel sync bus.
1.4 Digital Receivers
The Model 6230 [Model 6231] includes eight [four] Graychip GC4016 quad narrowband
digital receiver (DDR) chips. Each GC4016 DDR accepts four [two] 14−bit parallel
inputs from the AD6644 A/D converters. A crossbar switch inside each GC4016 allows
each of the 32 [16] receiver channels on the board to independently select any of the
A/D inputs for flexible switching.
The maximum input sampling rate, s, for the GC4016 is 80 MHz. Each receiver
includes four independently tunable receiver channels capable of tuning throughout
the DC to s/2 range, with output bandwidths ranging from 0.8 · s/N (for the standard
80% FIR filter), where the decimation factor, N, ranges from 32 to 16,384. For an input
sampling clock of 64 MHz, this output bandwidth range becomes approximately
3.1 kHz to 1.6 MHz. Each processor on the VIM baseboard can control all programma−
ble registers on its two associated GC4016s.
1.5 Digital Interfaces
The Model 6230 [Model 6231] contains two [one] Xilinx® Virtex®−E XCV300 FPGAs
(field programmable gate arrays). (These are optionally replaceable by other Virtex
devices in the series up to XCV600.) The FPGAs are factory programmed to implement
the standard data formatting, clocking, and control functions specified in this docu−
ment. Each GC4016 DDR delivers real or complex serial data streams into one FPGA,
where data is formatted and multiplexed for delivery across the VIM interface into the
32−bit parallel Bi−FIFOs (BIFOs) on the VIM baseboard. The AD6644 digital outputs
are also connected directly to each FPGA so that wideband A/D data can be delivered
directly to the DSP board, bypassing the digital receivers.
The user can re−program the Virtex−E FPGAs from the VIM baseboard processors.
This allows the user to implement his own algorithms for special timing requirements
and for pre−processing of AD6644 or GC4016 output data before sending it to the pro−
cessor BIFOs. Refer to Section 1.10, FPGA Configuration, for additional information
about the gate array configurations.

Pentek Model 6230/6231 Operating Manual Page 11
Rev.: B.4
1.6 Timing and Synchronization
A VIM baseboard processor can access all board control and status registers to control
synchronization, gating, triggering, and clocking functions. All VIM baseboard pro−
cessors can generate sync, gate, and trigger signals for distribution on the front panel
LVDS (low−voltage differential signal) sync bus. This sync bus includes sample clock,
gate, and sync signals. It allows one Model 6230/6231 to act as a bus Master, driving
these signals out to a front panel flat cable using LVDS differential signaling. Addi−
tional sync lines on the bus allow synchronization of the local oscillator phase, fre−
quency switching, decimating filter phase, and BIFO data collection on multiple
modules. Up to seven slave 6230/6231 modules can be driven from the bus Master,
supporting synchronous sampling and sync functions across all connected boards. If
the Model 6230/6231 is a bus Master, any of the VIM baseboard processors can create a
sync individually (one at a time) by toggling a bit in a register.
In addition to the LVDS sync bus, the Model 6230/6231 can receive two external input
signals: one TTL sync and one TTL gate or trigger. Refer to Chapter 5, Gate/Sync
Description, for additional information about the use and programming of gate, clock,
and sync signals.
1.7 Interrupts
The Model 6230/6231 has several maskable interrupt sources. Interrupts may be gen−
erated to any of the VIM baseboard processors by the A/D converter overload outputs,
transitions on the gate or sync signals, clock loss, or a programmable over−temperature
or a faulty power supply voltage.
The board’s Voltage/Temperature Monitor, an ADM1024, provides constant monitor−
ing of critical voltages and temperatures on the Model 6230/6231 PCB. This device is
programmable for voltage and temperature limits. If the voltage/temperature fall out−
side of the set limits, an interrupt can be generated.
1.8 VIM Interface
The FPGA outputs are connected directly through the VIM mezzanine interface to the
32−bit synchronous BIFOs on the VIM baseboard, where they are buffered for efficient
block transfers to the processors. Each processor on the VIM baseboard can control all
programmable registers on the associated GC4016s, as well as control and initiate sync
bus functions.

Page 12 Pentek Model 6230/6231 Operating Manual
Rev.: B.4
1.9 Block Diagrams
The following are block diagrams of the Models 6230 and 6231 digital receivers.
BI−
FIFO BI− FIFO
BI−
FIFO BI− FIFO
32 32
32 32
32
16
3232 32
PROC
A PROC C
PROC
B PROC D
VIM Processor Board
Model 6230
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
RF In
Sample
Cloc In
RF In RF In RF In
AD6644
14−BIT A/D
AD6644
14−BIT A/D
AD6644
14−BIT A/D
AD6644
14−BIT A/D
AMPLIFIER AMPLIFIER AMPLIFIER AMPLIFIER
LOW PASS
FILTER
LOW PASS
FILTER
LOW PASS
FILTER
LOW PASS
FILTER
14 14 14 14
CLOCK
GENERATOR/
DIVIDER
Cloc
& Sync
Bus A/D Cloc
Control
Front Panel I/O
ControlControl Control
I&QI&Q I&QI&QI&Q I&QI&Q I&Q
I & Q I & Q
I & Q I & Q
TTL
Sync &
Gate
XTL
OSC.
SYNCHRONIZATION
INTERRUPTS
AND CONTROL
Vi tex−E FPGA Vi tex−E FPGA
16
Front
Panel
I/O
Figure 1−1: Model 6230 Block Diagra
BI−
FIFO BI− FIFO
32 32
32
16
32
PROC
A (o C) PROC B (o D)
VIM Processor Board
Model 6231
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
RF In
Sample
Cloc In
RF In
AD6644
14−BIT A/D
AD6644
14−BIT A/D
AMPLIFIER AMPLIFIER
LOW PASS
FILTER
LOW PASS
FILTER
14 14
CLOCK
GENERATOR/
DIVIDER
Cloc
& Sync
Bus A/D Cloc
Control
Front Panel I/O
(optional)
Control
I&QI&Q I&QI&Q
I & Q
I & Q
TTL
Sync &
Gate
XTL
OSC.
SYNCHRONIZATION
INTERRUPTS
AND CONTROL
Vi tex−E FPGA
Figure 1−2: Model 6231 Block Diagra

Pentek Model 6230/6231 Operating Manual Page 13
Rev.: B.4
1.9 Block Diagrams (continued)
The following are block diagrams of the Models 6230 and 6231 with Option 105.
BI−
FIFO
BI−
FIFO
BI−
FIFO
BI−
FIFO
32 32
32 32
32
16
3232 32
PROC
A PROC C
PROC
B PROC D
VIM Processor Board
Model 6230
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
RF In
Sample
Cloc In RF In RF In RF In
AD6644
14−BIT A/D
AD6644
14−BIT A/D
AD6644
14−BIT A/D
AD6644
14−BIT A/D
RF
TRANSFORMER
RF
TRANSFORMER
RF
TRANSFORMER
RF
TRANSFORMER
14 14 14 14
CLOCK
GENERATOR/
DIVIDER
Cloc
& Sync
Bus A/D Cloc
Control
Front Panel I/O
ControlControl Control
I&QI&Q I&QI&QI&Q I&QI&Q I&Q
I & Q I & Q
I & Q I & Q
TTL
Sync &
Gate
XTL
OSC.
SYNCHRONIZATION
INTERRUPTS
AND CONTROL
Vi tex−E FPGA Vi tex−E FPGA
16
Front
Panel
I/O
Figure 1−3: Model 6230 Block Diagra , with Option 105
BI−
FIFO
BI−
FIFO
32 32
32
16
32
PROC
A (o C) PROC B (o D)
VIM Processor Board
Model 6231
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
GC4016
NARROW−
BAND
DIG. RCVR
4−CH
RF In
Sample
Cloc In RF In
AD6644
14−BIT A/D
AD6644
14−BIT A/D
14 14
CLOCK
GENERATOR/
DIVIDER
Cloc
& Sync
Bus A/D Cloc
Control
Front Panel I/O
(optional)
Control
I&QI&Q I&QI&Q
I & Q
I & Q
TTL
Sync &
Gate
XTL
OSC.
SYNCHRONIZATION
INTERRUPTS
AND CONTROL
Vi tex−E FPGA
RF
TRANSFORMER
RF
TRANSFORMER
Figure 1−4: Model 6231 Block Diagra , with Option 105

Page 14 Pentek Model 6230/6231 Operating Manual
Rev.: B.4
1.9.1 Channels
The following defines the different uses of the term ‘Channel’ in this manual
(refer also to the block diagrams on the prior two pages).
Input Channels — There are four input channels on the Model 6230
[two input channels on the Model 6231], one for each analog RF input
and A/D converter. These are identified as CH1, CH2, CH3, and CH4
for the 6230 [CH1 and CH2 for the 6231]. Each input channel may be
independently selected by any of the receiver channels (below).
Receiver Channels — Each VIM baseboard processor has access to eight
receiver channels, four channels in each of the two Graychip GC4016
DDRs associated with that processor. These are identified as DSP CH1
through DSP CH8, for each processor. Any one of the A/D input
channels (above) may be connected independently to each receiver
channel. Each receiver channel may be individually selected for output
to the VIM Bi−FIFO by the associated processor.
Processor Channels — There are four processor channels on the Model
6230 [two processor channels on the 6231], one for each processor on the
VIM baseboard. These are identified as Processors A, B, C, and D for the
6230 [Processors A and B, or C and D, for the 6231, depending on the
mezzanine position that the module is installed into on the VIM
baseboard]. Each processor channel is associated with (and provides
control for) two GC4106s on the module, and one Bi−FIFO on the VIM
baseboard. Two processor channels are associated with each FPGA
(Processor A controls FPGA1, Processor C controls FPGA2).

Pentek Model 6230/6231 Operating Manual Page 15
Rev.: B.4
1.10 PGA Configuration
The standard FPGAs on the Model 6230/6231 are the Xilinx Virtex−E XCV300E; the
Virtex−E XCV600E models are available as Option 600. The baseline functionality con−
sumes about 60% of the XCV300E or 30% of the XCV600E.
All data from the AD6644 A/D converters and the Graychip GC4016 DDRs pass
through these FPGAs before being fed to the VIM baseboard BIFOs. The Model 6230/
6231 is shipped with a default set of logic functions for the FPGAs, on JTAG−program−
mable serial EEPROMs. Each FPGA has it’s own EEPROM to facilitate two different
programmings. At power−up, this set of default functions is loaded into the FPGAs.
The FPGAs can be configured in several different ways:
• The default method is configuration loading from separate 4−Mbit configuration
EEPROMs. This is the power−up mode of the board. Configuration reload may
also be forced by Processors A and C (see Section 3.3).
• The second method, to facilitate development and debugging, is by serial download
to the FPGAs using a Xilinx download cable. This method will replace the factory−
programmed configuration that loads at power up from the EEPROMs. In this
mode, the FPGAs are chained to accept one download stream, so two different or
identical programs can be strung together in the download bitstream. This method
is volatile and will exist only until the power is turned off.
• The third method is byte−wide upload from Processors A and C. Processor A
configures the first FPGA, and Processor C the second, by writing the configuration
data to the FPGA Configuration Data Register (see Section 3.4). For a Virtex
XCV600E FPGA, approximately 512K bytes on the baseboard are required to hold
the configuration for each FPGA. This method is volatile and will exist only until
the power is turned off.
• The last method is to use the serial EEPROM configuration method, then overwrite
the default configuration by reprogramming each EEPROM from the JTAG
interface. This overwrites the default configuration by reprogramming the
EEPROMs. After turning power off, the FPGAs will power up with this new
configuration instead of the default configuration.
NOTE: This method will permanently overwrite the default configuration supplied
by Pentek. The default configuration is supplied with the available FPGA
Design Kit so that it can be restored if necessary.
Pentek has available GateFlow™ FPGA Design Kits that provide resources for the user
to modify the programmable logic functions for the Virtex−E FPGA. This allows the
user to implement his own algorithms for special timing requirements and for pre−
processing of AD6644 or GC4016 output data. Pentek offers this capability as a sepa−
rate development package, Model 4953 − Option 230 for the 6230, or Model 4953 −
Option 231 for the Model 6231. Contact Pentek at (201) 818−5900 for details about this
package.

Page 16 Pentek Model 6230/6231 Operating Manual
Rev.: B.4
1.10 PGA Configuration (continued)
1.10.1 Model 6230
Some spare pins on the Model 6230 FPGAs are cross−connected to facilitate
user programming or future functionality. The spare pins are broken up
into the following groups:
• The first group of 38 spares is available on either FPGA model. Twelve
pins are connected to a serial port on Processors A and C through a
quick switch, but are disabled in the default configuration (see Note
below). This optional connection allows a path for the two serial ports to
the front panel connector if desired. These spare pins split into two
groups of 19, and are cross−connected so that identical programming
and I/O pin numbers in both FPGAs is possible.
• The second group of 44 spares exists only in the XCV600E model. They
are divided into two groups of 22 pins and cross−connected.
• The third group of 16 pins and two quickswitch enables from each FPGA
go to the front panel FPGA connector (see Section 2.4.5). These are
connected with either FPGA model (XCV300E or XCV600E), and can be
used as either inputs or outputs. The quickswitches and 25−ohm series
resistors provide some over−voltage and short protection to the FPGA
I/O pins. See Section 3.22 for description of this I/O register.
hen the Model 6230 is attached to a Pentek VIM baseboard, the FPGAs
provide serial port connectivity as shown in the following illustration.
Note
The cont ol signals needed to enable connection of se ial po ts A1 and C1 to
the FPGAs a e disabled in the default Model 6230 FPGA configu ation. If
needed, these connections will have to be optionally p og ammed into the
FPGA logic.
VIM Baseboa d
Se ial Po ts
Model 6230
Cont ol Cont ol
Vi tex−E FPGA 1 Vi tex−E FPGA 2
Quick
Switch
Quick
Switch
A0 A1 B0 B1 C0 C1 D0 D1
Figure 1−5: Model 6230 FPGA Interconnectivity

Pentek Model 6230/6231 Operating Manual Page 17
Rev.: B.4
1.10 PGA Configuration (continued)
1.10.2 Model 6231
All spare pins on the Model 6231 FPGA are brought to the front panel FPGA
connector (see Section 2.4.5). These pins are connected with either FPGA
model (XCV300E or XCV600E), and can be used as either inputs or outputs.
See Section 3.22 for description of the associated I/O register.
hen the Model 6231 is attached to a Pentek VIM baseboard, the FPGA
provides serial port connectivity as shown in the following illustration.
1.11 Board Support Software
Pentek’s Model 4999 ReadyFlow® Board Support Libraries allow high−level program−
ming to speed development tasks. Refer to the ReadyFlow software documentation for
the Model 6230/6231 (Pentek part #801.62300) for further description of these capabili−
ties.
Pentek’s Model 4996 Vx orks® Driver allows high−level programming for various
workstation platforms. In addition to the feature set provided by the driver, source
code is included, allowing users to modify software functionality. Refer to the
Vx orks Driver documentation for the Model 6230/6231 (Pentek part #803.62300) for
further description of these capabilities.
VIM Baseboa d
Se ial Po ts
Model 6231
Vi tex−E FPGA
A0
(o C0)
A1
(o C1)
B0
(o D0)
B1
(o D1)
Figure 1−6: Model 6231 FPGA Interconnectivity

Page 18 Pentek Model 6230/6231 Operating Manual
Rev.: B.4
1.12 Specifications
ront Panel Connectors
Analog Inputs: Four [two] female SMA connectors (one per A/D converter)
Sample Clock Input: One female SMA connector
Sync/Gate Bus: One 26−pin connector, with four gates, one sync, and one
clock input/output LVDS signals, plus one sync and
one gate input TTL signals
TTL Sync/Gate: One 4−pin header, with one sync and one gate TTL inputs
PGA Input/Output:
Model 6230: One 50−pin connector, with 32 FPGA input/output pins,
20 mA maximum load per pin
Model 6231, Option 102: One 50−pin connector, with 24 FPGA input/output pins,
20 mA maximum load per pin
Analog Signal Inputs
Quantity: Four [two], via front panel SMA connectors
Input Type: Single−ended, non−inverting
Coupling: DC
Input Impedance: 50Ω
ull Scale Input: Standard: 2 Vp−p (± 1.0 V)
Option 105: 1 Vp−p (± 0.5 V)
Input Offset Error: ± 0.6% full scale range @ 25° C
± 1.6% full scale range over operating temperature range
Analog Input Conditioning (without Option 105)
Analog Input Amplifiers
Quantity: Four [two] (enclosed in a shielded cover)
Device: Analog Devices OPA642
Gain: One (unity), standard
3 dB Bandwidth: 90 MHz (based on gain of one)
Analog Input ilters
Quantity: Four [two] (enclosed in a shielded cover)
Type: Fixed frequency low−pass, 7−pole, LC
Passband: DC to 26 MHz (±3.0 dB ripple)
Stopband Attenuation: >70 dB @ 60 MHz
Bypass: May be bypassed by on−board jumper selection
Analog Input Conditioning (with Option 105)
Analog Input Transformers
Quantity: Four [two] (enclosed in a shielded cover)
Type: Mini−Circuits ADT4−5 T
3 dB Passband: 300 kHz to 500 MHz
Input Return Loss: 8.72 dB min., 31.13 dB max.
Bypass: None

Pentek Model 6230/6231 Operating Manual Page 19
Rev.: B.4
1.12 Specifications (continued)
Analog/Digital Converters
Quantity: Four [two] (enclosed in a shielded cover)
Device: Analog Devices AD6644 (see Appendix B)
Sampling Rate: 15 MHz to 65 MHz
Resolution: 14 bits
Coupling: DC
Clock Source: Onboard crystal oscillator, external clock, or LVDS clock
(software selectable)
External Clock Input
Voltage Range: 1 VP−P (minimum), 5 VP−P (maximum)
Type: Square or Sine ave
Duty Cycle: 45% to 55%
requency: 15 MHz to 65 MHz
Impedance: 50Ω, AC coupled
Sample Rate Control
Internal Clock: 64 MHz
External Clock: 15 MHz to 65 MHz
Sample Rate Divider: Divisible by 1, 2, or 4 (internal or external source)
Gates
Quantity: Four [two], one per VIM baseboard BIFO
Polarity: Programmable
Routing: Each VIM baseboard processor can create its own gate
Gate Disable: Each gate can be disabled from its processor
(BIFO writes default to enable)
Digital Receivers
Quantity: Eight [four] quad receiver chips (32 [16] receiver channels)
Device: Graychip GC4016 (see Appendix C)
Decimation: 32 to 16,384
Data Source: All A/D outputs are connected to each GC4016
Clock Source: A/D clock
Sync: Maskable inside each GC4016 chip
(All receiver channels directed to the same VIM base−
board BIFO must be synced at the GC4016 output)
Output: Serial data
(Serial output rate must be same as input clock rate)
Bypass Mode: Data from the A/D converters can be written directly into the
VIM baseboard BIFOs (bypassing the GC4016s), at a sam−
ple rate equal to the A/D clock decimated by 1 or any
even value between 2 and 4096

Page 20 Pentek Model 6230/6231 Operating Manual
Rev.: C
1.12 Specifications (continued)
Field−Programmable Gate Arrays
Quantity: Two [one], one for Processors A & B, one for Processors C & D
Device: Xilinx Virtex−E XCV300E (standard);
Option 600 – Xilinx Virtex−E XCV600E
Programming: Factory programmed by Pentek
(contact Pentek for user programming information)
Estimated Power Dissipation: Model 6230 Model 6231
+2.5V Digital Supply (DC/DC):
Graychip GC4016s: (at 80MHz and minimum decimation)
8 * 187mA = 1.5A 4 * 187mA = 0.75A
1.5A * 2.5V = 3.75W 0.75A * 2.5V = 1.875W
3.75W/.93 = 4.0 W 1.875W/.93 = 2.0 W
+5V Analog Supply (LC Filtered +5V):
AD6644 A/D Converters: 260 mA * 4 = 1.04 A 260 mA * 2 = 0.52 A
OPA642 Amplifiers: 25 mA * 4 = 0.10 A 25 mA * 2 = 0.05 A
AD8138 Amplifiers: 24 mA * 4 = 0.10 A 24 mA * 2 = 0.05 A
1.24 A * 5V = 6.2 W 0.62 A * 5V = 3.1 W
−5V Analog Supply (Linear from −12V):
OPA642 Amplifiers: 25 mA * 4 = 100 mA 25 mA * 2 = 50 mA
AD8138 Amplifiers: 24 mA * 4 = 96 mA 24 mA * 2 = 48 mA
196 mA * 12V = 2.3 W 98 mA * 12V = 1.2 W
+1.8V Digital Supply (DC/DC from 5V):
XCV300E FPGAs w/base circuitry: 1.3 W 0.65 W
XCV300E FPGAs w/heavy use: 5.6 W 2.8 W
XCV600E FPGAs w/heavy use: 11.8 W 5.91 W
+3.3V Digital Supply (DC/DC from 12V):
XCV300E FPGAs w/base circuitry: 1.2 W 0.6 W
XCV300E FPGAs w/heavy use: 1.3 W 0.65 W
XCV600E FPGAs w/heavy use: 1.9 W 0.95 W
_______ _______
Total Board Power:
XCV300E FPGAs w/base circuitry: 15 W 7.55 W
XCV300E FPGAs w/heavy use: 19.4 W 9.75 W
XCV600E FPGAs w/heavy use: 25.2 W 13.15 W
(Notes: Estimated at 80MHz — power consumption is less at 65 MHz;
FPGA power consumption will vary based on usage)
Physical
Dimensions: 6230 VIM−4 Module 6231 VIM−2 Module
Height: 228.6 mm (9.00 in) 114.3 mm (4.50 in)
Depth: 82.5 mm (3.25 in) 82.5 mm (3.25 in)
Width: 20.3 mm (0.80 in) 20.3 mm (0.80 in)
Weight: 260.8 grams (9.2 oz) 138.9 grams (4.9 oz)
Environmental
Operating Temperature: 0° to 50°C
Storage Temperature: −20° to 90°C
Relative Humidity: 0 to 95% non−condensing