Pentek 6230 User manual

Pentek Model 6230/6231 Operating Manual Page 1
Manual Part No: 800.62300 Rev: C.1 − October 23, 2006
Pentek, Inc.
One Park Way
Upper Saddle River, NJ 07458
(201) 818−5900
http://www.pentek.com
Copyright © 2006
OPERATING MANUAL
MODEL 6230/6231
32/16−Channel Digital Receiver VIM Module
for Pentek VIM Baseboards

Page 2 Pentek Model 6230/6231 Operating Manual
Manual Revision History
Warranty
Pentek warrants that all products manufactured by Pentek conform to published Pentek specifications and are free from defects in mate−
rials and workmanship for a period of one year from the date of delivery when used under normal operating conditions and within the
service conditions for which they were furnished.
The obligation of Pentek arising from a warranty claim shall be limited to repairing or at its option, replacing without charge, any product
that in Pentek’s sole opinion proves to be defective within the scope of the warranty. Pentek must be notified in writing of the defect or
nonconformity within the warranty period and the affected product returned to Pentek within thirty days after discovery of such defect or
nonconformity.
Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Pentek for warranty service. Pentek shall pay
for the return of products to buyer except for products returned from another country.
Pentek shall have no responsibility for any defect or damage caused by improper installation, unauthorized modification, misuse, neglect,
inadequate maintenance, or accident, or for any product that has been repaired or altered by anyone other than Pentek or its authorized
representatives.
The warranty described above is buyer’s sole and exclusive remedy and no other warranty, whether written or oral, is expressed or
implied. Pentek specifically disclaims fitness for a particular purpose. Under no circumstances shall Pentek be liable for any direct, indi−
rect, special, incidental, or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any
other legal theory.
Copyrights
With the exceptionofthoseitems listed below, the contentsof this publication arecopyright©2006,Pentek,Inc.
All Rights Reserved. Contents of this publication may not be reproduced in any form without written permission.
Appendix B, AD6644 Datasheet, is the copyrighted property of Analog Devices, Inc., Norwood MA
Appendix C, Graychip GC4016 Datasheet, is the copyrighted property of Graychip, Inc., Palo Alto, CA
Appendix D, ADM1024 Datasheet, is the copyrighted property of Analog Devices, Inc., Norwood MA.
Trademarks
Pentek, GateFlow, ReadyFlow, and VIM are registered trademarks or trademarks of Pentek, Inc.
VxWorks is a registered trademark of Wind River Systems, Inc. Xilinx and Virtex are registered trademarks or trademarks of Xilinx, Inc.
Date Manual Rev Comments
6/8/01 Preliminary Initial product release.
1/31/02 A Added instructions for programming ADM1024, Sect 3.6. Added channel number coding
for Channel Tag in output format, Section 4.2, per KB Case 972. Added detailed installation
instructions for Option 102, Sect 2.3. Removed Virtex−E FPGA Appendix—data is in FPGA
Design Kit, Part #49530−250. Added Input Offset Error Specifications, per KB case 1016.
6/14/02 A.1 Added notes on Real mode output from GC4016s in DDR modes, Sect 4.2, per KBcase 1073.
9/26/02 A.2 Added note on Reset hold time, Sect 3.7, per KBcase 961.
12/16/02 A.3 Added board weight, Sect 1.11, per KBcase 1137. Corrected installation instructions, Sect 2.3,
per KBcase 1138. Corrected FPGA mating connector ERNI part #, Sect 2.4.5, per KBcase 1129.
2/24/03 A.4 Corrected Sync/Gate & FPGA connector part numbers, Sect 2.4.3 and 2.4.5, per KBcase 1155.
3/4/03 A.5 Corrected DDR Bypass mode descriptions, Sect 4.2.1 and 4.2.2.
5/21/03 B Added Option 105 information.
6/6/03 B.1 Corrected Configuration Data Register to Write Only, Sect 3.4.
7/15/03 B.2 Added VME baseboards, Sect 1.1, added Support Software Sect 1.11, corrected Model 4205
base addresses, Sect 3.2.
10/15/03 B.3 Corrected footnotes for register power−up states, Tables 3−5, 3−19, 3−20, 3−23, 3−26, 3−27.
Added comment that input channel data goes only to associated BIFO for Bypass modes,
Sect 4.2.1 & 4.2.2, per KBcase 1153. Moved Timing & Sync to new Chapter 5.
6/25/04 B.4 Added note about more samples than trigger length , Sect 3.11, per KBcase 1161.
1/14/05 C Updated Power Specifications, Sect 1.12.
10/23/06 C.1 Added Environmental Specifications, Sect 1.12. Updated ERNI conector part numbers, Sect
2.4.3 & 2.4.5, per KBCase 1308.
Printed in the United States of America.

Pentek Model 6230/6231 Operating Manual Page 3
Page
Table of Contents
Rev.: B.4
Chapter 1: Introduction
1.1 General Description..............................................................................................................................9
1.2 Features ..................................................................................................................................................9
1.3 Analog/Digital Conversion ..............................................................................................................10
1.4 Digital Receivers .................................................................................................................................10
1.5 Digital Interfaces.................................................................................................................................10
1.6 Timing and Synchronization.............................................................................................................11
1.7 Interrupts .............................................................................................................................................11
1.8 VIM Interface.......................................................................................................................................11
1.9 Block Diagrams ...................................................................................................................................12
igure 1−1: Model 6230 Block Diagram.........................................................................................12
igure 1−2: Model 6231 Block Diagram.........................................................................................12
igure 1−3: Model 6230 Block Diagram, with Option 105.........................................................13
igure 1−4: Model 6231 Block Diagram, with Option 105.........................................................13
1.9.1 Channels .............................................................................................................................14
1.10 FPGA Configuration ..........................................................................................................................15
1.10.1 Model 6230 .........................................................................................................................16
igure 1−5: Model 6230 PGA Interconnectivity .......................................................16
1.10.2 Model 6231 .........................................................................................................................17
igure 1−6: Model 6231 PGA Interconnectivity .......................................................17
1.11 Board Support Software ....................................................................................................................17
1.12 Specifications.......................................................................................................................................18
Chapter 2: Installation and Connections
2.1 Inspection.............................................................................................................................................21
2.2 Jumper Block Settings ........................................................................................................................21
2.2.1 Analog Input Filter Bypass Jumpers (without Option 105) .......................................21
Table 2−1: Analog Input ilter Bypass Jumpers.........................................................21
2.2.2 FPGA Configuration Data Source Jumper ....................................................................22
Table 2−2: PGA Configuration Data Source Jumper ..............................................22
2.2.3 External TTL Inputs Select Jumpers ..............................................................................22
Table 2−3: External TTL Inputs Select Jumpers .........................................................22
igure 2−1: Model 6230 PCB Assembly, Component Side ........................................................23
igure 2−2: Model 6231 PCB Assembly, Component Side ........................................................24
igure 2−3: Model 6231 Option 102 PCB Assembly, Component Side...................................24

Page 4 Pentek Model 6230/6231 Operating Manual
Page
Table of Contents
Rev.: B.4
Chapter 2: Installation and Connections (continued)
2.3 Installing the Model 6230/6231 on a VIM Baseboard................................................................... 25
igure 2−4: Typical VIM Baseboard − Connectors & Mounting Holes ................................. 26
2.3.1 Installing Model 6230, or Model 6231 without Option 102 ........................................ 27
igure 2−5: VIM−4 Panel Mounting & Shipping Screws ........................................ 27
igure 2−6: VIM Module Nylon Spacer....................................................................... 28
igure 2−7: VIM Baseboard Blank Panel Screws....................................................... 28
2.3.2 Installing Model 6231 with Option 102 ......................................................................... 30
igure 2−8: Model 6231 with Option 102 Shipping Assembly................................ 30
igure 2−9: VIM Module Nylon Spacer....................................................................... 31
igure 2−10: VIM Baseboard Blank Panel Screws..................................................... 31
igure 2−11: Option 102 ront Panel Assembly ......................................................... 32
igure 2−12: VIM Baseboard with Option 102 ront Panel Assembly.................. 33
igure 2−13: Option 102 Stacking Connectors on VIM Module............................. 33
igure 2−14: Option 102 PCB Mounted on VIM Module......................................... 34
2.4 Front Panel Connections ................................................................................................................... 35
2.4.1 Analog Input Connectors ................................................................................................ 35
2.4.2 Sample Clock Input Connector ...................................................................................... 35
igure 2−15: Models 6230 and 6231 ront Panels ........................................................................ 36
2.4.3 Sync/Gate Connector ...................................................................................................... 37
Table 2−4: SYNC/GATE Connector Pins..................................................................... 37
2.4.4 Sync/Gate Header ........................................................................................................... 37
Table 2−5: SYNC/GATE/TRG Header Pins ................................................................ 37
2.4.5 FPGA Connector .............................................................................................................. 38
Table 2−6: PGA Connector Pins.................................................................................. 38
2.5 Front Panel LEDs................................................................................................................................ 39
2.5.1 Clock (CLK) LED .............................................................................................................. 39
2.5.2 Over Temperature (TEMP) LED .................................................................................... 39
2.5.3 Master (MAS) LED ........................................................................................................... 39
2.5.4 Terminate (TRM) LED ..................................................................................................... 39
2.5.5 Overload (OVLD CHn) LEDs ......................................................................................... 39

Pentek Model 6230/6231 Operating Manual Page 5
Page
Table of Contents
Rev.: B.4
Chapter 3: Memory Maps and Register Descriptions
3.1 Overview..............................................................................................................................................41
3.2 Model 6230/6231 Memory Map.......................................................................................................41
Table 3−1: VIM Base Addresses for Models 4290 to 4295 VIM Baseboards ..........................41
Table 3−2: VIM Base Addresses for Model 4205 VIM Baseboards .........................................41
Table 3−3: Model 6230/6231 Memory Map ...................................................................................42
3.3 Virtex Config Register........................................................................................................................43
Table 3−4: Virtex Config Register ..................................................................................................43
3.3.1 RITE ................................................................................................................................43
3.3.2 BUSY ...................................................................................................................................43
3.3.3 INIT .....................................................................................................................................43
3.3.4 DONE .................................................................................................................................44
3.3.5 PRGM .................................................................................................................................44
3.3.6 LD SRC ...............................................................................................................................44
3.4 Virtex Config Data Register ..............................................................................................................44
Table 3−5: Virtex Config Data Register.........................................................................................44
3.5 ait States Register............................................................................................................................45
Table 3−6: Wait States Register.......................................................................................................45
3.6 Hardware Monitor Port Register......................................................................................................46
Table 3−7: Hardware Monitor Port Register ................................................................................46
Table 3−8: ADM1024 Registers.......................................................................................................47
3.7 Master Control Register.....................................................................................................................48
Table 3−9: Master Control Register................................................................................................48
3.7.1 RESET .................................................................................................................................48
3.7.2 SYNC SRC ..........................................................................................................................48
3.7.3 SYNC POL .........................................................................................................................49
3.7.4 EXT SYNC EN ...................................................................................................................49
3.7.5 MCLK DIVn .......................................................................................................................49
3.7.6 CLK SRC SEL ....................................................................................................................49
3.7.7 OSC DSBL ..........................................................................................................................49
3.7.8 EXT CLK ............................................................................................................................50
3.7.9 TERM ..................................................................................................................................50
3.7.10 MASTR ...............................................................................................................................50
3.8 Bypass Rate Divide Register .............................................................................................................51
Table 3−10: Bypass Rate Divide Register .....................................................................................51
3.9 Channel Enable Register....................................................................................................................52
Table 3−11: Channel Enable Register............................................................................................52
Table 3−12: Register Bit Channel Assignments...........................................................................52
3.10 Gate Control Register.........................................................................................................................53
Table 3−13: Gate Control Register..................................................................................................53
3.10.1 INT EDGE x .......................................................................................................................53
3.10.2 GATE POL .........................................................................................................................54
3.10.3 GATE SELn ........................................................................................................................54

Page 6 Pentek Model 6230/6231 Operating Manual
Page
Table of Contents
Rev.: B.4
Chapter 3: Memory Maps and Register Descriptions
3.10.4 GATE DISBL ..................................................................................................................... 54
3.10.5 GATE SRC ......................................................................................................................... 54
3.10.6 TRIG CLEAR ..................................................................................................................... 54
3.10.7 HOLD MODE ................................................................................................................... 55
3.10.8 GATE/TRIG ...................................................................................................................... 55
3.10.9 EXT GATE ......................................................................................................................... 55
3.11 Trigger Length Register..................................................................................................................... 56
Table 3−14: Trigger Length Register .............................................................................................56
3.12 Channel Control Register.................................................................................................................. 57
Table 3−15: Channel Control Register .......................................................................................... 57
3.12.1 RESET ................................................................................................................................. 57
3.12.2 DIV RST EN ...................................................................................................................... 57
3.12.3 FMTR EN ........................................................................................................................... 57
3.12.4 DAT MODEn .................................................................................................................... 58
3.13 Sync/Gate Generator Register ......................................................................................................... 59
Table 3−16: Sync/Gate Generator Register................................................................................... 59
3.13.1 FIFO GATE ........................................................................................................................ 59
3.13.2 SYNC .................................................................................................................................. 59
3.14 Interrupt Mask Register .................................................................................................................... 60
Table 3−17: Interrupt Mask Register.............................................................................................60
Table 3−18: Interrupt Register Bits................................................................................................ 61
3.15 Interrupt Flag Register ...................................................................................................................... 62
Table 3−19: Interrupt lag Register ............................................................................................... 62
3.16 Interrupt Status Register ................................................................................................................... 63
Table 3−20: Interrupt Status Register............................................................................................ 63
3.17 Semaphore Register ........................................................................................................................... 64
Table 3−21: Semaphore Register .................................................................................................... 64
3.18 I/O Direction 2 Register (Model 6231 only)................................................................................... 65
Table 3−22: I/O Direction 2 Register (Model 6231 Option 102 only) ...................................... 65
3.19 I/O Data 2 Register (Model 6231 only)........................................................................................... 66
Table 3−23: I/O Data 2 Register (Model 6231 Option 102 only) ............................................... 66
3.20 I/O Direction Register....................................................................................................................... 67
Table 3−24: I/O Direction Register ................................................................................................ 67
3.21 I/O Enable Register ........................................................................................................................... 68
Table 3−25: I/O Enable Register ..................................................................................................... 68
3.21.1 I/O EN1 ............................................................................................................................. 68
3.21.2 I/O EN2 ............................................................................................................................. 68
3.22 I/O Data Register............................................................................................................................... 69
Table 3−26: I/O Data Register ......................................................................................................... 69
3.23 Graychip 0 & 1 Registers................................................................................................................... 70
Table 3−27: Graychip 0 & 1 Registers............................................................................................70
Table 3−28: Processor/Graychip Register Sets............................................................................. 70

Pentek Model 6230/6231 Operating Manual Page 7
Page
Table of Contents
Rev.: B.4
Chapter : Data Formatting and Routing
4.1 Overview..............................................................................................................................................71
4.2 Data Routing and Formats ................................................................................................................71
4.2.1 DDR Bypass Mode, A/D Data, Unpacked (001) ..........................................................72
Table 4−1: Output Data ormat − DDR Bypass Mode, Unpacked .........................72
4.2.2 DDR Bypass Mode, A/D Data, Time Packed (010) .....................................................72
Table 4−2: Output Data ormat − DDR Bypass Mode, Time Packed ....................72
4.2.3 DDR Bypass Mode, A/D Data, Channel Packed (011) ...............................................73
Table 4−3: Output Data ormat − DDR Bypass Mode, Channel Packed ..............73
4.2.4 DDR Mode, 16−Bit, Unpacked I/Q, Tagged (100) .......................................................74
Table 4−4: Output Data ormat − DDR Mode, 16−bit, Unpacked I/Q, Tagged...74
4.2.5 DDR Mode, 24−Bit, Unpacked I/Q, Tagged (101) .......................................................75
Table 4−5: Output Data ormat − DDR Mode, 24−bit, Unpacked I/Q, Tagged...75
4.2.6 DDR Mode, 16−Bit, Packed I/Q (110) ...........................................................................76
Table 4−6: Output Data ormat − DDR Mode, 16−bit, Packed I/Q ........................76
4.2.7 DDR Mode, 24−Bit, Packed I/Q (111) ...........................................................................77
Table 4−7: Output Data ormat − DDR Mode, 16−bit, Packed I/Q ........................77
Chapter 5: Timing and Synchronization
5.1 Overview..............................................................................................................................................79
igure 5−1: Model 6230 Gate/Sync/Clock Logic ..........................................................................79
igure 5−2: Model 6231 Gate/Sync/Clock Logic ..........................................................................80
5.2 Sync.......................................................................................................................................................80
5.3 Clock.....................................................................................................................................................80
5.4 Gates .....................................................................................................................................................81

Page 8 Pentek Model 6230/6231 Operating Manual
Page
Table of Contents
Rev.: B.4
Appendix A: Configuration EEPROM Format
A.1 Introduction .....................................................................................................................................A−1
A.2 EEPROM Format Example ............................................................................................................A−1
Table A−1: VIM ID EEPROM Register......................................................................................A−1
Table A−2: EEPROM Example (Model 6230 shown)...............................................................A−2
Appendix B: Analog Devices AD66 A/D Converter
B.1 Introduction ..................................................................................................................................... B−1
Appendix C: Graychip GC 016 Digital Receiver
C.1 Introduction .....................................................................................................................................C−1
Appendix D: Analog Devices ADM102 System Hardware Monitor
D.1 Introduction .....................................................................................................................................D−1

Pentek Model 6230/6231 Operating Manual Page 9
Rev.: B.4
Chapter 1: Introduction
1.1 General Description
The Models 6230 and 6231 are general purpose, narrowband digital receiver VIM®
(Velocity Interface Mezzanine) modules that perform frequency down conversion,
low−pass filtering, and decimation of the digitized input signal. The Model 6230 is a
32−channel VIM−4 module that features four 14−bit, 65−MHz A/D converters, and can
be configured with up to 32 channels of narrowband receivers. The Model 6231 is a
16−channel VIM−2 module, with two 14−bit, 65−MHz A/D converters, and up to 16
channels of narrowband receivers.
The Models 6230 and 6231 attach directly to VIM−compatible baseboards, including the
Pentek Models 4205, and 4290 through 4295 Quad DSP (Digital Signal Processing)
boards.
1.2 eatures
Four 65−MHz, 14−bit A/D converters (Model 6230)
Two 65−MHz, 14−bit A/D converters (Model 6231)
32 channels of narrowband digital receivers (Model 6230)
16 channels of narrowband digital receivers (Model 6231)
All receivers can select any of the A/D inputs
DC to 90−MHz input range (standard models)
300−kHz to 150−MHz input range (Option 105)
DC to 32−MHz center frequency tuning with 0.02−Hz resolution
3.6−kHz to 1.6−MHz output bandwidths
Front panel clock and sync bus can synchronize multiple boards
Direct connection to each VIM processor with no shared bus bottlenecks
Compliant with VIM module specification
Note
In this manual, all specifications and use inst uctions a e p esented in efe ence to
the Model 6230. Whe e a diffe ence exists, the co esponding info mation fo the
Model 6231 is included in b ackets “[...]”.

Page 10 Pentek Model 6230/6231 Operating Manual
Rev.: B.4
1.3 Analog/Digital Conversion
The Model 6230 [Model 6231] accepts four [two] analog RF inputs on front panel SMA
connectors in the range of DC to 90 MHz to support direct IF undersampling. Each
input signal is buffered by an Analog Devices OPA642 amplifier. Low−pass anti−
aliasing filters for each input signal may be individually enabled or bypassed by on−
board jumpers. ith Option 105, the amplifier, filters, and bypass jumpers are
replaced by an RF transformer, and the RF input range is 300 kHz to 150 MHz.
An Analog Devices AD6644 14−bit, 65−MHz A/D converter then digitizes each of the
analog inputs. The A/D converter clock can be driven from an internal 64−MHz crys−
tal oscillator, from an external sample clock supplied through a front panel SMA con−
nector, or from the front panel sync bus.
1.4 Digital Receivers
The Model 6230 [Model 6231] includes eight [four] Graychip GC4016 quad narrowband
digital receiver (DDR) chips. Each GC4016 DDR accepts four [two] 14−bit parallel
inputs from the AD6644 A/D converters. A crossbar switch inside each GC4016 allows
each of the 32 [16] receiver channels on the board to independently select any of the
A/D inputs for flexible switching.
The maximum input sampling rate, s, for the GC4016 is 80 MHz. Each receiver
includes four independently tunable receiver channels capable of tuning throughout
the DC to s/2 range, with output bandwidths ranging from 0.8 · s/N (for the standard
80% FIR filter), where the decimation factor, N, ranges from 32 to 16,384. For an input
sampling clock of 64 MHz, this output bandwidth range becomes approximately
3.1 kHz to 1.6 MHz. Each processor on the VIM baseboard can control all programma−
ble registers on its two associated GC4016s.
1.5 Digital Interfaces
The Model 6230 [Model 6231] contains two [one] Xilinx® Virtex®−E XCV300 FPGAs
(field programmable gate arrays). (These are optionally replaceable by other Virtex
devices in the series up to XCV600.) The FPGAs are factory programmed to implement
the standard data formatting, clocking, and control functions specified in this docu−
ment. Each GC4016 DDR delivers real or complex serial data streams into one FPGA,
where data is formatted and multiplexed for delivery across the VIM interface into the
32−bit parallel Bi−FIFOs (BIFOs) on the VIM baseboard. The AD6644 digital outputs
are also connected directly to each FPGA so that wideband A/D data can be delivered
directly to the DSP board, bypassing the digital receivers.
The user can re−program the Virtex−E FPGAs from the VIM baseboard processors.
This allows the user to implement his own algorithms for special timing requirements
and for pre−processing of AD6644 or GC4016 output data before sending it to the pro−
cessor BIFOs. Refer to Section 1.10, FPGA Configuration, for additional information
about the gate array configurations.