Pericom PI2EQX6811ZDE Installation and operating instructions

Pericom Semiconductor Corp., 3545 N. First Street, San Jose, California, USA 408-435-0800 www.pericom.com
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PI2EQX6811ZDE
PI2EQX6811ZDE Evaluation Board Rev.B User Guide
Nov.16,2011
Contents
¾Introduction
¾Board Operation
Power options
Device configuration
System connection
Power-on sequence
¾Board Design Information
PCB Schematic
PCB Layout Reference
PCB BOM List
Introduction
PI2EQX6811ZDE Evaluation Board is designed to allow convenient testing of its operation and features. This board
can work with readily available SATA and eSATA cables for easy connection to SATA3.0 HDD, SSD, OMD storage
components and PC system hosts.
This board allows the PI2EQX6811ZDE device to be powered in +1.5V directly from external power, or 5V with a mini-
USB connector provided to convert.
This User Guide describes the setup, configuration and operation of PI2EQX6811ZDE Eval Board Rev.B. Figure1
provides a top view of PI2EQX6811ZDE Eval Board Rev.B, and Figure2 is bottom view of the board.
Figure1. Top view of PI2EQX6811ZDE Eval board Rev.A

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Figure2. Bottom view of PI2EQX6811ZDE Eval board Rev.A
Board Operation
PI2EQX6811ZDE is a 1-port (2-channel), bi-directional, signal SATA3.0 re-driver to provide indication when the load
is connected to HOST or Device. Figure3 shows the logical block diagram of PI2EQX6811ZDE. Two channels of the
PI2EQX6811ZDE are fully independent in operation and configuration by I2C function. Channel configuration of
output pre-emphasis, output swing and input equalization must be set appropriately to match the attached cable/trace
length and type.
Figure3. Logical Block Diagram of PI2EQX6811ZDE

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zPower Options
The PI2EQX6811ZDE Evaluation Board provides the options for supplying +1.5V directly or +5V power from mini-
USB connector. Figure 4 circles the important connections.
1) Using the +5V power supplied by miniUSB connector (J1). The on-board LDO down-steps the voltage to +1.5V.
When using this source, note that jumper JP11 must be shorted (populated).
2) Using +1.5V power input directly by JP18 power pin header and JP19 ground pin header. When using this
method, JP11 must be open.
3) For PI3EQX6801ZDE power supply, the evaluation board is shipped from the default with +1.5V from externally
power supply.
VDD
+
EC4
22u_3528
C7
0.1u_0402
+
EC5
22u_3528
C8
0.1u_0402
D1
LED_G
12
R3
510ohm_0402
J1
CON_USB2.0_MiniB_SMT
VBUS 1
D- 2
D+ 3
ID 4
GND 5
U2
CJ1117-1.5V
ADJ/GND
1
VOUT 2 VIN
3
+5V
R1
0_0402
R2 NP_0402
JP11
1 2
JP18
1 2 3
JP19
1 2 3
VDD
C1
0.1u_0402
C2
0.1u_0402
C3
0.1u_0402
C4
0.1u_0402
+
EC1
22u_3528
Figure4. Power supply of PI2EQX6811ZDE
zDevice Configuration
The PI2EQX6811ZDE ReDriver supports Pre-emphasis, swing adjustment and input equalization for optimum
operation and signal margins.
PI2EQX6811ZDE provides two ways configuration controls depending on the state of the I2C_EN# pin.
When I2C_EN# is set to HIGH (JP23 to VDD), the configuration input pins set the configuration operating state
and changes to these control pins will change the operating I2C_EN#. For pin configurations, there are some
configuration values to be selected only.
When I2C_EN# pin is set to LOW (JP23 to GND), reprogramming of these control registers via I2C is allowed.
For I2C configurations, all the configuration values can be used by I2C as default configuration on EVB.
Table1 shows the pin functions for pin control and I2C control.

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VDD
I2C Programmable address bit A0
8dB
I2C Data Line
Same as Pin control function
I2C Programmable address bit A1
Don't Care
Don't Care
I2C Clock Line
GND
Input Equalization for Channel B
JP21
16dB
Open 4dB
2dB
VDD
JP22
0dB
GND
Input Equalization for Channel B
3.5dB
Open
P9:A1/B_EM
Pre-emphasis control for Channel B
Tri-level control
Input Equalization for Channel A
Tri-level control by JP25
Setting Value same as P8
P17:
SDATA/A_EQ
Auto slumber mode Enable
High: disable
Low: enable
P18:APD_EN#
P19:
SCLK/A_EM
Pre-emphasis control for Channel A
Tri-level control by JP27
Setting Value same as P9
P10:I2C_EN#
900
I2C Enable
High: pin control
Low: I2C control
Output Swing control for Channel A&B
Tri-level control
P20:SW
667
VDD
JP24
533
GND
Output Swing for Channel A&B
mV(Vtx_diff_pp) at 3Gb/s
Open
I2C Control FunctionPIN NAME PIN Control FUNCTION
P7:EN
P8:A0/B_EQ
Input Equalization for Channel B
Tri-level control
With Internal 100k-ohm pull-up resistor
High: Normal Operation
Low: Power Down Mode
Same as Pin control function
1) Pin Configurations
Configuration begins with I2C_EN# pin with JP23, which must be connected to VDD. The EN pin of the
PI2EQX6811ZDE has an internal 200K pull-up resistor to define a high level default (JP20 Open) for normal operation.
When EN pin is shorted to GND (JP20 is shorted to GND), device operation is disabled. This is useful for checking
PI2EQX6811ZDE disabled-state power consumption. Figure5 is pin strap configuration for pin headers.

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Figure5. Pin Strap Configuration of PI2EQX6811ZDE
Input Equalizer Setting
Input equalizer setting has P17 (A_EQ) and P18 (B_EQ) tri-level configuration by JP25 and JP21. So it is available
with 3 values in Blue color in Table1 below.
Output Pre-emphasis Setting
Output Pre-emphasis setting has P19 (A_EM) and P9 (B_EM) tri-level configuration by JP27 and JP22. Table1 shows
its selectable setting values.
Output Swing Setting
Output Swing setting has P20 (SW) tri-level configuration by JP24. Table1 shows its selectable setting values.
Auto-slumber Mode Enable Setting
Auto-slumber mode enable setting has P18 (APD_EN#) configuration by JP26. When JP26 is connected to GND,
auto-slumber mode will be enabled, but it is connected to VDD, auto-slumber mode will be disabled.
2) I2C Configuration
On PI2EQX6811ZDE EVB, I2C_EN# pin (JP23) is shorted to GND on EVB, I2C configuration is enabled for all the
setting as default. And P8 (JP21, A0) and P9 (JP22, A1) pins are also shorted to GND as default I2C address-C0.
Figure6 is their locations on EVB and I2C interface connector definition and location.

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Figure6. I2C address Pins Jumper and Interface location
For PI2EQX6811ZDE’s I2C interface, it is compliant with 3.3V power. Figure7 is read/write waveform sample at the
register value below for the reference.
Figure7. I2C Write/Read Waveform Sample
NOTE that there is one dummy byte in Write Sequence.
For detail I2C register description, please refer to Page7-10 in datasheet.
I2C Write Sequence I2C Read Sequence
DUMMY BYTE
C0

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3) Board Connection
Figure8 is board connections for the reference.
Figure8. Board Connection
zSystem Connection
The diagrams below show some example system test setups with the PI2EQX6811ZDE Eval Board.
Figure9 shows the connection using a NB PC and eSATA Express Card. Note that many notebooks PCs already
offer an eSATA port which can be used as the test signal source without the add-in card.
Figure9. eHDD connection Test Setup using NB+eSATA Express Card with PI2EQX6811ZDE Eval Board
PI2EQX6811ZDE
EVB
To Device or HDD
From Host
VDD
GND

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Figure10 shows the connection using Intel MB
Figure10. internal HDD connection Test Setup using Intel MB with PI2EQX6811ZDE Eval Board
zPower-on Sequence
It is recommended as good practice, that all system components be powered off while connections and configuration
settings are made. There is no specific power-on sequence required when applying power to the PI2EQX6811ZDE
Eval Board. When connected to the system and powered by USB as shown above, then all devices will power-up
together.
If the host PC and/or HDD are powered on, while the Eval Board is off, there will be no damage to the
PI2EQX6811ZDE under typical conditions. If the Eval Board is then powered on, the system will generally detect the
SATA HDD as a hot-plug event, and the HDD will begin to operate properly. Note that some PC systems offer BIOS
control over hot plug events, and if the HDD is not recognized, this BIOS setting is the most likely cause and should
be changed. When connecting to the system as shown above, all devices will power on together and avoid this BIOS
issue.
PI2EQX6811ZDE
EVB

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Board Design Information
zPCB Schematic
AI_P
AI_N
AI_R_P
AI_R_N
BO_NBO_C_N
VDD
BO_C_P BO_P
JP24
1 2 3
JP25
1 2 3
JP26
1 2 3
APD_EN#
JP27
1 2 3
AO_P
JP21
1 2 3
AO_N
JP23
1 2 3
JP22
1 2 3
AO_C_P
VDD
AO_C_N
BI_R_N
VDD
A0_BEQ
BI_N
BI_R_P
BI_P
SW
VDD is +1.5V for PI2EQX6811
JP12
CON_SATA_SMT
11
22
33
44
55
66
77
JP18
1 2 3
JP19
1 2 3
SCL_AEM
VDD
A1_BEM
VDD
I2C_EN#EN
VDD
C1
0.1u_0402
SDA_AEQ
C2
0.1u_0402
C3
0.1u_0402
C4
0.1u_0402
+ EC1
22u_3528
JP13
CON_SATA_SMT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
C6
0.1u_0402
R29
10k_0402
R30
10k_0402
+3. 3V
SCL_AEM
J2
4p-2.54mm Connector
1
2
3
4
SDA_AEQ
JP20
1 2 3
R6 0_0402
R4 NP/0_0402
R7 0_0402
U3
PI2EQX6811ZDE@TQFN20
AI+
1
AI-
2
NC
3
BO-
4
BO+
5
VDD
6
EN
7
A0/B_EQ
8
A1/B_EM
9
I2C_EN#
10
BI+ 11
BI- 12
NC 13
AO- 14
AO+ 15
VDD 16
SDATA/A_EQ 17
APD_EN# 18
SCLK/A_EM 19
SW 20
HGND 21
R5 NP/0_0402
C11 10n_0402
C12 10n_0402
R8 0_0402
R9 0_0402
C15 10n_0402
C16 10n_0402
VDD
+
EC4
22u_3528
C7
0.1u_0402
+
EC5
22u_3528
C8
0.1u_0402
D1
LED_G
12
R3
510ohm_0402
J1
CON_USB2.0_MiniB_SMT
VBUS 1
D- 2
D+ 3
ID 4
GND 5
U2
CJ1117-1.5V
ADJ/GND
1
VOUT 2 VIN
3
+5V
R1
0_0402
R2 NP_0402
JP11
1 2
zPCB Layout Reference
a. Stack Up:
b. Isolation Spacing = 30 mil
c. Width & Spacing (W/S) of 100ΩDifferential Trace = 10 / 9 mil

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zPCB BOM List
Reference Description Package Qty
U2 LM3674-1.5V SOT23-5 1
U3 PI2EQX6811ZDE@TQFN20 TQFN20 1
Bare PCB
PCB, PI2EQX6811ZDE-SATA ReDriver
Rev.B PCB 1
D1 LED 0805 1
JP12,JP13 SATA L-type connector L-type 2
J2 4p-2.54mm Connector 2.54mm 1
J1 miniUSB connector B-type 1
JP11 2PIN HEADER 2.54mm 1
JP18,JP19,JP20,JP21,JP22,
JP23,JP24,JP25,JP26,JP27 3PIN HEADER 2.54mm 10
C11,C12,C15,C16 Ceramic Capacitor, 10nF 0402 4
C1,C2,C3,C4,C6,C7,C8 Ceramic Capacitor, 0.1uF 0402 7
EC1,EC4,EC5 Tan cap, 22u 3528 3
R3 Chip Resistor, 510ohm 0402 1
R29,R30 Chip Resistor, 10Kohm 0402 2
R1,R6,R7,R8,R9 Chip Resistor, 0ohm 0402 5

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History
Version 1.0 Original Version Nov 16, 2011