Philips TEA5880TS User manual

1. General description
The TEA5880TS stereo FM radio IC dramatically reduces the printed-circuit board area
(only 100 mm2) needed to integrate FM radio functionality into portable devices. This
makes it invaluable for any application where space is at a premium.
Relying on a system host processor for radio tuning, the TEA5880TS is ideally suited for
powerful devices such as PDAs, notebooks, portable CD and MP3 players.
2. Features
■No alignments necessary
■Complete adjustment-free stereo decoder; no external crystal required
■Fully integrated MPX VCO circuit
■Fully integrated low IF selectivity and demodulation
■The full integration level means no or few external components required
■No external FM discriminator needed due to full integration
■Built-in adjacent channel interference total reduction (no 114 kHz, no 190 kHz)
■The level of the incoming signal at which the radio must lock is software programmable
■Due to new tuning concept, the tuning is independent of the channel spacing
■Very high sensitivity due to integrated low noise RF input amplifier
■RF Automatic Gain Control (AGC) circuit
■Standby mode for power-down, no power switch circuitry required
■2.7 V minimum supply voltage
■MPX output for RDS
■3-wire bus
■In combination with the host, fast, low power operation of preset mode, manual search,
automatic search and automatic store are possible
■Host can be in Sleep mode after tuning; a minute retuning is recommended to
compensate for temperature and voltage fluctuations
■Covers all Japanese, European and US bands.
TEA5880TS
Integrated FM stereo radio IC for host processor tuning in
handheld applications
Rev. 02 — 26 April 2004 Preliminary data sheet

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 2 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
3. Quick reference data
Table 1: Quick reference data
V
CCA
= V
CCD
Symbol Parameter Conditions Min Typ Max Unit
VCCA analog supply voltage 2.7 3.0 5.0 V
VCCD digital supply voltage 2.7 3.0 5.0 V
ICCA analog supply current operating - 17 22 mA
standby - 1 100 µA
ICCD digital supply current operating - 250 500 mA
standby - 1 100 µA
ILED optional stereo LED - 1 2 mA
fFM(ant) FM input frequency 76 - 108 MHz
Tamb ambient temperature VCCA = VCC(VCO) = VCCD = 3 V −10 - +75 °C
VCCA = VCC(VCO) = VCCD = 5 V −40 - +85 °C
FM overall system parameters
Vi(RF) RF sensitivity input
voltage fRF = 76 MHz to 108 MHz; ∆f = 22.5 kHz; fmod = 1 kHz; (S+N)/N = 26 dB;
de-emphasis = 75 us;
BAF = 300 Hz to 15 kHz; left = right
-13µV
SUPpilot pilot suppression ∆fpilot = 6.75 kHz; ∆f = 68.5 kHz 40 dB
IP3in in-band 3rd order
intercept point at LNA
input
-95-dBµV
IP3out out-band 3rd order
intercept point at LNA
input
-95-dBµV
S−300 LOW side 300 kHz
selectivity ∆f = −300 kHz; fRF = 76 MHz to 108 MHz - 40 - dB
S+300 HIGH side 300 kHz
selectivity ∆f = 300 kHz; fRF = 76 MHz to 108 MHz - 50 - dB
S−200 LOW side 200 kHz
selectivity ∆f = −200 kHz; fRF = 76 MHz to 108 MHz - 30 - dB
S+200 HIGH side 200 kHz
selectivity ∆f = 200 kHz; fRF = 76 MHz to 108 MHz - 40 - dB
IR image rejection fRF = 76 MHz to 108 MHz - 26 - dB
VAUDL;
VAUDR
left and right audio output
voltage VRF = 1 mV; left = right; ∆f = 22.5 kHz; fmod = 1 kHz - 100 - mV
(S+N)/N maximum signal plus
noise-to-noise ratio VRF = 1 mV; left = right; ∆f = 22.5 kHz;
fmod = 1 kHz de-emphasis = 75 µs;
BAF = 300 Hz to 15 kHz
48 56 - dB
αcs stereo channel
separation VRF = 1 mV; right = 1 and left = 0 or right = 0 and left = 1; fmod = 1 kHz;
∆fpilot = 6.75 kHz; ∆fleft = 68.5 kHz and
∆fright = 0 or ∆fright = 68.5 kHz and ∆fleft = 0
15 25 - dB

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Preliminary data sheet Rev. 02 — 26 April 2004 3 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
4. Ordering information
THD total harmonic distortion VRF = 1 mV; left = right; ∆f = 75 kHz;
fmod = 1 kHz; BAF = 300 Hz to 15 kHz - 0.7 1.5 %
VRF = 1 mV; left = right; ∆f = 22.5 kHz;
fmod = 1 kHz; BAF = 300 Hz to 15 kHz - 0.2 0.7 %
DEEM integrated de-emphasis - 50/75 - µs
Table 1: Quick reference data
…continued
V
CCA
= V
CCD
Symbol Parameter Conditions Min Typ Max Unit
Table 2: Ordering information
Type number Package
Name Description Version
TEA5880TS SSOP24 plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

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9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Preliminary data sheet Rev. 02 — 26 April 2004 4 of 27 Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
5. Block diagram
Depending on the antenna design the filter components at pins 1 and 2 may not be necessary. The only two remaining coils connected to pin
17 to 20 can be replaced by printed-circuit board traces that will fit underneath the TEA5880TS resulting in a design without any external
components; see Section 14 for details on the printed-circuit board coils.
Fig 1. Block diagram.
001aaa665
QUADRATURE
MIXER
STABILISATOR
QUADRATURE
OSCILLATOR TUNING SYSTEM
SELECTIVITY DEMODULATOR
POWER
SWITCH
STEREO
DECODER DE-EMPHASIS 50/75 µs
DIGITAL
INTERFACE
MICROCONTROLLER
DE-EMPHASIS
15 kHz MIXER
LEVEL VOLTAGE
GENERATOR
10
TEA5880TS
11
9
5
68 7
2117 18 19 20
1
2
4 3, 13, 24
VCCA
RFIN
RFGND
LR1 VCC1 VCC1 LL1 reserved R/W CLOCK
AUDL
AUDR
MPX
DATA
VCCD GND LED n.c.
12 14, 15, 16, 22, 23

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9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved. Preliminary data sheet Rev. 02 — 26 April 2004 5 of 27 Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
Fig 2. Block diagram (no external components).
001aaa666
STABILISATOR
QUADRATURE
OSCILLATOR TUNING SYSTEM
SELECTIVITY DEMODULATOR
POWER
SWITCH
STEREO
DECODER DE-EMPHASIS 50/75 µs
DIGITAL
INTERFACE
MICROCONTROLLER
DE-EMPHASIS
15 kHz MIXER
LEVEL VOLTAGE
GENERATOR
10
TEA5880TS
11
9
5
68 7
2117 18 19 20
4 3, 13, 24
VCCA
LR1 VCC1 VCC1 LL1 reserved R/W CLOCK
AUDL
AUDR
MPX
DATA
VCCD GND LED n.c.
12 14, 15, 16, 22, 23
QUADRATURE
MIXER
RFIN
RFGND

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 6 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
6. Pinning information
6.1 Pin description
Table 3: Pin description
Symbol Pin Description
RFIN 1 RF input
RFGND 2 RF ground
GND 3 ground
VCCD 4 digital supply voltage
VCCA 5 analog supply voltage
R/W 6 digital read/write command input
DATA 7 bidirectional digital data line
CLOCK 8 digital data clock line input
MPX 9 FM MPX signal output
AUDL 10 audio left channel output
AUDR 11 audio right channel output
LED 12 stereo LED output
GND 13 ground
n.c. 14 not connected
n.c. 15 not connected
n.c. 16 not connected
LR1 17 coil right
VCC1 18 internal analog voltage
VCC1 19 internal analog voltage
LL1 20 coil left
reserved 21 reserved for testing use
n.c. 22 not connected
n.c. 23 not connected
GND 24 ground

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 7 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
7. Functional description
7.1 FM quadrature mixer
The FM quadrature mixer converts FM RF (76 MHz to 108 MHz) to an IF of 110 kHz. The
FM quadrature mixer provides inherent image rejection.
7.2 Quadrature oscillator
The internally tuned LC VCO provides the Local Oscillator (LO) signal for the FM
quadrature mixer. The VCO frequency range is 150 MHz to 217 MHz.
7.3 Selectivity
Fully integrated I and Q channel IF filter.
7.4 Demodulator
The FM quadrature demodulator is an integrated PLL demodulator.
7.5 Level voltage generator and analog-to-digital converter
The level voltage is analog-to-digital converted with 3 bits and output via the data line.
7.6 IF counter
The IF counter outputs a 16-bit count result via the data line.
7.7 Mute
The digital interface controls the audio mute and output level.
Fig 3. Pin configuration.
TEA5880TS
RFIN GND
RFGND n.c.
GND n.c.
VCCD reserved
VCCA LL1
R/W VCC1
DATA VCC1
CLOCK LR1
MPX n.c.
AUDL n.c.
AUDR n.c.
LED GND
001aaa667
1
2
3
4
5
6
7
8
9
10
11
12
14
13
16
15
18
17
20
19
22
21
24
23

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 8 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
7.8 Stereo decoder
The PLL stereo decoder is adjustment free. The stereo decoder can be switched to mono
via the digital interface.
8. Digital interface (3-wire bus)
The TEA5880TS has a 3-wire bus with read/write, clock and data line.
The register set of the TEA5880TS can be accessed via the digital interface.
The pins given in Table 4 are defined for the digital interface of the TEA5880TS.
Table 4: Digital interface pins
Pin number Name Type Description Remark
Pin 6 R/W input LOW is read from TEA5880TS;
HIGH is write to TEA5880TS
Pin 8 CLOCK input clock rising edge
Pin 7 DATA input/output bidirectional data
Fig 4. Digital interface block diagram.
001aaa668
OUTPUT
SOURCE
SELECTOR
CONTROL
REGISTER A
ADDRESS
DECODER
CONTROL
REGISTER B
CONTROL
REGISTER C
REST OF THE
REGISTERS
STATUS REGISTER
15 BITS SIPO (SERIAL IN PARALLEL OUT)
stereo LED
stereo clock
IF OSC
R/W
FM OSC
CLOCK
DATA
COUNTER 1 (16 bits)
16 BITS PISO (PARALLEL IN SERIAL OUT)
R/W
11 bits data
4 bits data
16 bits data 16 bits data
CLOCK R/W
R/W
enable
counter 1
control bits
control bits
control bits
control bits
1-bit data

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 9 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
8.1 Register description
[1] The application should write logic 0 to this register at start-up to ensure that the device functions correctly.
Table 5: TEA5880TS registers description
Address Register name Access Operation Data width Clocks
0000b VADC write only VADC register 11 bits 15
0001b CTRL_C write only control register C 11 bits 15
0010b CTRL_A write only control register A 11 bits 15
0011b OSC_STEREO write only oscillator stereo
decoder clock 11 bits 15
0100b CTRL_B write only control register B 11 bits 15
0101b CAP_FM write only capacitor bank FM 11 bits 15
0110b OSC_IF write only oscillator IF 11 bits 15
0111b OSC_FM write only oscillator FM 11 bits 15
- STATUS read only status register 16 bits 15
- COUNTER read only counter register 16 bits 15
Table 6: VADC - (address 0h) bit description
Bit Symbol Description
14 to 11 - address bits
10 to 6 VADC2[4:0] controls the width filter
5 - not applicable; should be written to logic 0
4 to 0 VADC1[4:0] controls the center filter
Table 7: CTRL_C - (address 1h) bit description[1]
Bit Symbol Description
14 to 11 - address bits
10 and 9 - reserved for production test; should be written to logic 0
8 - reserved for swapping counters1 and 2; should be written to logic 0
7 to 4 - not applicable; should be written to logic 0
3 to 1 - reserved for time delay selection (counter 2); application should keep
bits 3 to 1 at logic 0; see Table 8
0 - reserved for enable counter 2; should be written to logic 0
Table 8: Time delay selection
Value Decimal Stop value
000b 0 count 2
001b 1 count 8
010b 2 count 32
011b 3 count 128
100b 4 count 512
101b 5 count 2048
110b 6 count 8192
111b 7 count 32768

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 10 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
[1] The frequency is decreased when increasing the content of this register.
Table 9: CTRL_A - (address 2h) bit description
Bit Symbol Description
14 to 11 - address bits
10 to 7 OUTPUT_
SELECT[3:0] selects an internal circuit as output for measurement purpose; see Table 10
6 STE_PMUTE mutes the stereo PLL when set to logic 1; this bit should be
set during calibration of the stereo decoder clock and should be
cleared during normal operation
5 DEM_PMUTE mutes the demodulator PLL when set to logic 1; this bit
should be set during calibration of the IF frequency and should
be cleared during normal operation
4 STE_INT_OFF# turns off the stereo integrator loop when set to logic 0
3 EN_MEAS# enables measurement when set to logic 0
2 AMUTE mutes the audio when set to logic 1
1 FM enables the FM circuitry when set to logic 1
0 - reserved for AM circuitry; should be written to logic 0
Table 10: Description of OUTPUT_SELECT bits
Symbol Value Decimal Output selected
OS-NONE 0000b 0 no output selected
OS_FM_OSC 0001b 1 FM oscillator
OS_NA2 0010b 2 not defined
OS_CNT2_RDY_NA 0011b 3 reserved for counter 2 ready output
OS_NA4 0100b 4 not defined
OS_STEREO_DEC 0101b 5 stereo decoder clock
OS_NA6 0110b 6 not defined
OS_STEREO_LED 0111b 7 stereo LED
OS_NA8 1000b 8 not defined
OS_IF_OSC 1001b 9 IF oscillator
OS_INTERRUPT_NA 1010b 10 reserved for interrupt output
OS_PISO 1011b 11 PISO output (reading STATUS / COUNTER
register)
OS_NA12 1100b 12 not defined
OS_RDS_NA 1101b 13 reserved for RDS output
OS_NA14 1110b 14 not defined
OS_NA15 1111b 15 not defined
Table 11: OSC_STEREO - (address 3h) bit description[1]
Bit Symbol Description
14 to 11 - address bits
10 to 0 SO[10:0] 11-bit digital-to-analog converter for adjusting the stereo decoder clock

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Preliminary data sheet Rev. 02 — 26 April 2004 11 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
[1] The frequency is decreased when increasing the content of this register (more capacitors).
Table 12: CTRL_B - (address 4h) bit description
Bit Symbol Description
14 to 11 - address bits
10 L_CNT latch counter: a transition from logic 1 to logic 0 will latch the
COUNTER register into the PISO (reading the PISO hereafter will read
the COUNTER register)
9 L_STS latch status: a transition from logic 1 to logic 0 will latch the STATUS
register into the PISO (reading the PISO hereafter will read the STATUS
register)
8 to 6 - reserved for output level control; should be written with 4 (100b);
see Table 13
5 DEEMP de-emphasis: logic 1 is 75 µs (USA), logic 0 is 50 µs (Europe, Japan)
4 PISO_CLR a transition from logic 1 to logic 0 will clear the PISO; the PISO should
be clear before reading the STATUS/COUNTER register
3 CNT_RST a transition from logic 1 to logic 0 will clear both counter 1 and counter 2
2 CNT1_EN counter 1 enabled (counting mode) when set to logic 1
1 - should be written to logic 0
0 MONO mono mode when set to logic 1, stereo mode when set to logic 0
Table 13: Description of output level control register bits
Value Decimal Output level
0000b 0 12 mV
0001b 1 20 mV
0010b 2 35 mV
0011b 3 60 mV
0100b 4 100 mV
0101b 5 170 mV
0110b 6 200 mV
Table 14: CAP_FM - (address 5h) bit description[1]
Bit Symbol Description
14 to 11 - address bits
10 - reserved for capacitor extra current; this bit should be written to logic 1
by any access to the CAP_FM to ensure that the device functions
properly
9 to 8 - reserved, should be written to logic 0
7 to 0 FC[7:0] FM capacitor bank switches for adjusting the FM (RF) frequency in big
steps. Every bit, when set, will switch on a capacitor with a weight
according to its position i.e. bit 0 has weight 1, bit 1 has weight 2, bit 2
has weight 4 etc, bit 6 has weight 64, except for bit 7, which also has the
same weight as bit 6; there is thus only 71⁄2effective bits; this means
that the value range 0 to 127 will switch on different capacitors the value
range 128 to 191 switches on the same capacitors as range 64 to 127,
the value range 192 to 255 will switch on different capacitors (an
overlapped range of 64 values caused when FC[7:6] = 01b or 10b)

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Preliminary data sheet Rev. 02 — 26 April 2004 12 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
[1] The frequency is decreased when increasing the content of this register.
[1] The frequency is increased when increasing the content of this register.
[1] This register does not have an address. To read the status register, latch its content into the PISO (using
L_STS bit in control register B) then read out the PISO.
[1] This register does not have an address. To read the counter register, latch its content into the PISO (using
L_CNT bit in control register B) then read out the PISO.
Table 15: OSC_IF - (address 6h) bit description[1]
Bit Symbol Description
14 to 11 - address bits
10 to 0 IFO[10:0] 11-bit digital-to-analog converter for adjusting the IF frequency
Table 16: OSC_FM - (address 7h) bit description[1]
Bit Symbol Description
14 to 11 - address bits
10 to 0 FO[10:0] 11-bit digital-to-analog converter for adjusting the FM frequency in fine steps;
this register is used in combination with the CAP_FM register to set a FM
frequency
Table 17: STATUS - bit description[1]
Bit Symbol Description
15 to 9 FS[6:0] field strength, indicated by the amount of bits set:
0 bits set = < 10 dBµV
1 bit set = 10 dBµV to 20 dBµV
2 bits set = 20 dBµV to 30 dBµV
3 bits set = 30 dBµV to 40 dBµV
4 bits set = 40 dBµV to 50 dBµV
5 bits set = 50 dBµV to 60 dBµV
6 bits set = 60 dBµV to 70 dBµV
7 bits set = > 70 dBµV
8 - not applicable; always read as logic 1
7 to 5 R[2:0] chip revision; the revision for TEA5880TS is 100b
4 to 3 - not applicable; always read as logic 1
2 - reserved for production test
1 - not applicable; always read as logic 1
0 - reserved for production test
Table 18: COUNTER - bit description[1]
Bit Symbol Description
15 to 0 CNT[15:0] pulses counted during the period that the counter is enabled and the NR/W
line the 3 wire bus is low

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Preliminary data sheet Rev. 02 — 26 April 2004 13 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
8.2 Accessing the TEA5880TS
Access to the TEA5880TS can be achieved via the 3-wire bus. At the host side, the R/W
and CLOCK are output signals, while the DATA signal is bidirectional.
When powered up, the host should initialize the 3-wire bus in the host read mode as
follows:
1. Set (at host side) the DATA line into input mode
2. R/W set to LOW
3. CLOCK set to LOW.
Note: Use the following sequence for changing read/write mode:
1. To change from host read mode to host write mode proceed as follows:
a. Keep the CLOCK signal LOW
b. Set the R/W signal to HIGH (write mode)
c. Set the DATA pin (of the application controller) into output mode.
2. To change from host write mode to host read mode proceed as follows:
a. Keep the CLOCK signal LOW
b. Set the DATA pin (of the application controller) into input mode
c. Set R/W to LOW (input mode).
8.3 Writing to the TEA5880TS
Writing to the TEA5880TS is achieved with a 15-bit data pattern:
•D[14:11]: 4-bit register address
•D[10:0]: 11-bit register data.
The data pattern is sent serially to the TEA5880TS as follows:
1. Drive R/W pin HIGH to set the TEA5880TS in input mode
2. Drive the DATA pin to correct level
3. Generate positive edge of CLOCK (driving CLOCK into LOW-to-HIGH transition)
4. Delay some time to meet the data hold time requirement
5. Driving CLOCK into HIGH-to-LOW transition
6. Repeat step (2) to (5) 15 times to shift the 15-bit data pattern into the TEA5880TS
7. Drive R/W pin LOW; this signals the TEA5880TS to latch the data into the correct
register.
Note: The application should shift the LSB out first.

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Preliminary data sheet Rev. 02 — 26 April 2004 14 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
8.4 Reading from the TEA5880TS
Only the status or the counter register can be read from the TEA5880TS.
These are 16-bit registers and can be read serially as follow:
1. Select OS_PISO (parallel in, serial out) as output (control register A,
OUTPUT_SELECT bits)
2. Clear the PISO (control register B, PISO_CLR bit, pulse HIGH-to-LOW transition)
3. Latch the counter register (control register B, L_CNT bit, pulse HIGH-to-LOW
transition) or the status register (control register B, L_STS bit, pulse HIGH-to-LOW
transition) into the PISO
4. Drive R/W pin LOW to set the TEA5880TS in output mode
5. Read the first bit at pin DATA
6. Generate positive CLOCK pulse (LOW-to-HIGH transition)
7. Delay for a period of time to meet the data set-up time requirement
8. Read the data bit at pin DATA
9. Drive CLOCK into HIGH-to-LOW transition
10.Repeat step (6) to (9) 15 times to shift the remaining 15 bits of data out of the chip
Note: The TEA5880TS will shift the MSB out first.
8.5 Measuring frequency with the TEA5880TS
The three frequencies: IF, stereo decoder clock and FM can be measured by using the
counter register and a software timing window. This is achieved as follows:
1. Select the output to be measured (control register A, OUTPUT_SELECT bits, select
OS_STEREO_DEC, OS_IF_OSC or OS_FM_OSC output)
2. Enable measure mode (clear EN_MEAS# bit of control register A)
3. Reset the counter (control register B, CNT_RST bit, pulse HIGH-to-LOW transition)
4. Start the counter on the TEA5880TS (control register B, set CNT1_EN bit); at the
moment the R/W signal goes LOW the counter starts
5. Wait time t
6. To stop the counter, first set the R/W signal HIGH, then disable the counter in the
TEA5880TS (control register B, clear CNT1_EN bit)
7. Read the pulse count n from the counter register of the TEA5880TS
8. Restore the measure mode
9. Restore the output select bits.
Note: The measuring window begins at the moment the R/W signal is driven LOW (point
4) and ends when the R/W signal is driven HIGH (point 6).

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 15 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
The IF and stereo decoder frequency can be calculated using the equation f = n/t, and the
FM frequency can be calculated using the equation f = (n/t) x 256.
Note: The precision of ‘f’ depends on the following:
•The duration of t. 1 pulse wrong at t = 1 ms results in more deviation than at t = 32 ms
•The precision of the measuring window: calculate with t = 32 ms gives other ‘f’ values
than with t = 32 ms. In the application care should be taken to have an accurate
measuring window t.
8.6 Initialize the TEA5880TS
After power-up, the TEA5880TS needs to be initialized as follows:
•Control register A: STE_PMUTE = 1; DEM_PMUTE = 1; AMUTE = 1; FM = 1; other
bits = 0
•Control register B: CNT_RST = 1; PISO_CLR = 1; MONO = 1; DEEMP = 1 (for
Europe); Bit [8:6] = 100b; other bits = 0
•Control register C: All bits = 0
•VADC register: VADC1 = 26 (decimal), this value should not be changed hereafter;
VADC2 = 18 (decimal), this value should not be changed hereafter
•Calibrate the IF frequency at 110 kHz
•Calibrate the stereo decoder clock at 37.5 kHz (to reduce the initialization time,
calibration of the stereo decoder clock can be postponed until the stereo mode is
selected).
9. Timing diagrams
Fig 5. Writing data.
001aaa669
LSB MSB MSBLSB
1 1511
11-bit data 4-bit address
DATA
CLOCK
R/W

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Preliminary data sheet Rev. 02 — 26 April 2004 16 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
Fig 6. Reading data.
001aaa670
DATA LSB
0 15
MSB
16-bit data
R/W
CLOCK
Fig 7. Measuring sequence.
001aaa671
enable PISO at output source
disable 16-bit counter
timing width 8 ms to 100 ms
enable 16-bit counter to count
reset 16-bit counter clear
set 16-bit counter clear
enable internet clock
enable FM OSC at output source selector

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 17 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
10. Limiting values
[1] Machine model (R = 10 Ω, C = 200 pF, 75 µH).
[2] Human body model (R = 1.5 kΩ, C = 100 pF).
11. Thermal characteristics
12. Characteristics
Table 19: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
VCCD digital supply voltage −0.3 +5 V
VCCA analog supply voltage −0.3 +8 V
Tstg storage temperature −55 +150 °C
Tamb ambient temperature VCCA = VCC(VCO) = VCCD = 3 V −10 +75 °C
VCCA = VCC(VCO) = VCCD = 5 V −40 +85 °C
Vesd electrostatic discharge voltage
for all pins [1] −200 +200 V
[2] −2000 +2000 V
Table 20: Thermal characteristics
Symbol Parameter Conditions Typ Unit
Rth(j-a) thermal resistance from junction to ambient in free air <tbd> K/W
Table 21: Digital input AC values
Symbol Parameter Conditions Min Typ Max Unit
Digital inputs
VIH HIGH-level input voltage IOH = 500 µA 1.4 - - V
VIL LOW-level input voltage - - 0.6 V
Digital outputs
Isink (L) LOW-level sink current 500 - - µA
VOL LOW-level output voltage IOL = 500 µA - - 0.6 V
Timing
fclk clock input - - 1 MHz
tCLK(H) clock HIGH time 495 - - ns
tCLK(L) clock LOW time 495 - - ns

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 18 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
13. Components list
No external components necessary.
(1) Mono signal.
(2) Mono noise.
(3) Stereo left.
(4) Stereo right.
(5) Stereo noise.
Fig 8. Signal characteristics.
THD = 30 %.
Fig 9. Total harmonic distortion.
001aaa673
−10 1107030
−20
−40
0
20
dB
−60
(1)
(2)
(3)
(4)
(5)
RFIN (dBµV)
001aaa674
RFIN (dBµV)
−10 1107030
2
3
1
4
5
THD
(%)
0

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 19 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
14. Printed-circuit board layout for SSOP24 package
The printed-circuit board traces from LL1 to VCC1 and from VCC1 to LR1 as shown in
Figure 10, are to create two inductors, each of approximately 38 nH. These inductors,
together with internal capacitors, form part of the LC oscillator to determine the FM tuning
band. If the value of the inductors becomes much greater than 38 nH, the whole FM
tuning band (normally from 76 MHz to 108 MHz) will be shifted lower. If the value of the
inductors becomes much smaller than 38 nH, the whole FM tuning band (normally from
76 MHz to 108 MHz) will be shifted higher.
If the layout of the two inductance traces is not preferred, two SMD inductors can be used
to replace the two printed-circuit board inductance traces as an alternative. The layout of
the two SMD inductors should be as close to the pins as possible.
(1) Width of printed-circuit board trace = 0.15 mm; spacing between printed-circuit board
trace = 0.15 mm.
(2) Pins 14, 15, 16, 21, 22 and 23 are not connected.
Fig 10. Printed-circuit board layout.
001aaa675
GND
RFIN
RFGND
VCCD
AUDR
GND
n.c.
n.c.
n.c.
LR1
reserved
n.c.
n.c.
GND
LL1
MPX
3.5 mm
3.5 mm
R/W
CLOCK
DATA
AUDL
LED
VCC1
VCC1
VCCA

9397 750 13022 © Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Preliminary data sheet Rev. 02 — 26 April 2004 20 of 27
Philips Semiconductors TEA5880TS
Integrated FM stereo radio IC for host processor tuning
15. Application information
(1) optional.
Fig 11. Application diagram.
001aaa672
FM antenna
TEA5880FM
1
2
3
4
5
6
7
8
9
10
11
12
LL1
LR1
100 nF (1)
100 nF (1)
24
23
22
21
20
19
18
17
16
15
14
13
RFIN
VCCA
VCCD
LED
AUDL
MPX
CLOCK
DATA
R/W
AUDR
VCC1
VCC1