PLDA XpressGX4LP User manual

Version 1.0.8 March 2012
Copyright © PLDA 1996-2012
XpressGX4LP
Reference Manual

XpressGX4LP Reference Manual
2
XpressGX4LP
Reference Manual
Document Change History
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by PLDA SAS. Other
brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
of the product and its use contained in this document are given by PLDA in good faith. This document is provided
“as is” with no warranties whatsoever, including any warranty of merchantability, non infringement, fitness for any
particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
This document is intended only to assist the reader in the use of the product. PLDA shall not be liable for any loss
or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product. Nor shall PLDA be liable for infringement of proprietary rights relating to use of
information in this document. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.
Date DocVersion Board Version Change
March 2012 1.0.8 P120 v1.0 •Corrected clocking circuitry diagram and SFP+
interface signal specification.
•Updated configuration references.
October 2011 1.0.7 P120 v1.0 •Added fpga_adbus command (reload boot sector).
September 2011 1.0.6 P120 v1.0 •Corrected clock circuitry table and diagram.
September 2011 1.0.5 P120 v1.0 •Modified fpga_adbus signal.
•Added image of daughter card.
September 2011 1.0.4 P120 v1.0 •Modified Flash signals descriptions.
August 2011 1.0.3 P120 v1.0 •Updated documentation to reflect new features for
board version P120 v1.0, including 10G Ethernet
channels and extension interface.
June 2011 1.0.2 P117 v1.0 •Updated clocking information and block diagram.
•Added FPGA resources and board configuration
module information.
May 2011 1.0.1 P117 v1.0 •Corrected documentation bugs.
May 2011 1.0.0 P117 v1.0 •First Release

3
XpressGX4LP Reference Manual
Table of Contents
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Feedback and Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.1 Purpose of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Board Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2 XpressGX4LP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 XpressGX4LP Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Block Diagram of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Mechanical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3 XpressGX4LP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.1 Stratix IV GX FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Board Configuration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Dedicated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 PCI Express Endpoint Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 QDRII + SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 10G Ethernet Channels (SFP+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10 Mechanical Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Extension Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.11.1 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.11.2 PPS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.12 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

XpressGX4LP Reference Manual
4
Appendix A: XpressGX4LP Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix B: Voltage and Temperature Absolutes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Appendix C: XpressGX4LP Configuration References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5
XpressGX4LP Reference Manual
List of Tables
Table 1: Board features description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2: Stratix IV GX FPGA Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3: Transfer signals description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4: Timing ranges for data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5: Pin Assignments for the Flash Access Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6: Flash Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7: XpressGX4LP clock assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8: Pin assignments for the PCI Express endpoint connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9: QDRII + SRAM Banks A + B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10: QDRII + SRAM Banks C + D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11: DDR3 SDRAM Banks A + B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12: SFP+ interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13: Pin assignments for the board LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14: Pin assignments for the reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15: Pin assignments for the mechanical switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16: Pin assignments for the UART interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17: Pin assignments for the PPS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

XpressGX4LP Reference Manual
6
List of Figures
Figure 1: XpressGX4LP layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2: XpressGX4LP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3: XpressGX4LP component side with daughter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4: Max II EPM1270 Board Configuration Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5: Data transfer between the User Design and the Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6: Timing of data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7: XpressGX4LP clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8: PCI Express connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9: QDRII + SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10: DDR2 SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11: SFP+ interface connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12: 10G Ethernet connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13: LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14: Reset button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15: Mechanical switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16: Extension interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17: Extension interface pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18: UART interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19: XpressGX4LP and power supply daughter card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20: Power Distribution for the XpressGX4LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7
XpressGX4LP Reference Manual
Preface
About this Document
This document has been written for design managers, system engineers, and designers of ASICs and FPGAs who
are evaluating or using the PLDA XpressGX4LP board. Prior knowledge of PCI Express is assumed.
Additional Reading
PLDA periodically updates its documentation. Please contact PLDA Technical Support or check the Web site at
http://www.plda.com for current versions.
Please refer to the following documents for information on specification standards:
•PCI Express™ Specification, Revision 2.0
•PCI Express Card Electromechanical Specification, Revision 2.0
•Spansion Flash S29GL-N Data Sheet, Revision B, Amendment 7
Feedback and Contact Information
Feedback about this document
PLDA welcomes comments and suggestions about this documentation. Please contact PLDA Technical Support
and provide the following information:
•the title of the document
•the page number to which your comments refer
•a description of your comments
Contact information
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
Tel: USA [phone] - International [phone]
Fax: [phone]
http://www.plda.com
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For sales questions, please contact [email protected].
Technical Support
For technical support questions, please contact PLDA Support at http://www.plda.com/plda_login.php using the
Support Center if you have a PLDA online account.
If you don’t have a PLDA account, contact http://www.plda.com/support_enquiry.php.

Introduction XpressGX4LP Reference Manual
8
Chapter 1 Introduction
1.1 Purpose of the Board
The XpressGX4LP board is designed to enable all engineers, even those with little PCI Express experience, to
design complex applications using PCIe and 10GbE as their main communication interfaces.
It is a low-profile, highly-integrated PCI Express FPGA board with dual-10G Ethernet channels engineered for
both prototyping and field deployment.
The XpressGX4LP board is based on the Altera Stratix IV GX in FBGA 1517 package, and available FPGAs
include the EP4SGX230KF40C2N and the EP4SGX530KH40C2N.
1.2 Features List
•PCI Express x8 2.5/5.0 Gbps
•Dual 10G Ethernet Channel
•Two SFP+ interfaces for 10GBASE-SR, 10GBASE-LR, 10GBASE-LRM, 1000BASE-X, and Passive
Direct Attach SFP+ cable
•Built-in self-configure mode for 10G transceiver and SFP+ modules
•Stratix IV GX FPGA
•EP4SGX230 (XpressGX4-LP230HE-Gen2 and XpressGX4-LP230LE-Gen2)
•EP4SGX530 (XpressGX4-LP530HE-Gen2 and XpressGX4-LP530LE-Gen2)
•FPGA Configuration Module
•Power monitoring
•Flash Controller for FPGA and/or SoC Firmware images, accessible from PCI Express or User Design
•Clock circuitry
•40, 100, 125, 156.25, 200 and 400 MHz clocks
•Memories
•Two 1-Gbyte DDR3 SDRAM (XpressGX4-LP530HE-Gen2 and XpressGX4-LP230HE-Gen2), or
•Two 256-Mbyte DDR3 SDRAM (XpressGX4-LP230LE-Gen2 and XpressGX4-LP530LE-Gen2) with 16-bit
datapath
•Four 9-MByte QDRII+ SRAM with 9-bit datapath (XpressGX4-LP530HE-Gen2 and
XpressGX4-LP230HE-Gen2))
•64-Mbyte Flash
•General I/Os
•Four User LEDs
•Four FPGA Configuration LEDs
•Two Tx/Rx Ethernet LEDs per channel
•One Reset button
•One FPGA Configuration reload button
•One FPGA image boot selector
•Three User Switches
•Power
•PCI Express edge connector power (12V and 3.3V)
•Mechanical
•Low profile PCI Express height
A detailed description of board features can be found in Section 2.3.

9
XpressGX4LP Reference Manual Introduction
1.3 System Requirements
To use XpressGX4LP board features, you must install the PLDA Software Tools. The PLDA Software Tools can
be downloaded from PLDA’s extranet site. You can log in to the extranet from PLDA’s web site www.plda.com.
1.4 Board Configuration Requirements
•Altera USB-Blaster
•Altera Quartus 11.1

XpressGX4LP Architecture XpressGX4LP Reference Manual
10
Chapter 2 XpressGX4LP Architecture
The XpressGX4LP board is supplied by both the 12V and 3.3V of the PCI Express slot. The PCI Express 12V
generates 1.5V, 1.8V, 2.5V, and 0.9V voltages, while the 3.3V generates 1.2V and 3V voltages.
These voltages are available on the mezzanine power supply daughter card, which is mounted on the
XpressGX4LP by default. This daughter card is supplied with the XpressGX4LP board. See Section 3.12 for more
information.
The XpressGX4LP is delivered with a fansink mounted on the FPGA.
2.1 XpressGX4LP Layout
The following figure shows the component side of the XpressGX4LP board, without the mezzanine power supply
daughter card:
Figure 1: XpressGX4LP layout
User
Switches /
RST
2x SFP+
JTAG
Extension Interface
(UART + PPS) DDR3 SDRAM
(up to 2 x 1GB)
Independent banks
PCIe 8x
Gen 2
QDR2 SRAM
(up to 4 x 9MB)
(optional)
FPGA
Configuration
Module