PLDA XpressGX4LP User manual

Version 1.0.8 March 2012
Copyright © PLDA 1996-2012
XpressGX4LP
Reference Manual

XpressGX4LP Reference Manual
2
XpressGX4LP
Reference Manual
Document Change History
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by PLDA SAS. Other
brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
of the product and its use contained in this document are given by PLDA in good faith. This document is provided
“as is” with no warranties whatsoever, including any warranty of merchantability, non infringement, fitness for any
particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
This document is intended only to assist the reader in the use of the product. PLDA shall not be liable for any loss
or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product. Nor shall PLDA be liable for infringement of proprietary rights relating to use of
information in this document. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.
Date DocVersion Board Version Change
March 2012 1.0.8 P120 v1.0 •Corrected clocking circuitry diagram and SFP+
interface signal specification.
•Updated configuration references.
October 2011 1.0.7 P120 v1.0 •Added fpga_adbus command (reload boot sector).
September 2011 1.0.6 P120 v1.0 •Corrected clock circuitry table and diagram.
September 2011 1.0.5 P120 v1.0 •Modified fpga_adbus signal.
•Added image of daughter card.
September 2011 1.0.4 P120 v1.0 •Modified Flash signals descriptions.
August 2011 1.0.3 P120 v1.0 •Updated documentation to reflect new features for
board version P120 v1.0, including 10G Ethernet
channels and extension interface.
June 2011 1.0.2 P117 v1.0 •Updated clocking information and block diagram.
•Added FPGA resources and board configuration
module information.
May 2011 1.0.1 P117 v1.0 •Corrected documentation bugs.
May 2011 1.0.0 P117 v1.0 •First Release

3
XpressGX4LP Reference Manual
Table of Contents
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Feedback and Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
1.1 Purpose of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.3 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.4 Board Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 2 XpressGX4LP Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 XpressGX4LP Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Block Diagram of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.4 Mechanical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 3 XpressGX4LP Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.1 Stratix IV GX FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Board Configuration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Dedicated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 PCI Express Endpoint Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 QDRII + SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6 DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.7 10G Ethernet Channels (SFP+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.8 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.9 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10 Mechanical Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Extension Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.11.1 UART Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.11.2 PPS Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.12 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

XpressGX4LP Reference Manual
4
Appendix A: XpressGX4LP Power Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Appendix B: Voltage and Temperature Absolutes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Appendix C: XpressGX4LP Configuration References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5
XpressGX4LP Reference Manual
List of Tables
Table 1: Board features description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 2: Stratix IV GX FPGA Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3: Transfer signals description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4: Timing ranges for data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5: Pin Assignments for the Flash Access Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6: Flash Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7: XpressGX4LP clock assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8: Pin assignments for the PCI Express endpoint connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9: QDRII + SRAM Banks A + B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 10: QDRII + SRAM Banks C + D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11: DDR3 SDRAM Banks A + B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12: SFP+ interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 13: Pin assignments for the board LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 14: Pin assignments for the reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 15: Pin assignments for the mechanical switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 16: Pin assignments for the UART interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 17: Pin assignments for the PPS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

XpressGX4LP Reference Manual
6
List of Figures
Figure 1: XpressGX4LP layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 2: XpressGX4LP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 3: XpressGX4LP component side with daughter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4: Max II EPM1270 Board Configuration Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5: Data transfer between the User Design and the Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 6: Timing of data transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 7: XpressGX4LP clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8: PCI Express connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9: QDRII + SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 10: DDR2 SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 11: SFP+ interface connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12: 10G Ethernet connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 13: LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 14: Reset button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 15: Mechanical switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 16: Extension interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17: Extension interface pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 18: UART interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 19: XpressGX4LP and power supply daughter card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20: Power Distribution for the XpressGX4LP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

7
XpressGX4LP Reference Manual
Preface
About this Document
This document has been written for design managers, system engineers, and designers of ASICs and FPGAs who
are evaluating or using the PLDA XpressGX4LP board. Prior knowledge of PCI Express is assumed.
Additional Reading
PLDA periodically updates its documentation. Please contact PLDA Technical Support or check the Web site at
http://www.plda.com for current versions.
Please refer to the following documents for information on specification standards:
•PCI Express™ Specification, Revision 2.0
•PCI Express Card Electromechanical Specification, Revision 2.0
•Spansion Flash S29GL-N Data Sheet, Revision B, Amendment 7
Feedback and Contact Information
Feedback about this document
PLDA welcomes comments and suggestions about this documentation. Please contact PLDA Technical Support
and provide the following information:
•the title of the document
•the page number to which your comments refer
•a description of your comments
Contact information
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PLDA
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
Tel: USA [phone] - International [phone]
Fax: [phone]
http://www.plda.com
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For sales questions, please contact [email protected].
Technical Support
For technical support questions, please contact PLDA Support at http://www.plda.com/plda_login.php using the
Support Center if you have a PLDA online account.
If you don’t have a PLDA account, contact http://www.plda.com/support_enquiry.php.

Introduction XpressGX4LP Reference Manual
8
Chapter 1 Introduction
1.1 Purpose of the Board
The XpressGX4LP board is designed to enable all engineers, even those with little PCI Express experience, to
design complex applications using PCIe and 10GbE as their main communication interfaces.
It is a low-profile, highly-integrated PCI Express FPGA board with dual-10G Ethernet channels engineered for
both prototyping and field deployment.
The XpressGX4LP board is based on the Altera Stratix IV GX in FBGA 1517 package, and available FPGAs
include the EP4SGX230KF40C2N and the EP4SGX530KH40C2N.
1.2 Features List
•PCI Express x8 2.5/5.0 Gbps
•Dual 10G Ethernet Channel
•Two SFP+ interfaces for 10GBASE-SR, 10GBASE-LR, 10GBASE-LRM, 1000BASE-X, and Passive
Direct Attach SFP+ cable
•Built-in self-configure mode for 10G transceiver and SFP+ modules
•Stratix IV GX FPGA
•EP4SGX230 (XpressGX4-LP230HE-Gen2 and XpressGX4-LP230LE-Gen2)
•EP4SGX530 (XpressGX4-LP530HE-Gen2 and XpressGX4-LP530LE-Gen2)
•FPGA Configuration Module
•Power monitoring
•Flash Controller for FPGA and/or SoC Firmware images, accessible from PCI Express or User Design
•Clock circuitry
•40, 100, 125, 156.25, 200 and 400 MHz clocks
•Memories
•Two 1-Gbyte DDR3 SDRAM (XpressGX4-LP530HE-Gen2 and XpressGX4-LP230HE-Gen2), or
•Two 256-Mbyte DDR3 SDRAM (XpressGX4-LP230LE-Gen2 and XpressGX4-LP530LE-Gen2) with 16-bit
datapath
•Four 9-MByte QDRII+ SRAM with 9-bit datapath (XpressGX4-LP530HE-Gen2 and
XpressGX4-LP230HE-Gen2))
•64-Mbyte Flash
•General I/Os
•Four User LEDs
•Four FPGA Configuration LEDs
•Two Tx/Rx Ethernet LEDs per channel
•One Reset button
•One FPGA Configuration reload button
•One FPGA image boot selector
•Three User Switches
•Power
•PCI Express edge connector power (12V and 3.3V)
•Mechanical
•Low profile PCI Express height
A detailed description of board features can be found in Section 2.3.

9
XpressGX4LP Reference Manual Introduction
1.3 System Requirements
To use XpressGX4LP board features, you must install the PLDA Software Tools. The PLDA Software Tools can
be downloaded from PLDA’s extranet site. You can log in to the extranet from PLDA’s web site www.plda.com.
1.4 Board Configuration Requirements
•Altera USB-Blaster
•Altera Quartus 11.1

XpressGX4LP Architecture XpressGX4LP Reference Manual
10
Chapter 2 XpressGX4LP Architecture
The XpressGX4LP board is supplied by both the 12V and 3.3V of the PCI Express slot. The PCI Express 12V
generates 1.5V, 1.8V, 2.5V, and 0.9V voltages, while the 3.3V generates 1.2V and 3V voltages.
These voltages are available on the mezzanine power supply daughter card, which is mounted on the
XpressGX4LP by default. This daughter card is supplied with the XpressGX4LP board. See Section 3.12 for more
information.
The XpressGX4LP is delivered with a fansink mounted on the FPGA.
2.1 XpressGX4LP Layout
The following figure shows the component side of the XpressGX4LP board, without the mezzanine power supply
daughter card:
Figure 1: XpressGX4LP layout
User
Switches /
RST
2x SFP+
JTAG
Extension Interface
(UART + PPS) DDR3 SDRAM
(up to 2 x 1GB)
Independent banks
PCIe 8x
Gen 2
QDR2 SRAM
(up to 4 x 9MB)
(optional)
FPGA
Configuration
Module

11
XpressGX4LP Reference Manual XpressGX4LP Architecture
2.2 Block Diagram of the Board
The XpressGX4LP board is based on an Altera Stratix IV GX FPGA, as shown below:
Figure 2: XpressGX4LP block diagram
QDR2 Memories
FPGA Config Module
DDR3 Memories
Extension Interface
Clocks
400 MHz
1
I2C
1
I2C
XAUI_1
MDIO /2
50
XAUI_2
65 65 65 65
100 MHz
200 MHz
reserved
8Tx/Rx
100 Mhz
54
54
4
2
3
1
3
Bootsel
Spare (x10)
Protocore (7)
Config FPGA
125 MHz
40 MHz
clk_fpga

XpressGX4LP Architecture XpressGX4LP Reference Manual
12
2.3 Board Features
The following table describes XpressGX4LP board features:
Feature
name Description
x8 PCI Express 2.0 male
connector This connector supports PCI Express at 2.5 and 5.0 Gbps for x8, x4, and x1 link width.
SFP+ interfaces Two SFP+ interfaces are managed by an AppliedMicro QT2225-1 PHY. Both links
support 10GBASE-LRM/SR/LR, 1000BASE-X and Passive Direct Attach SFP+
Cable.
QDR II + SRAM Four independent banks of 4Mx18-bit (1 chip of CY7C2563KV18 for each bank)
are available on the board (for the XpressGX4-LP530HE-Gen2 and XpressGX4-
LP230HE-Gen2 boards only).
DDR3 SDRAM Two independent banks of up to 1GB (512M x 16-bit) DDR3 SDRAM are available.
FPGA configuration
module An 8-bit configuration module (40 MHz) is available to configure the FPGA at each board boot-up.
This module consists of two 256-Mbit Spansion Flash memories and a Max II
CPLD.
Two boot sectors are available and can be selected with the SW1-4 switch. The
XpressGX4LP board can be loaded with either a PCI Express 8x Gen2 Reference
Design (in Sector 0) or a dual 10G Ethernet test design (in Sector 1).
The FlashProm can be configured with PLDA FlashPCI software. FPGA
programming time is estimated at 700ms for the biggest FPGA from the power-
good signal.
JTAG connector The JTAG connector enables FPGA configuration via an Altera USB-Blaster and
Quartus.
Extension interface The Extension interface consists of a UART interface and a PPS interface. These
interfaces are provided via an RS232/485 serial link on an HE10 connector print
and require a custom cable.
Reset button 1 local power-on reset button on the component side of the board.
Switches 4 micro switches on the solder side.
LEDs 4 User LEDs are available on the component side of the board.
On-board clock circuitry The board features 100, 200, and 400 MHz clocks signals from the PLL connected
to the 100 MHz PCIe clock. 125 and 40 MHz clock signals are generated by two
AC oscillators, and a 156.25 MHz clock is generated for use with the Dual 10G
Ethernet PHY only.
Table 1: Board features description

13
XpressGX4LP Reference Manual XpressGX4LP Architecture
2.4 Mechanical Description
The following diagram illustrates the mechanical architecture of the XpressGX4LP board with the fansink and the
supply daughter card mounted.
Note: The overall height of the board, that is, the height of the highest component, is 14mm.
Figure 3: XpressGX4LP component side with daughter card
U1
U1
1
U3
U3
A1
U6
U6
A1
U21
U21
A1
C646
C646
JB
P2
P2
1
P3
P3
1
R166
R166
C154
C153
C153
C672
C672
R5
R61
U9
U9
A1
U12
U12
A1
R115
R63
R63
C146
C146
C653
C653
R92
C654
C149
C149
C664
C664
C657
C6
C6
+
C655
C118
C118
C658
C658
R170
R170
C647
C647
R64
R64
OSC2
OSC2
1
C120
C120
OSC3
OSC3
1
R129
C659
C659
C673
C673
R19
R19
C660
C660
C147
C147
R21
R21
C648
C648
R26
R26
R27
R25
C151
C150
C150
R23
R29
R29
R28
R20
R20
R112
R113
C152
R114
C665
C24
R24
JTAG
JTAG
R134
U18
U18
A2
C22
R145R145
BP1
BP1
R146
R146
DS3
K
DS4
K
DS5
DS5
K
DS2
DS2
K
C656
C169 C169
R198
U14
U14
R168
R168
RS422P
RSGND
T1OUT
T2OUT
T2OUT
RS422N
R1IN
R1IN
R2IN
R2IN
R190
R190 R195R195
C143
C142
C141
V1
V1
V12
V12
R194
SFP1
SFP1
1
SFP2
SFP2
1
L4
L4
L3
L3
CV1
CV1
R125
R193
VBAT
VBAT
GBAT
GBAT
R192R192
RS2V5RS2V5
C249
C249 +
C247
C247
+
VPCIE1
VPCIE1
C148
C148
U7
U7
1
C3
+
C12
+
C16
C16
+
C17
C17
+
C39
C39
C42
C42
C44
C47
+
C51
CV2
CV2
CV3
CV3
CV4
CV4
DS1
DS1
K
FAN12V
FAN12V
GNDBAT
R6
R12
R12
SW2
SW2
1
T1
T1
TP12
TP12V
U15
U15
VCCBAT
VCCBAT
1
B49
B1
PLDA
P120_XpressGX4_lp_v1_1
www.plda.com
PLDA
P121_XpressGX4_supply_v1_2
www.plda.com
+12V
39.15mm
7.45mm
11.65mm
12.15mm
57.15mm
4.85mm
167.65mm
15.00mm
7.50mm
46.19
64.40mm
68.90mm
71.20
1.90mm
9.35mm
53.90mm
3.65mm

XpressGX4LP Features XpressGX4LP Reference Manual
14
Chapter 3 XpressGX4LP Features
3.1 Stratix IV GX FPGA Device
The XpressGX4LP board can be mounted with either the Altera EP4SGX230KF40C2N FPGA or the
EP4SGX530KH40C2N FPGA. The following table shows the resources of each available Stratix IV GX FPGA:
3.2 Board Configuration Module
The XpressGX4LP board uses the EPM1270 Max II CPLD as an FPGA Configuration Module for:
•FPGA configuration from the Flash Memory (Sector 0 or 1)
•Flash updates from PCI Express
•IP protection
•PLL configuration
•Flash user access
•Power up or Reset controller
The following diagram shows the board configuration module:
Figure 4: Max II EPM1270 Board Configuration Module
FPGA ALMs LEs M9K RAM
Blocks M144k Blocks MLAB Blocks Total RAM 18b x 10b Multipliers PLL
230 91200 228000 1235 22 4560 17133kb 1288 8
530 212480 531200 1280 64 10624 27376kb 1024 8
Table 2: Stratix IV GX FPGA Resources
mperst #
Flash
Access
Module
PLL Config
Power-Up and
Reset CTRL
IP Protection
/32
/16
/16
@/ctrl
/3
FPGA
clk_fpga
clk_max
.
.
.
Push
Button
Clocks
SW1-4
fpga_adbus
FPP

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XpressGX4LP Reference Manual XpressGX4LP Features
You can use two different methods to program the Flash using the Board Configuration Module. The default
method is to use PLDA’s FlashPCI software, which programs the FPGA images into the Flash over PCI Express.
This method uses the reference design in order to program the Flash (Sector 0/1). (See the Getting Started for
more information about FPGA configuration).
The second method is to use the Flash Access Module to program data from the user design. This method is
particularly appropriate for Nios II Processor-based designs. For example, Flash Sector 0 can be used to store the
FPGA image, and Flash Sector 1 used to store the Nios firmware.
The User Design can access the Flash Access Module using fpga_adbus, which is a single-master (User Design),
single-slave (Flash Access Module) bus. This bus enables data to be read from and written to the Flash, as well as
enabling the revision register to be read and Flash commands to be written.
The following diagram illustrates data transfer using fpga_adbus. Note that all transfers are based on three cycles
(Command, Write Data, and Read Data) and that each cycle is mandatory:
Figure 5: Data transfer between the User Design and the Flash
The following table describes each signal used to make transfers between the User Design and the Flash:
Signal Name Description
fpga_req The User Design drives this signal, which is used to request a read/write transaction.
Active on the falling edge, data is posted on its rising edge.
fpga_read The User Design drives this signal, which is used to request a read data transfer. Active
on the falling edge, this signal is deasserted when cpld_busy is low.
fpga_adbus[31:0] This is a bi-directional bus that transfers data in three cycles:
•1st cycle: Command word driven by User Design
•fpga_adbus[31]: Unused
•fpga_adbus[30:28]: Command:
•001: Read data Flash
•010: Write Flash command
•011: Read revision register (must be F2Cxxxxx)
•100: Program data to Flash: This command is related to the two-cycle Flash
command ’Unlock Bypass Program’; using this command enables you to
bypass the first cycle, which is then automatically generated by the CPLD (see
the Flash documentation for further information).
•101: Reload boot sector: The boot sector to be reloaded depends on the value
of fpga_adbus[0] and can be used instead of the configuration boot switch (see
Section 3.10):
•0 = reload boot sector 0
•1 = reload boot sector 1
•fpga_adbus[27:0]: Flash address
•2nd cycle: Write data driven by User Design
•3rd cycle: Read data driven by Flash Access Module
Table 3: Transfer signals description
Command Write Data Read data
fpga_req
fpga_read
fpga_adbus
cpld_ack
cpld_busy
Command cycle Write data Read data

XpressGX4LP Features XpressGX4LP Reference Manual
16
The following diagram shows typical timing for data transfers:
Figure 6: Timing of data transfers
The following table shows the timing ranges that must be respected in order to guarantee correct data transfers:
cpld_ack Data transfer must be acknowledged by the Flash Access Module; this signal is
deasserted when fpga_req is asserted.
cpld_busy This signal indicates when the Flash Access Module is busy. Deassertion depends on
the specification for Flash memory (typically after 25 to 125ns). In order to avoid
deadlock on this bus, the User Design must check that cpld_busy is set to zero before
sending a new command to the bus.
Symbol Min. Time Max. Time
T1 25ns --
T2 50ns --
T3 50ns 75ns
T4 50ns 75ns
T5 25ns --
T6 50ns --
T7 Depends on the specification for Flash memory (typically after 25 to 125ns,
but it can take up to 0.5s during a Flash Erase Sector command)
Table 4: Timing ranges for data transfer
Signal Name Description
Table 3: Transfer signals description
Command Write Data Read data
fpga_req
fpga_read
fpga_adbus
cpld_ack
cpld_busy
T1 T2 T1 T2
T4
T4
T5
T6
T7
T3

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XpressGX4LP Reference Manual XpressGX4LP Features
The following table shows pin assignments for the Flash Access Module signals:
The following table shows the memory mapping for the Flash Access Module:
Pin Signal Pin Signal
AC32 fpga_adbus[0] AD30 fpga_adbus[21]
AC31 fpga_adbus[1] AB31 fpga_adbus[22]
AJ35 fpga_adbus[2] AD28 fpga_adbus[23]
AJ34 fpga_adbus[3] AD29 fpga_adbus[24]
AH35 fpga_adbus[4] AG31 fpga_adbus[25]
AH34 fpga_adbus[5] AG32 fpga_adbus[26]
AK35 fpga_adbus[6] AC28 fpga_adbus[27]
AK34 fpga_adbus[7] AG27 fpga_adbus[28]
AL35 fpga_adbus[8] AB27 fpga_adbus[29]
AL34 fpga_adbus[9] AB28 fpga_adbus[30]
AH33 fpga_adbus[10] AB30 fpga_adbus[31]
AH32 fpga_adbus[11] -- --
AD26 fpga_adbus[12] AK30 fpga_req
AN34 fpga_adbus[13] AK31 fpga_read
AM35 fpga_adbus[14] AH27 cpld_ack
AM34 fpga_adbus[15] AC29 cpld_busy
AK33 fpga_adbus[16] -- --
AJ32 fpga_adbus[17] -- --
AE29 fpga_adbus[18] -- --
AE28 fpga_adbus[19] -- --
AD31 fpga_adbus[20] -- --
Table 5: Pin Assignments for the Flash Access Module
Name Size Address
FPGA Sector 1 or User Sector
(SW1-4 = 1) 32MB 3FF FFFF
200 0000
Sector 0 
(SW1-4 = 0) 32MB 1FF FFFF
000 0000
Table 6: Flash Memory Mapping

XpressGX4LP Features XpressGX4LP Reference Manual
18
3.3 Dedicated Clocks
The following diagram shows clock circuitry for the XpressGX4LP:
Figure 7: XpressGX4LP clock circuitry
/2
/2
/2
/2
fpllout1
xpllout1
fpllout2
xpllout2
2
40 MHz +/- 100ppm
125 MHz +/- 100ppm
/1
/1
clk_fpga
ext_osc4
156.25 MHz
/2
/2
/2
/2
/2
PCIe_CLK_400MHZ (500 fs RMS jitter)
PCIe_CLK_100MHZ
AV19
n(AE35)
p(AE34)
n(AN1); p(AN2)
n(AL1); p(AL2)
n(J39); p(J38)
n(G39); p(G38)
n(AA39); p(AA38)
n(AA35); p( AB34)
n(W39); p( W38)
n(AC35); p(AC34)
n(W1); p(W2)
Global Clock (CMOS)
Global Clock (LVDS)
Transceiver Ref Clock (LVDS)
Transceiver Ref Clock (PCML)
Transceiver Ref Clock (PCML)
Transceiver Ref Clock (LVPECL)
Global Clock (LVDS)
Global Clock (LVDS)
ext_clk0 (100 Mhz)
ext_clk1 (200 Mhz)
ext_clk3 (reserved)

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XpressGX4LP Reference Manual XpressGX4LP Features
The following table describes clock assignments for the board:
Signal FPGA Pin Type Comment
PCIe_CLK_100MHz_p/n AA38/AA39 PCML 1.4 100 MHz Transceiver REFCLK for PCIe Gen2 (LMK03033C
output). This is a fixed clock signal coming from the PCIe clock.
PCIe_CLK_400MHz_p/n W38/W39 PCML 1.4 not currently used
Ext_clk0_p/n AB34/AA35 LVDS 100 MHz fixed clock for DDR3/QDR2 (LMK03033C output user
configurable)
Ext_clk1_p/n AC34/AC35 LVDS 200 MHz fixed user clock (LMK03033C output user
configurable)
Ext_clk3_p/n W2/W1 LVPECL not currently used
fpllout1_p/n AN2/AN1 LVDS not currently used (see the documentation for the Dual 10G
Ethernet PHY for more information).
fpllout2_p/n J38/J39 LVDS
xpllout1_p/n AL2/AL1 LVDS Either off, 156.25 Mhz, or 312.5 MHz fixed clock depending on
the configuration of the Dual 10G Ethernet PHY
xpllout2_p/n G38/G39 LVDS
clk_fpga AV19 CMOS Single-ended 40 MHz clock used for the MAX II CPLD and
FPGA.
Ext_osc4_p/n AF34/AE35 LVDS 125 MHz +/- 100ppm dedicated to PCIe Hard IP.
Table 7: XpressGX4LP clock assignments

XpressGX4LP Features XpressGX4LP Reference Manual
20
3.4 PCI Express Endpoint Connector
The x8 PCI Express male connector enables access to Endpoint PCI Express components as a x1, x4, or x8 PCI
Express 2.0 Link.
Figure 8: PCI Express connector
The table below describes pin assignments for the PCI Express Endpoint connector. Shaded signals are defined
as optional by the PCI Express Card Electromechanical Specification 2.0, and signals that appear bold are active
signals implemented on the XpressGX4LP.
Side B Side A
PCI Express
Pin FPGA Pin Signal PCI Express Pin FPGA Pin Signal
1-- +12V 1connected to
mPRSNT#2 mPRSNT1#
2-- +12V 2-- +12V
3-- RSVD 3-- +12V
4-- GND 4 -- GND
5-- RSVD 5nc JTAG2
6-- RSVD 6nc JTAG3
7-- GND 7 nc JTAG4
8-- +3.3V 8nc JTAG5
9nc JTAG1 9-- +3.3V
10 Linked to 3.3V
via a jumper 3.3Vaux 10 -- +3.3V
11 nc mWAKE#11 AN35 mPERST#
-- -- -- --
12 -- RSVD 12 -- GND
13 -- GND 13 connected to
LMK03033C PCIe_CLKp
14 AU38 mPERp0 14 PCIe_CLKn
15 AU39 mPERn0 15 -- GND
16 -- GND 16 AT36 mPETp0
Table 8: Pin assignments for the PCI Express endpoint connector