PLDA XpressGX5LP-SE User manual

Version 1.0.0 November 2013
Copyright © PLDA 1996-2013
XpressGX5LP-SE
Reference Manual

XpressGX5LP-SE Reference Manual
2
XpressGX5LP-SE
Reference Manual
Document Change History
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by PLDA SAS. Other
brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
of the product and its use contained in this document are given by PLDA in good faith. This document is provided
“as is” with no warranties whatsoever, including any warranty of merchantability, non infringement, fitness for any
particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
This document is intended only to assist the reader in the use of the product. PLDA shall not be liable for any loss
or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product. Nor shall PLDA be liable for infringement of proprietary rights relating to use of
information in this document. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.
Date Doc Version Board Version Change
November 2013 1.0.0 P128 v1.0.0 •First release

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XpressGX5LP-SE Reference Manual
Table of Contents
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Feedback and Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1 Purpose of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Board Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 XpressGX5LP-SE Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 XpressGX5LP-SE Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Block Diagram of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Mechanical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 3 XpressGX5LP-SE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1 Stratix V GX FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Board Configuration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 FlashPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Dedicated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 PCI Express Endpoint Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 QDR2+ SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 DDR3L SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 Dual SFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 Dual Tri-Color LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Mechanical Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

XpressGX5LP-SE Reference Manual
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List of Tables
Table 1: Board features description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2: Stratix V GX FPGA Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3: FlashPROM pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4: FPGA and CPLD pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5: Flash Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6: XpressGX5LP-SE clock assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7: Pin assignments for the PCI Express endpoint connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8: QDR2+ SRAM pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9: DDR3L SDRAM pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10: SFP+ pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11: Dual tri-color LED pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12: Pin assignments for the board LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13: Pin assignments for the reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14: Pin assignments for the mechanical switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15: Pin assignments for the EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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XpressGX5LP-SE Reference Manual
List of Figures
Figure 1: XpressGX5LP-SE layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2: XpressGX5LP-SE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3: XpressGX5LP-SE component side with daughter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4: JTAG Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5: Board configuration components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6: Max V 5M2210ZF256 board configuration and management module. . . . . . . . . . . . . . . . . . . 14
Figure 7: PCI Express connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8: QDR2+ SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9: DDR3L SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10: QSFP+ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11: 10/1 Gbs links using the Dual SFP+ interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12: User LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13: Reset button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14: Mechanical switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 15: Power Distribution for the XpressGX5LP-SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

XpressGX5LP-SE Reference Manual
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Preface
About this Document
This document has been written for design managers, system engineers, and designers ofASICs and FPGAs who
are evaluating or using the PLDA XpressGX5LP-SE board. Prior knowledge of PCI Express is assumed.
Additional Reading
PLDA periodically updates its documentation. Please contact PLDA Technical Support or check the Web site at
http://www.plda.com for current versions.
Please refer to the following documents for information on specification standards:
•PCI Express™ Specification, Revision 2.0
•PCI Express Card Electromechanical Specification, Revision 2.0
Feedback and Contact Information
Feedback about this document
PLDA welcomes comments and suggestions about this documentation. Please contact PLDA Technical Support
and provide the following information:
•the title of the document
•the page number to which your comments refer
•a description of your comments
Contact information
Corporate Headquarters
PLDA
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Rue Guillibert
13856 Aix-en-Provence Cedex 3 - France
Tel: USA [phone] - International [phone]
Fax: [phone]
http://www.plda.com
Sales
For sales questions, please contact [email protected].
Technical Support
For technical support questions, please contact PLDA Support at http://www.plda.com/plda_login.php using the
Support Center if you have a PLDA online account.
If you don’t have a PLDA account, contact http://www.plda.com/support_enquiry.php.

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XpressGX5LP-SE Reference Manual Ch.1 Introduction
Chapter 1 Introduction
1.1 Purpose of the Board
The XpressGX5LP-SE board is designed to enable all engineers, even those with little PCI Express experience, to
design complex applications using PCIe and 10 Gigabit Ethernet as their main communication interfaces.
XpressGX5LP-SE is a low-profile, highly-integrated PCI Express FPGA board with two fully independent 10 G
Ethernet channels engineered for both prototyping and field deployment.
The board is based on the Altera Stratix V GX in the FBGA 1517 package and is available with either the
5SGXEA7K2F40C2N or the 5SGXEA4K2F40C2N FPGA.
1.2 Features List
•PCI Express x8 2.5/5.0/8.0 Gbps (Gen 1, 2 or 3)
•PCI Express edge connector
•.Dual 1G/10G ethernet channels
•Two SFP+ interfaces to support 2 independent protocols on fiber optic or copper tranceivers.
•Stratix V GX FPGA
•5SGXEA7K2F40C2N or 5SGXEA4K2F40C2N
•Board configuration module
•Power monitoring
•Power-Up and reset controller
•IP protection (PLDA Protocore)
•FPGA configuration functionality supports
•Complete FPGA configuration from Flash Devices
•Flash image boot management
•FPGA re-load functionality
•Clock circuitry
•FPGA configuration (Flash): 40 MHz
•PCIe: 100 MHz
•1G/10G: 644.53125MHz Clock
•DDR3 & QDR2+ SRAM: 200 MHz
•Memories
•Two 4 GB DDR3L-1600 SDRAM with 72-bit data path (2x8GB capable)
•Two 144Mbit QDR2 + SRAM with 18-bit data path
•256 or 512 MB Flash
•Two 256Kbit I2C EEPROMs
•Extension Serial link
•Board capabilities extension or board-to-board connection over SAMTEC QSH connector (optional)
•General I/Os
•Eight user LEDs
•Four FPGA configuration LEDs
•Four tri-color LEDs on the board bracket
•One reset button
•One FPGA configuration reload button
•One FPGA image boot selector
•Three user switches
•Board-to-board Interface (4 GXB Rx/Tx + 10 LVCMOS) (optional)
•Power supply

Ch.1 Introduction XpressGX5LP-SE Reference Manual
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•PCI Express edge connector power (12 V and 3.3 V)
•Power derived directly from PCI Express slot
•Mechanical
•Low profile PCI Express height
A detailed description of board features can be found in Section 2.3.
1.3 System Requirements
To use XpressGX5LP-SE board features, you must install the PLDA Software Tools. The PLDA Software Tools
can be downloaded from PLDA’s extranet site. You can log in to the extranet from PLDA’s web site www.plda.com.
1.4 Board Configuration Requirements
•Altera USB-Blaster
•Altera Quartus 12.1 SP2 dp7

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XpressGX5LP-SE Reference Manual Ch.2 XpressGX5LP-SE Architecture
Chapter 2 XpressGX5LP-SE Architecture
The XpressGX5LP-SE board is supplied by both the 12 V and 3.3 V of the PCI Express slot. The PCI Express
12 V generates 1.35 V, 1.8 V, 2.5 V, and 0.9 V voltages, while the 3.3 V generates 3.0 V voltages.
These voltages are available on the mezzanine power supply daughter card, which is mounted on the
XpressGX5LP-SE by default. This daughter card is supplied with the XpressGX5LP-SE board. See Section 3.13
for more information.
The XpressGX5LP-SE is delivered with a fansink mounted on the FPGA.
2.1 XpressGX5LP-SE Layout
The following figure shows the component side of the XpressGX5LP-SE board with the mezzanine power supply
daughter card:
Figure 1: XpressGX5LP-SE layout

Ch.2 XpressGX5LP-SE Architecture XpressGX5LP-SE Reference Manual
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2.2 Block Diagram of the Board
The XpressGX5LP-SE board is based on an Altera Stratix V GX FPGA, as shown below:
Figure 2: XpressGX5LP-SE block diagram