PLDA XpressGX5LP-SE User manual

Version 1.0.0 November 2013
Copyright © PLDA 1996-2013
XpressGX5LP-SE
Reference Manual

XpressGX5LP-SE Reference Manual
2
XpressGX5LP-SE
Reference Manual
Document Change History
Proprietary Notice
Words and logos marked with ® or ™ are registered trademarks or trademarks owned by PLDA SAS. Other
brands and names mentioned herein may be the trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars
of the product and its use contained in this document are given by PLDA in good faith. This document is provided
“as is” with no warranties whatsoever, including any warranty of merchantability, non infringement, fitness for any
particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.
This document is intended only to assist the reader in the use of the product. PLDA shall not be liable for any loss
or damage arising from the use of any information in this document, or any error or omission in such information,
or any incorrect use of the product. Nor shall PLDA be liable for infringement of proprietary rights relating to use of
information in this document. No license, express or implied, by estoppel or otherwise, to any intellectual property
rights is granted herein.
Date Doc Version Board Version Change
November 2013 1.0.0 P128 v1.0.0 •First release

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XpressGX5LP-SE Reference Manual
Table of Contents
About this Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Feedback and Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.1 Purpose of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Features List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.4 Board Configuration Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 XpressGX5LP-SE Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.1 XpressGX5LP-SE Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Block Diagram of the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.4 Mechanical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Chapter 3 XpressGX5LP-SE Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.1 Stratix V GX FPGA Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Board Configuration Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 FlashPROM Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3 Dedicated Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 PCI Express Endpoint Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 QDR2+ SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.6 DDR3L SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7 Dual SFP+ Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.8 Dual Tri-Color LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.9 LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10 Local Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.11 Mechanical Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.12 EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.13 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

XpressGX5LP-SE Reference Manual
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List of Tables
Table 1: Board features description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2: Stratix V GX FPGA Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 3: FlashPROM pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4: FPGA and CPLD pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5: Flash Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 6: XpressGX5LP-SE clock assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7: Pin assignments for the PCI Express endpoint connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8: QDR2+ SRAM pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 9: DDR3L SDRAM pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 10: SFP+ pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 11: Dual tri-color LED pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 12: Pin assignments for the board LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 13: Pin assignments for the reset button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 14: Pin assignments for the mechanical switches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 15: Pin assignments for the EEPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

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XpressGX5LP-SE Reference Manual
List of Figures
Figure 1: XpressGX5LP-SE layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2: XpressGX5LP-SE block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3: XpressGX5LP-SE component side with daughter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4: JTAG Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5: Board configuration components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6: Max V 5M2210ZF256 board configuration and management module. . . . . . . . . . . . . . . . . . . 14
Figure 7: PCI Express connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8: QDR2+ SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 9: DDR3L SDRAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 10: QSFP+ interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 11: 10/1 Gbs links using the Dual SFP+ interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 12: User LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 13: Reset button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 14: Mechanical switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 15: Power Distribution for the XpressGX5LP-SE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

XpressGX5LP-SE Reference Manual
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Preface
About this Document
This document has been written for design managers, system engineers, and designers ofASICs and FPGAs who
are evaluating or using the PLDA XpressGX5LP-SE board. Prior knowledge of PCI Express is assumed.
Additional Reading
PLDA periodically updates its documentation. Please contact PLDA Technical Support or check the Web site at
http://www.plda.com for current versions.
Please refer to the following documents for information on specification standards:
•PCI Express™ Specification, Revision 2.0
•PCI Express Card Electromechanical Specification, Revision 2.0
Feedback and Contact Information
Feedback about this document
PLDA welcomes comments and suggestions about this documentation. Please contact PLDA Technical Support
and provide the following information:
•the title of the document
•the page number to which your comments refer
•a description of your comments
Contact information
Corporate Headquarters
PLDA
Parc club du golf - Bât. 11a
Rue Guillibert
13856 Aix-en-Provence Cedex 3 - France
Tel: USA [phone] - International [phone]
Fax: [phone]
http://www.plda.com
Sales
For sales questions, please contact [email protected].
Technical Support
For technical support questions, please contact PLDA Support at http://www.plda.com/plda_login.php using the
Support Center if you have a PLDA online account.
If you don’t have a PLDA account, contact http://www.plda.com/support_enquiry.php.

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XpressGX5LP-SE Reference Manual Ch.1 Introduction
Chapter 1 Introduction
1.1 Purpose of the Board
The XpressGX5LP-SE board is designed to enable all engineers, even those with little PCI Express experience, to
design complex applications using PCIe and 10 Gigabit Ethernet as their main communication interfaces.
XpressGX5LP-SE is a low-profile, highly-integrated PCI Express FPGA board with two fully independent 10 G
Ethernet channels engineered for both prototyping and field deployment.
The board is based on the Altera Stratix V GX in the FBGA 1517 package and is available with either the
5SGXEA7K2F40C2N or the 5SGXEA4K2F40C2N FPGA.
1.2 Features List
•PCI Express x8 2.5/5.0/8.0 Gbps (Gen 1, 2 or 3)
•PCI Express edge connector
•.Dual 1G/10G ethernet channels
•Two SFP+ interfaces to support 2 independent protocols on fiber optic or copper tranceivers.
•Stratix V GX FPGA
•5SGXEA7K2F40C2N or 5SGXEA4K2F40C2N
•Board configuration module
•Power monitoring
•Power-Up and reset controller
•IP protection (PLDA Protocore)
•FPGA configuration functionality supports
•Complete FPGA configuration from Flash Devices
•Flash image boot management
•FPGA re-load functionality
•Clock circuitry
•FPGA configuration (Flash): 40 MHz
•PCIe: 100 MHz
•1G/10G: 644.53125MHz Clock
•DDR3 & QDR2+ SRAM: 200 MHz
•Memories
•Two 4 GB DDR3L-1600 SDRAM with 72-bit data path (2x8GB capable)
•Two 144Mbit QDR2 + SRAM with 18-bit data path
•256 or 512 MB Flash
•Two 256Kbit I2C EEPROMs
•Extension Serial link
•Board capabilities extension or board-to-board connection over SAMTEC QSH connector (optional)
•General I/Os
•Eight user LEDs
•Four FPGA configuration LEDs
•Four tri-color LEDs on the board bracket
•One reset button
•One FPGA configuration reload button
•One FPGA image boot selector
•Three user switches
•Board-to-board Interface (4 GXB Rx/Tx + 10 LVCMOS) (optional)
•Power supply

Ch.1 Introduction XpressGX5LP-SE Reference Manual
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•PCI Express edge connector power (12 V and 3.3 V)
•Power derived directly from PCI Express slot
•Mechanical
•Low profile PCI Express height
A detailed description of board features can be found in Section 2.3.
1.3 System Requirements
To use XpressGX5LP-SE board features, you must install the PLDA Software Tools. The PLDA Software Tools
can be downloaded from PLDA’s extranet site. You can log in to the extranet from PLDA’s web site www.plda.com.
1.4 Board Configuration Requirements
•Altera USB-Blaster
•Altera Quartus 12.1 SP2 dp7

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XpressGX5LP-SE Reference Manual Ch.2 XpressGX5LP-SE Architecture
Chapter 2 XpressGX5LP-SE Architecture
The XpressGX5LP-SE board is supplied by both the 12 V and 3.3 V of the PCI Express slot. The PCI Express
12 V generates 1.35 V, 1.8 V, 2.5 V, and 0.9 V voltages, while the 3.3 V generates 3.0 V voltages.
These voltages are available on the mezzanine power supply daughter card, which is mounted on the
XpressGX5LP-SE by default. This daughter card is supplied with the XpressGX5LP-SE board. See Section 3.13
for more information.
The XpressGX5LP-SE is delivered with a fansink mounted on the FPGA.
2.1 XpressGX5LP-SE Layout
The following figure shows the component side of the XpressGX5LP-SE board with the mezzanine power supply
daughter card:
Figure 1: XpressGX5LP-SE layout

Ch.2 XpressGX5LP-SE Architecture XpressGX5LP-SE Reference Manual
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2.2 Block Diagram of the Board
The XpressGX5LP-SE board is based on an Altera Stratix V GX FPGA, as shown below:
Figure 2: XpressGX5LP-SE block diagram

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XpressGX5LP-SE Reference Manual Ch.2 XpressGX5LP-SE Architecture
2.3 Board Features
The following table describes XpressGX5LP-SE board features:
Table 1: Board features description
Feature
name Description For more
information,
see ...
x8 PCI Express 3.0 male
connector This connector supports PCI Express at 2.5, 5.0, and 8.0 Gbps for x8, x4, and x1 link width. PCI Express is provided via FPGA transceivers. Section 3.4
Dual SFP+ interfaces Two independent SFP+ interfaces using two GxB on the FPGA to enable two 1/
10 (or other data rate) links. Section 3.7
QDR2+ SRAM Two independant QDR2+ SRAMchips are available, which feature: Section 3.5
DDR3 SDRAM Two independent banks of DDR3L-SDRAM are available. Each bank consists of
9 x 4 Gb (8-bit wide) chips, which feature: Section 3.6
Extension serial link The extension serial link uses four Rx/Tx Gigabit links to enable board-to-board
data transfer of up to 40 Gbps. This link also provides ten other LVCMOS signals. --
Board configuration
module A 32-bit configuration module (40MHz) is available to configure the FPGA at each board power-up.
This module consists of two 2-Gbit Numonyx Flash Devices and anAltera MAX V
The Flash devices can be programmed using PLDA’s FlashPCI software. Each
device is directly connected to the FPGA and the CPLD pins.
Section 3.2
JTAG connector A mini JTAG connector is available on the board. You must use the extender
provided by PLDA to configure the FPGA via JTAG, using an Altera USB-Blaster
and Quartus.
Max V Board Manager The on board MAX V CPLD manages FPGA configuration, as well as IP
protection, CvP, partial reconfiguration and power/temperature management.
Reset button 1 local power-on reset button on the component side of the board. Section 3.10
Switches 3 micro switches on the component side. Section 3.11
Tri-color LEDs Two dual tri-color LEDs are available on the board bracket and can be used to
display information about the SFP+ connectors or user-defined information. Section 3.8
LEDs 8 user LEDs are available on the component side of the board. Section 3.9
EEPROMs Two 256k-bit Serial FlashPROMs are available for data storage via two I²C links Section 3.12
Power supply Power is provided via a daughter card supplied by the PCIe slot (12/3.3 V). Section 3.13
•144Mbit density
•18-bit data path
•separate IO
•400MHz clock Frequency
•Up to 8 Gbytes density (4 Gbytes are mounted by default)
•72-bit data path
•Up to 800 MHz clock frequency
•Maximum throughput of 12.8 Gbytes per bank

Ch.2 XpressGX5LP-SE Architecture XpressGX5LP-SE Reference Manual
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2.4 Mechanical Description
The following diagram illustrates the mechanical architecture of the XpressGX5LP-SE board without the fansink
mounted.
Note: The overall height of the board, that is, the height of the highest component, is 14mm.
Figure 3: XpressGX5LP-SE component side with daughter card

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XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features
Chapter 3 XpressGX5LP-SE Features
3.1 Stratix V GX FPGA Device
The XpressGX5LP-SE board can be mounted with either the Altera 5SGXEA7K2F40C2N or the
5SGXEA4K2F40C2N FPGA. The following table shows the resources of each available Stratix V GX FPGA:
Table 2: Stratix V GX FPGA Resources
FPGA LEs Registers M20K RAM
Blocks M20K Memory 18x18 Multipliers 27x27 Multipliers PLL
5SGXA4 420 K 634 K 1900 37 Mbits 512 512 24
5SGXA7 622 K 939 K 2560 50 Mbits 256 256 28
3.2 Board Configuration Module
3.2.1 JTAG
The XpressGX5LP-SE features a mini JTAG connector. A 10cm cable is provided with the board so you can
configure the FPGA with your USB-BLASTER and Quartus.
The cable must be plugged into the board as shown in the following picture:
Figure 4: JTAG Connector
3.2.2 FlashPROM Configuration
The XpressGX5LP-SE uses an Altera 5M2210ZF256C5N MAX V CPLD as a 32-bit FPP configuration module.
This module consists of two 256MB PC28F00BP30EFA Micron 16-bit FlashPROMs that are directly connected to
the FPGA on the FPP configuration interface.
At power-up, the CPLD acts as an address counter to configure the FPGA.
Both FlashPROMs are accessible via the FPGA and the CPLD (data, address and control signals are shared
between these devices).
Switch (SW1-4) is available to select a boot sector (0 or 1).

Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual
14
The following figure shows the configuration components of the XpressGX5LP-SE:
Boot sector selection switch (SW1-4)
LEDs
JTAG Conf RST
Figure 5: Board configuration components
The following diagram shows the board configuration module:
Figure 6: Max V 5M2210ZF256 board configuration and management module

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XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features
The following table shows pin assignments for the FlashPROM:
Table 3: FlashPROM pin assignments
flash_data00 AP33 B12 flash_ad00 AJ29 K2 flash1_adv# AK26 B9
flash_data01 AT33 C12 flash_ad01 AK30 N1 flash1_ce# AL26 D10
flash_data02 AR33 B16 flash_ad02 AW23 P2 flash1_oe# AM25 A10
flash_data03 AU34 C11 flash_ad03 AU23 M3 flash1_rst# AN25 C10
flash_data04 AU33 D11 flash_ad04 AP25 M4 flash1_wait AN24 C9
flash_data05 AN31 B14 flash_ad05 AK29 K3 flash1_we# AL25 A9
flash_data06 AM31 A11 flash_ad06 AR25 N2 flash1_wp# AN26 E10
flash_data07 AU32 A13 flash_ad07 AL30 J1 -- -- --
flash_data08 AT32 B10 flash_ad08 AL29 L1 flash2_adv# AL27 B3
flash_data09 AR31 D12 flash_ad09 AV25 N3 flash2_ce# AL28 C4
flash_data10 AP31 C13 flash_ad10 AU24 L4 flash2_oe# AN28 A4
flash_data11 AW34 B13 flash_ad11 AW25 M2 flash2_rst# AM28 C3
flash_data12 AV34 B11 flash_ad12 AP27 J2 flash2_wait AK27 B1
flash_data13 AW31 A15 flash_ad13 AU26 L2 flash2_we# AN27 A2
flash_data14 AV31 A12 flash_ad14 AU25 M1 flash2_wp# AJ27 C2
flash_data15 AW32 E11 flash_ad15 AV26 L5 -- -- --
flash_data16 AV32 E6 flash_ad16 AW26 K5 flash_clk AM26 B4
flash_data17 AJ33 F5 flash_ad17 AP28 G1 -- -- --
flash_data18 AH33 F6 flash_ad18 AR27 G2 -- -- --
flash_data19 AL33 G3 flash_ad19 AT26 H2 -- -- --
flash_data20 AK33 D1 flash_ad20 AU27 L3 -- -- --
flash_data21 AK32 E5 flash_ad21 AM29 F4 -- -- --
flash_data22 AJ32 D3 flash_ad22 AT24 J3 -- -- --
flash_data23 AH31 C8 flash_ad23 AV23 K4 -- -- --
flash_data24 AG31 G4 flash_ad24 AT27 H1 -- -- --
flash_data25 AF31 G5 flash_ad25 AR28 F3 -- -- --
flash_data26 AE31 E7 flash_ad26 AT23 H3 -- -- --
flash_data27 AJ30 E3 -- -- -- -- --
flash_data28 AH30 E2 -- -- -- -- --
flash_data29 AR30 D8 -- -- -- -- --
flash_data30 AP30 D2 -- -- -- -- --
flash_data31 AU30 E1 -- -- -- -- --
Flash Data FPGA CPLD Flash
Address FPGA CPLD Flash
Control
Signal FPGA CPLD

Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual
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The following table shows the pin assignments for the FPGA and CPLD configuration signals:
FPGA Configuration Signals
Signal CPLD Signal Name/Function FPGA
nConfig K13 nConfig AK35
Conf_done K15 Conf_done AH6
Nstatus L15 nstatus AM5
Init_done K12 Init_done AL34
Dclk_cpld J4 Dclk_CPLD AC31
Msel0 H14 Msel0 AA9
Msel1 G14 Msel1 AA10
Msel2 H15 Msel2 AD8
Msel3 G15 Msel3 AG8
Msel4 H16 Msel4 AH7
CPLD Configuration Signals
osc_config_cpld H5 osc_config_fpga AV29
clrconfig# E14 Reset push button (BPCONF) --
Max_SW0 C14 Configuration boot sector switch
(SW1-4) --
flash_reload_enable
(conf_rfu0) L14 Flash reload enable AV22
flash_boot_number
(conf_rfu1) N14 Flash boot number AR24
Conf_rfu2 K14 Conf_rfu2 AR22
conf_rfu3 J14 conf_rfu3 AU21
conf_rfu4 N15 conf_rfu4 AM23
conf_rfu5 M15 conf_rfu5 AW22
conf_rfu6 M14 conf_rfu6 AP24
CPLD Configuration LEDs
cpld_confdone R13 CPLDOK LED (green) --
max_leduser0 R14 DSMAX0 LED (Red) --
max_leduser1 T15 DSMAX1 LED (Green) --
max_leduser2 R16 DSMAX2 LED (Orange) --
XpressGX5LP-SE Power Management
ddr3_pgood D4 DDR3 termination supply power
good --
ddr3_slp_s3 D6 DDR3 termination supply enable --
por_VCCA_GXB N10 VCCA_GXB Power on Reset --
Table 4: FPGA and CPLD pin assignments

17
XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features
por_VCCR_GXB F14 VCCR_GXB Power on Reset --
fpga_power_good F15 FPGA power good AC25
Protocore Dedicated Signals
prot0_out G13 prot0_out AG26
prot1_in0 E12 prot1_in0 AE25
prot1_in1 E13 prot1_in1 AF23
prot1_out F12 prot1_out AE24
prot2_in0 H13 prot2_in0 AG24
prot2_in1 G12 prot2_in1 AE23
prot2_out F13 prot2_out AJ26
fpga_proto_misc0 A5 fpga_proto_misc0 AB27
fpga_proto_misc1 A7 fpga_proto_misc1 AA26
fpga_proto_misc2 C7 fpga_proto_misc2 AC26
fpga_proto_misc3 B6 fpga_proto_misc3 AA27
fpga_proto_misc4 A6 fpga_proto_misc4 AC27
fpga_proto_misc5 B7 fpga_proto_misc5 AD26
proto_led0 M11 DSMAX3 LED (Red) --
proto_led1 M12 DSMAX4 LED (Green) --
proto_led2 M7 DSMAX5 LED (Orange) --
proto_led3 M6 DSMAX6 LED (Green) --
XpressGX5LP-SE Temp MGT
-- -- fpga_temp_n (LM83) P5
-- -- fpga_temp_p (LM83) R6
smb_temp_clk N8 LM83 (U38.14) --
smb_temp_d P12 LM83 (U38.12) --
temp_crit# N9 LM83 (U38.16) --
temp_int# T12 LM83 (U38.11) --
External Configuration Management Interface (on J3 Connector)
External_CPLD_IF_0 D13 TBD (pin J3.1] --
External_CPLD_IF_1 D16 TBD (pin J3.3] --
External_CPLD_IF_2 D14 TBD (pin J3.5] --
External_CPLD_IF_3 E15 TBD (pin J3.7] --
External_CPLD_IF_4 E16 TBD (pin J3.4] --
External_CPLD_IF_5 D15 TBD (pin J3.6] --
FPGA Configuration Signals
Signal CPLD Signal Name/Function FPGA
Table 4: FPGA and CPLD pin assignments

Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual
18
The following table shows the memory mapping for the Flash Access Module:
Table 5: Flash Memory Mapping
Name Size Address
FPGA Sector 1 or User Sector
(SW1-4 = 1) 64MB 7FF FFFF
400 0000
Sector 0
(SW1-4 = 0) 64MB 3FF FFFF
000 0000
CvP / PR signals (Configuration via protocol / Partial reconfiguration
Cvp_confdone M13 Cvp_confdone AT29
pr_done L12 pr_done AT30
pr_error N13 pr_error AU29
pr_ready L11 pr_ready AN29
pr_request L13 pr_request AN30
FPGA Configuration Signals
Signal CPLD Signal Name/Function FPGA
Table 4: FPGA and CPLD pin assignments

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XpressGX5LP-SE Reference Manual Ch.3 XpressGX5LP-SE Features
3.3 Dedicated Clocks
The following table describes clock assignments for the board:
Table 6: XpressGX5LP-SE clock assignments
Global Clock inputs
osc_config_FPGA AV29 LVCMOS25 Single-ended 40MHz clock used for the Max V CPLDs.
Osc3 p/n AK23/AL23 LVDS 125 MHz CLK used for PCIe Hard IP
Osc4p/n AE17/AE16 LVDS 100MHz CLK for global CLK network
Osc5 p/n E34/D34 LVDS 200 MHz CLK dedicated to DDR3L Bank1
Osc7 p/n AV7/AW7 LVDS 200 MHz CLK dedicated to DDR3L Bank0
Osc8 p/n J23/J24 LVDS 200 MHz CLK dedicated to QDR2 banks
Gxb Transceiver Clock inputs
Pcie_clk_100MHz p/n AF34/AF35 HCSL 100 MHz Transceiver RefCLK for PCIe Gen2
Signal FPGA Pin Type Comment

Ch.3 XpressGX5LP-SE Features XpressGX5LP-SE Reference Manual
20
3.4 PCI Express Endpoint Connector
The PCI Express male connector enables access to Endpoint PCI Express components as a x1, x4, or x8 PCI
Express 2.0/3.0 Link.
Figure 7: PCI Express connector
The table below describes pin assignments for the PCI Express Endpoint connector. Shaded signals are defined
as optional by the PCI Express Card Electromechanical Specification 2.0, and signals that appear bold are active
signals implemented on the XpressGX5LP-SE.
Side B Side A
PCI Express
Pin FPGA Pin Signal PCI Express Pin FPGA Pin Signal
1 -- +12V 1 connected to
mPRSNT#2 mPRSNT1#
2 -- +12V 2 -- +12V
3 -- +12V 3 -- +12V
4 -- GND 4 -- GND
5 MAX2 - J8 Sm_clk 5 nc JTAG2
6 MAX2 - H8 Sm_dat 6 nc JTAG3
7 -- GND 7 nc JTAG4
8 -- +3.3V 8 nc JTAG5
9 nc JTAG1 9 -- +3.3V
10 Linked to 3.3V
via a jumper 3.3Vaux 10 -- +3.3V
11 nc mWAKE# 11 AC28 mPERST#
-- -- -- -- -- --
12 -- RSVD 12 -- GND
13 -- GND 13 AF34 PCIe_CLKp
14 AV38 mPERp0 14 AF35 PCIe_CLKn
15 AV39 mPERn0 15 -- GND
Table 7: Pin assignments for the PCI Express endpoint connector