PLX Technology CompactPCI 9030RDK-LITE Quick user guide

PCI 9030RDK-LITE
Hardware Reference Manual

PCI 9030RDK-LITE
Hardware Reference Manual
Version 1.3
October 2004
Website: http://www.plxtech.com
Technical Support: http://www.plxtech.com/support/
Phone: [phone]
800 759-3735
Fax: [phone]

© 2004 PLX Technology, Inc. All rights reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice. Products may
have minor variations to this publication, known as errata. PLX assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks of PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PCI 9030/LITE-RDK-HRM-P0-1.3
Printed in the USA, October 2004

PREFACE
NOTICE
This document contains PLX Confidential and Proprietary information. The contents of this document may
not be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this document for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this document is subject to change without notice.
Although every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for
any errors, incidental, or consequential damages in connection with the furnishing, performance, or use of
this manual or examples herein. PLX assumes no responsibility for damage or loss resulting from the use
of this manual, for loss or claims by third parties, which may arise through the use of the RDK, or for any
damage or loss caused by deletion of data as a result of malfunction or repair.
ABOUT THIS MANUAL
This document describes the PLX PCI 9030RDK-LITE, a Reference Design Kit, from a hardware
perspective. It contains a description of all major functional circuit blocks on the board and also is a
reference for the creation of software for this product. This manual also includes complete schematics
and bill of materials.
REVISION HISTORY
Date Version Comments
May 2000 1.0
Hardware Reference Manual release
•Added Section
3.8 PME# Circuit
•Added Section
3.11 Memory Access to the DPRAM
•Updated
Table 3-2. Contents of the Serial EEPROM
•Updated
Table 6-1. Bill of Materials
•Other minor changes
June 2002 1.1
•Updated schematic to remove duplicate pull-up resistor
R66 on TEST signal
•Updated Table 3-2 with new value for offset 7Ah
•Other minor changes
March 2003 1.2 •Minor updates to schematic and BOM.
October 2004 1.3 •EEPROM table, Manual and BOM update
PCI 9030RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved. i

TABLE OF CONTENTS
1. GENERAL INFORMATION................................................................................................1-1
1.1 FEATURES...................................................................................................................................1-2
1.2 RDK INSTALLATION .....................................................................................................................1-2
2. SYSTEM ARCHITECTURE...................................................................................................1
3. HARDWARE ARCHITECTURE.........................................................................................3-1
3.1 HARDWARE MEMORY MAP...........................................................................................................3-2
3.2 PCI 9030....................................................................................................................................3-2
3.3 SERIAL EEPROM ....................................................................................................................... 3-3
3.4 SYNCHRONOUS DUAL-PORT RAM (DPRAM) ............................................................................... 3-6
3.5 TEST HEADERS ...........................................................................................................................3-6
3.6 PLX OPTION MODULE CONNECTOR .............................................................................................3-6
3.7 HARDWARE MODULES .................................................................................................................3-6
3.7.1 RS232 Serial Port...............................................................................................................3-6
3.7.2 Debug and Status LEDs.....................................................................................................3-7
3.7.3 Reset Circuitry ....................................................................................................................3-7
3.7.3.1 Power-on-Reset..............................................................................................................................3-7
3.7.3.2 Reset Pushbutton Switch................................................................................................................3-7
3.7.4 Flash ROM Socket..............................................................................................................3-7
3.8 PME# CIRCUIT............................................................................................................................ 3-7
3.9 PROTOTYPING AREA....................................................................................................................3-7
3.9.1 Thirty-three (33) Surface Mount Footprints ........................................................................ 3-8
3.9.2 The Common BGA Landscape........................................................................................... 3-9
3.10 CONFIGURING THE RDK BOARD .................................................................................................3-10
3.11 MEMORY ACCESS TO THE DPRAM ............................................................................................3-10
4. CUSTOMER SUPPORT.....................................................................................................4-1
5. REFERENCES...................................................................................................................5-2
6. ABEL CODE / BILL OF MATERIALS / SCHEMATICS.....................................................6-1
6.1 ABEL CODE FOR U10..................................................................................................................6-1
PCI 9030RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved. iii

LIST OF FIGURES
Figure 1-1. PCI 9030RDK-LITE Layout Diagram ................................................................................1-1
Figure 2-1. PCI 9030RDK-LITE System Architecture.......................................................................... 2-1
Figure 3-1. PCI 9030RDK-LITE Hardware Block Diagram.................................................................. 3-1
Figure 3-2. BGA Landscapes ..............................................................................................................3-9
LIST OF TABLES
Table 3-1. PCI 9030RDK-LITE Memory Map......................................................................................3-2
Table 3-2. Contents of the Serial EEPROM........................................................................................3-4
Table 3-3. Prototyping Footprints and Prototyping Area on the PCI 9030RDK-LITE Board...............3-8
Table 6-1. Bill of Materials...................................................................................................................6-3
PCI 9030RDK-LITE Hardware Reference Manual v1.3
iv © 2004 PLX Technology, Inc. All rights reserved.

1. General Information
5VCC
3.3V
GND 3.3V
GND
J3
LAH5
Serial
EPROM
J5
U12 U11
PCI 9030
ISA Connector Footprint
16 pin
SOIC 16 pin SOIC
16 pin
SOIC
16 pin
SOIC
20 pin
SSOIC
20 pin
SOIC
20 pin
SOIC
20 pin
SOIC
208/144/80
PQFP
footprints
44 pin
TQFP
20 pin
PLCC
54 pin TSOP
54 pin TSOP
84/68/44/28
PLCC
footprints
25x25 0.1" through hole
prototyping area
176/100/48
PQFP
footprints
48 pin
SSOP 48 pin SSOP
POM Connector
24 pin
SSOP
24 pin
SSOP
LAH1 LAH2
LAH6
U5
LAH4 LAH3
DPRAM
U7 DPRAM U8
U1
DC/DC
Converter
16 pin
SSOP
16 pin
SSOP
OSC
U3
28 pin SOIC
FP1 for flash
memory
28 pin SOIC
OSC
U14
S1
U13
48 pin
SSOP 48 pin SSOP
LEDs
26x26 0.05"
pitch BGA
landscape
Figure 1-1. PCI 9030RDK-LITE Layout Diagram
The PCI 9030RDK-LITE Reference Design Kit (RDK) is a PCI bus target prototyping kit, which can be
used for custom designs such as networking, telecom, imaging, industrial and storage applications
with the PLX PCI 9030 SMARTarget™ I/O Accelerator chip. It allows designers to create designs with
or without a microprocessor.
PCI 9030RDK-LITE Hardware Reference Manual v1.3
© 2004 PLX Technology, Inc. All rights reserved. 1-1

Section 1
General Information RDK Installation
1.1 Features
The PCI 9030RDK-LITE Rapid
Development Kit (RDK) is a PCI Bus Target
Prototyping Kit, which contains a four-layer,
assembled PC board with the dimensions
of 12.28” L x 5.20” W and the following
features:
•PLX PCI 9030 SMARTarget™
I/O Accelerator (176-pin PQFP)
•Socketed serial EEPROM for
configuring PCI 9030
•Supports both multiplexed and non-
multiplexed bus modes
•Thirty-three (33) surface mount
prototyping footprints and a 0.05” pitch
BGA landscape, which can be used
with different FPGAs, CPLDs,
SDRAMs, SRAMs, data transceivers
and general purpose logic devices
•Socketed 32-pin PLCC footprint for
flash boot ROM
•On-board, up to 32-bit wide
synchronous dual-port SRAM and a
small 20-pin programmable GAL, which
demonstrates PCI 9030 continuous
burst read/write features, allowing the
user to plug the board into a PCI
system and be operational immediately
•Four (4) green user-defined
status/debug LEDs and one (1) red
power on LED
•Built-in DB9 connector, RS232
transceiver, and UART for a serial port
to the Local bus
•A push button switch and a reset
generator to provide reset signals to
any device on the board.
•PLL and socketed oscillator for Local
bus clock provide up to 60MHz clock
•5V to 3.3V voltage regulator to enable
card to plug into 5V only PCI slot
•Six logic analyzer headers with
standard HP footprint to allow easy
probing of Local bus signals
•PLX Multiplexed bus mode Option
Module (POM) connector, which
provides connection to other PLX
POMs or devices
•A 25x25, 0.1-inch grid through-hole
area allows easy prototyping with
through-hole components
•ISA bus connector footprint
1.2 RDK Installation
1. Turn off the computer and open the
computer case.
2. Wear user-suitable grounding
straps.
3. Plug the PCI 9030RDK-LITE board
into one of the PCI slots.
4. Close the computer case and turn
on the computer.
PCI 9030RDK-LITE Hardware Reference Manual v1.3
1-2 © 2004 PLX Technology, Inc. All rights reserved.