PLX Technology PEX 8548-AA RDK Quick user guide

l
PEX 8548-AA RDK
Hardware Reference Manual
Version 1.2
July, 2007
Website: www.plxtech.com
Support: www.plxtech.com/support
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PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
ii © 2007 PLX Technology, Inc. All Rights Reserved.
© 2006 – 2007 PLX Technology, Inc. All Rights Reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX
Technology, Inc.
Other brands and names are the property of their respective owners.
Document Number: PEX 8548-AA RDK-HRM-P1-1.2

PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. iii
Contents
Preface ..........................................................................................................................................................v
Notice .........................................................................................................................................................v
About This Manual .....................................................................................................................................v
Revision History .........................................................................................................................................v
1General Information ............................................................................................................................... 1
1.1 PEX 8548 Switch Features.............................................................................................................. 2
1.2 PEX 8548RDK Features.................................................................................................................. 2
2System Architecture ............................................................................................................................... 3
3Hardware Architecture ........................................................................................................................... 4
3.1 PEX 8548 PCI Express Switch........................................................................................................ 4
3.2 PCI Express Upstream Port PCI Express Connection.................................................................... 4
3.3 PCI Express Downstream Port Connections................................................................................... 5
3.3.1 Downstream Port Breakout Add-In Boards............................................................................... 7
3.4 PCI Express Hot Plug Circuitry........................................................................................................ 8
3.5 Reference Clock Circuitry................................................................................................................ 8
3.6 PERST# Circuitry ............................................................................................................................ 8
3.7 Port Status Indicator LEDs .............................................................................................................. 9
3.8 Strapping Switches – SW7, SW5, SW4, SW6, SW8, and SW3.................................................... 10
3.9 Power Circuitry .............................................................................................................................. 11
3.10 Serial EEPROM Interface.............................................................................................................. 12
3.11 JTAG Interface .............................................................................................................................. 12
3.12 I2C Interface ................................................................................................................................... 13
4Mechanical Architecture....................................................................................................................... 14
4.1 Monitoring Point, LED Indicator, and Control Summary................................................................ 15
4.1.1 Monitoring Points .................................................................................................................... 15
4.1.2 LED Indicators......................................................................................................................... 16
4.1.3 Controls................................................................................................................................... 17
4.2 Board Layout Information .............................................................................................................. 18
4.2.1 Trace Routing Design Rules ................................................................................................... 18
4.2.2 Power Decoupling ................................................................................................................... 18
4.2.3 PCB Layer Stackup................................................................................................................. 19
5Frequently Asked Questions................................................................................................................ 20
6Bill of Materials..................................................................................................................................... 21
7Schematics........................................................................................................................................... 27
8References........................................................................................................................................... 37

PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
iv © 2007 PLX Technology, Inc. All Rights Reserved.
Figures
Figure 1. PEX 8548RDK – Component Side View....................................................................................... 1
Figure 2. PEX 8548RDK Functional Block Diagram .................................................................................... 3
Figure 3. PCI Express Board Interconnect ................................................................................................... 5
Figure 4. x8x4x4 and x8x8 Downstream Configurations.............................................................................. 6
Figure 5. Breakout Add-In Boards ................................................................................................................ 7
Figure 6. PCI Express Reset Circuitry.......................................................................................................... 8
Figure 7. PEX 8548RDK Port Status (PORT_GOOD) Indicators ................................................................ 9
Figure 8. Strapping Switches – SW7, SW5, SW4, SW6, SW8, and SW3 ................................................. 10
Figure 9. PEX 8548RDK Power Distribution Circuitry ................................................................................ 11
Figure 10. Power-Up and Power-Down Sequencing.................................................................................. 11
Figure 11. JTAG Header (Top View) .......................................................................................................... 12
Figure 12. I2C Header (Top View)............................................................................................................... 13
Figure 13. I2C Configuration Control........................................................................................................... 13
Figure 14. PEX 8548RDK Mechanical Outline........................................................................................... 14
Figure 15. Decoupling Capacitor Footprints ............................................................................................... 18
Figure 16. PEX 8548RDK 10-Layer PCB Stackup.....................................................................................19
Tables
Table 1. PEX 8548RDK Monitoring Points................................................................................................. 15
Table 2. PEX 8548RDK LED Indicators ..................................................................................................... 16
Table 3. PEX 8548RDK Controls ............................................................................................................... 17

PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. v
Preface
Notice
This manual contains PLX Confidential and Proprietary information. The contents of this manual may not
be copied nor duplicated in any form, in whole or in part, without prior written consent from
PLX Technology, Inc.
PLX provides the information and data included in this manual for your benefit, but it is not possible
to entirely verify and test all the information, in all circumstances, particularly information relating to
non-PLX manufactured products. PLX makes neither warranty nor representation relating to the quality,
content, or adequacy of this information. The information in this manual is subject to change without
notice. Although every effort has been made to ensure the accuracy of this manual, PLX shall not be
liable for any errors, incidental or consequential damages in connection with the furnishing, performance,
or use of this manual or examples herein. PLX assumes no responsibility for damage or loss resulting
from the use of this manual, for loss or claims by third parties, which may arise through the use of the
PEX 8548RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.
About This Manual
This Hardware Reference Manual describes the PLX PEX 8548 Rapid Development Kit (RDK) Board
(PEX 8548RDK), from a hardware perspective. It contains a description of all major functional circuit
blocks on the PEX 8548RDK, and serves as a reference for creating software for this product. This
manual also includes a complete Bill of Materials and Schematics.
Revision History
Date Version Comments
November 13, 2006 1.0 Initial release. Supports Board Revision 100.
May 8, 2007 1.1
Added item cto “Frequently Asked Questions” section.
Changed RDK references/part number to
“PEX 8548-AA RDK”.
Updated Data Book revision listed in Section 8.
Applied miscellaneous enhancements throughout the manual.
July 3, 2007 1.2
Corrected CEM Specification revision reference on page 3.
Removed “AA” from most part number references.
Applied miscellaneous enhancements throughout the manual.
Updated Data Book revision listed in Section 8.
Added I2C Specification information.

PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
vi © 2007 PLX Technology, Inc. All Rights Reserved.
THIS PAGE INTENTIONALLY LEFT BLANK.

1General Information
The PLX PEX 8548RDK is a Rapid Development Kit based on PLX Technology’s ExpressLane™
PEX 8548, a 9-port, 48-lane, 3-station PCI Express switch. The PEX 8548RDK provides a complete
hardware and software development platform to facilitate getting designs up and running quickly, lowering
risk and reducing time-to-market. The PEX 8548RDK routes Station 0 to a x16 male board edge
connector (P1), allowing the PEX 8548RDK to be directly plugged into a motherboard’s x16 PCI Express
connector, or plugged into x8, x4, or x1 PCI Express connectors by using board edge adapters. This
connector is the path by which power, REFCLK, and PERST# are brought onto the PEX 8548RDK.
Station 1 and Station 2 are routed to female x16 PCI Express slot connectors J1 and J2, respectively.
Figure 1 provides a component-side view of the PEX 8548RDK.
PEX 8548
J2
STATION 1 Port Status
STATION 1
HOT PLUG
DS9
Station 2
STATION 2
Station 0DS1
DS6
Station 1
J1
Voltage
Generation
STATION 0
OPEN
SW7
OPEN
SW4
OPEN
SW5
SW3
SW8
SW6
Serial EEPROM
U14
I2C
REF
CLK
P2
CLOSED
OPEN
CLOSED CLOSED CLOSED
OPEN
OPEN
CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED CLOSED
CLOSED
OPEN
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
OPEN
CLOSED
CLOSED
VDD33_EARLY
VDD12_EARLY
VDD10
VTT
VDD33
DS20
DS13
DS4
VDD33_J1
VDD12_J1 VDD33_J2
VDD12_J2
DS2 DS3
DS10 DS11
DS7 DS8
DS5
DS12
SW2
SW1
JP3
I2C
JP1 JP2
P1
DS18
DS19
INTA#
ERROR#
OPEN OPEN OPEN
JTAG
DS14
DS15
DS17
DS16
U1
Figure 1. PEX 8548RDK – Component Side View
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 1

PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
2 © 2007 PLX Technology, Inc. All Rights Reserved.
1.1 PEX 8548 Switch Features
9-port (maximum), 48-lane, 3-station PCI Express switch
Standard 736-ball PBGA-H3 package (37.5 x 37.5 mm)
240 Gbps maximum bandwidth [2.5 Gbps/lane x 48 lanes x 2 (full duplex)]
Non-blocking internal crossbar architecture supports TLP bandwidth capacity of each x16 link
1,024-byte Maximum Packet Size
Performance tuning
Assign x1, x2, or x4, x8, or x16 lanes per port; combination of x8 ports provides x16
Allows any port to be designated as the upstream port (Port 0 is recommended)
Configuration with Strapping balls, serial EEPROM, or I2C
Lane and Polarity reversal
Quality of Service (QoS) with one Virtual Channel (VC) and eight Traffic Classes (TC)
Round-Robin and Weighted Round-Robin Port Arbitration
INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent)
ball support
Compliant to the following specifications:
PCI Local Bus Specification, Revision 3.0
PCI Bus Power Management Interface Specification, Revision 1.2
PCI to PCI Bridge Architecture Specification, Revision 1.2
PCI Express Base Specification, Revision 1.1
PCI Express Card Electromechanical (CEM) Specification, Revision 1.0a
The I2C-Bus Specification, Version 2.1
1.2 PEX 8548RDK Features
PLX PEX 8548 PCI Express switch in a 736-ball PBGA-H3 package
Form factor based on the PCI Express Card Electromechanical (CEM) Specification,
Revisions 1.0a and 1.1
Two downstream PCI Express slot connectors, each configured as x16
Breakout Boards available for further fan-out (x8x8 and x8x4x4 boards available)
DIP switches for hardware configuration of PEX 8548 switch
On-board PCI Express REFCLK Fan-Out buffer
One Hot Plug-controllable slot
Socketable Serial EEPROM (+3.3V devices supported)
I2C interface to read and write registers
On-board Power Sequencer
Manual pushbutton PERST# capability
Port Status indicator LEDs for visual inspection of link status
Auxiliary hard disk drive header, for supporting additional power requirements for add-in boards

2System Architecture
The PEX 8548RDK is a PLX Rapid Development Kit intended primarily for use in silicon evaluation and
design reference. The form factor is based on the PCI Express Card Electromechanical (CEM)
Specification, Revisions 1.0a and 1.1. The PEX 8548RDK is designed to work by plugging into a
PCI Express-compliant motherboard. Figure 2 illustrates the PEX 8548RDK functional block diagram.
The 16 lanes of Station 0 (which consists of Ports 0, 1, and 2) are routed to a male x16 PCI Express
board edge connector (P1). This connector delivers +3.3 VDC and +12 VDC, the Reference Clock, and
PERST# to the PEX 8548RDK.
The 16 lanes of Station 1 (which consists of Ports 8, 9, and 10) are routed to a female x16 PCI Express
straddle-mount slot connector (J1). The PEX 8548RDK provides +3.3 VDC and +12 VDC, the Reference
Clock, and PERST# to this connector. On-board circuitry allows Port 8 to operate as a Hot Plug port;
however, this means that Port 8 cannot be configured as the upstream port.
The 16 lanes of Station 2 (which consists of Ports 12, 13, and 14) are routed to a female x16 PCI Express
through-hole slot connector (J2). The PEX 8548RDK provides the Reference Clock and PERST#, and a
hard disk drive header (P2) provides +3.3 VDC and +12 VDC, to this connector.
OPEN OPEN OPEN OPEN OPEN OPEN
Figure 2. PEX 8548RDK Functional Block Diagram
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 3

PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
4 © 2007 PLX Technology, Inc. All Rights Reserved.
3Hardware Architecture
There are several subsystems on the PEX 8548RDK. Among them are a power system that powers the
PEX 8548 switch, circuitry for supporting Hot Plug on Station 1 (Port 8), a Reference Clock Fan-Out
buffer circuit, and LED indicators and controls. The following sections describe each PEX 8548RDK
subsystem.
3.1 PEX 8548 PCI Express Switch
The PEX 8548 is a 9-port, 48-lane, 3-station (up to three ports per station, maximum of nine PCI Express
ports), non-blocking PCI Express switch. The switch operates in Transparent mode. Each lane consists of
Transmit and Receive signal pairs, which transfer data at a rate of 2.5 Gbps in both directions. The
maximum achievable bandwidth is 240 Gbps [2.5 Gbps * 48 lanes * 2 (full duplex)]. The port configuration
is flexible and can be changed using a serial EEPROM, the I2C interface, or Strapping balls. The
PEX 8548RDK is designed to allow Station 0 to be routed to a x16 male PCI Express board edge
connector, and each of the other two stations (Stations 1 and 2) to be routed to a x16 female PCI Express
slot connector. Breakout add-in boards can be plugged into the Station 1 and/or Station 2 connectors, to
break these stations out to x8x8 or x8x4x4 port configurations.
3.2 PCI Express Upstream Port PCI Express Connection
The upstream port (within Station 0) is a x16 link that connects the PEX 8548 switch to the male x16
PCI Express board edge connector (P1). The PEX 8548RDK can plug into narrower PCI Express slots
(x8, x4, or x1) by using a small adapter board, such as those offered by Catalyst. In these situations, the
PEX 8548 switch negotiates down to the narrower link width.

3.3 PCI Express Downstream Port Connections
The PEX 8548RDK, in conjunction with breakout add-in boards, provides connectivity to support up to six
downstream ports – three from Station 1 and three from Station 2. For each station, PCB traces provide a
x16 link to one PCI Express slot connector, for a hardwired default configuration of x16 for Station 1 and
x16 for Station 2. (Refer to Figure 3.) If the link width connected between the PEX 8548 switch and an
add-in board’s PCI Express device is not x16, the link auto-negotiates to a common link width.
Figure 3. PCI Express Board Interconnect
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 5

Hardwire connections that support x8x4x4 and x8x8 downstream configurations can be provided by
breakout add-in boards, as illustrated in Figure 4.
Endpoint Endpoint
Endpoint
Endpoint
Endpoint
PEX 8548
PEX 8548 RDK
Breakout Board
Breakout Board
Figure 4. x8x4x4 and x8x8 Downstream Configurations
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
6 © 2007 PLX Technology, Inc. All Rights Reserved.

3.3.1 Downstream Port Breakout Add-In Boards
Breakout add-in boards allow breaking out of the x16 station link into smaller port configurations. There
are two breakout board configurations – x16 to x8x8 and x16 to x8x4x4. An on-board Clock Fan-Out
buffer circuit provides REFCLK to the slot connectors, from the REFCLK signal provided through the male
PCI Express board’s edge connector. (Refer to Figure 5.)
Figure 5. Breakout Add-In Boards
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 7

3.4 PCI Express Hot Plug Circuitry
Three of the PEX 8548 switch’s ports (Ports 1, 8, and 9) have a PCI Express Hot Plug Controller. The
PEX 8548RDK uses only Port 8’s Hot Plug Controller, in conjunction with an Intersil ISL6161 Hot Plug
Controller, to provide Hot Plug capability to the Station 1 PCI Express slot. The Port 1 and Port 9 Hot Plug
Controllers are not used.
Note: Because Port 8 is hardware-configured to support Hot Plug, Port 8 cannot be used as the
upstream port.
3.5 Reference Clock Circuitry
The PEX 8548RDK uses the 100-MHz differential Reference Clock (REFCLK), provided at the male
add-in board’s edge connector. This clock drives a 1:3 Clock Fan-Out buffer circuit, to drive the two
downstream connectors, as well as the PEX 8548 switch. REFCLK to the Station 1 Hot Plug connector is
enabled by the PEX 8548 switch’s Port 8 Hot Plug Controller. (The Reference Clock data path is included
in Figure 2.)
3.6 PERST# Circuitry
The PEX 8548RDK generates PERST# to the PEX 8548 switch and Station 2 port connector, by
wire-ORing PERST# from the male board edge connector with a reset controller chip (U11) driven by
+3.3 VDC to the PEX 8548 switch and a manual Reset driven by the MAN_PERST# pushbutton (SW2).
(Refer to Figure 6.) PERST# to the Station 1 Hot Plug connector is driven by the PEX 8548 switch’s
Port 8 Hot Plug Controller.
Figure 6. PCI Express Reset Circuitry
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
8 © 2007 PLX Technology, Inc. All Rights Reserved.

3.7 Port Status Indicator LEDs
The PEX 8548 switch incorporates a nine-signal interface dedicated to providing port status for each of
the nine possible ports. Two port status states are indicated:
Port is up and operating – PEX_PORT_GOOD# Status signal is asserted, PORT_GOOD status
LED is turned On
Port is not used – PEX_PORT_GOOD# Status signal is de-asserted, PORT_GOOD status LED
is turned Off
The PEX 8548RDK uses these signals to drive nine discrete green PORT_GOOD status LEDs (located
on the upper-right corner of the PEX 8548RDK; refer to Figure 1 and Figure 7). When an LED is driven,
that port is active. (Refer to Section 4.1.2, “LED Indicators,” for further details.)
Figure 7. PEX 8548RDK Port Status (PORT_GOOD) Indicators
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 9

3.8 Strapping Switches – SW7, SW5, SW4, SW6, SW8, and SW3
The PEX 8548 switch has several Strapping balls that provide the capability to perform various types of
hardware initialization, without the use of software. Most Strapping balls are brought out to DIP switches
(SW7, SW5, SW4, SW6, SW8, and SW3). Other Strapping balls that are not used in typical situations are
strapped, using pull-up or pull-down resistors. Figure 8 illustrates the default switch settings. (Refer to
Section 4.1.3, “Controls,” for further details.)
Figure 8. Strapping Switches – SW7, SW5, SW4, SW6, SW8, and SW3
Note: The grayed-out switch location in SW8 and SW3 is not used.
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
10 © 2007 PLX Technology, Inc. All Rights Reserved.

3.9 Power Circuitry
The PEX 8548RDK is used as an add-in board. All power to the on-board components is provided directly
from the male board edge connector +12 VDC and +3.3 VDC power pins. The +12 VDC power is
converted to +1.0 VDC, for use by the PEX 8548 switch. Most on-board devices, such as Clock buffers,
serial EEPROM, Port 8 Hot Plug circuitry, and numerous I/O buffers on the PEX 8548 switch, use the
+3.3 VDC power rail. All power rails reference a common ground. Figure 9 illustrates the PEX 8548RDK
power distribution circuitry.
Voltages to the PEX 8548 switch are sequenced such that VDD_1.0V powers up before VDD_3.3V and
VDD_VTT, and powers down after VDD_3.3V and VDD_VTT. (Refer to Figure 10.)
Power field-effect transistors (FETs) are used to gate board power to the Station 1 Hot Plug connector.
The Station 2 slot connector receives +12 VDC and +3.3 VDC from a straight, hard disk drive header that
can support up to 10A per pin.
Power decoupling uses a three-per-decade decoupling scheme, starting at 12.5 MHz, to avoid resonance
peaks in the power distribution system.
PEX 8548 (U1)
+1.0V Core
+1.0V SerDes
+3.3V LVTTL I/O
+1.5 – +1.8V VTT
VDDHD_5V
Other On-Board
Circuits
+12V to +1.0V @10A
DC/DC Converter
+5V to +3.3V
@8A DC/DC
Converter
Hot Plug
Circuit
VDDHP_3.3V
VDDHP_12V
Fan
VDD_12V
VDD_3.3V
VDD_VTT
VDD_3.3V
VDD_1.0V
Voltage Sense
VDDEARLY_1.0V
Hard Disk Drive
Header
PCI Express Board Edge Connector
+3.3V to +1.5 – +1.8V
Regulator
Figure 9. PEX 8548RDK Power Distribution Circuitry
VDD_1.0V
VDD_3.3V
VDD_VTT
Figure 10. Power-Up and Power-Down Sequencing
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 11

3.10 Serial EEPROM Interface
The PEX 8548RDK provides a socketable serial EEPROM (Atmel AT25128A-10PI-2.7) (U14). The serial
EEPROM contents are used to initialize the PEX 8548 switch after power-on reset.
3.11 JTAG Interface
The PEX 8548RDK includes a dedicated 2x5 JTAG header (JP3) to the PEX 8548 switch. (Refer to
Figure 11.) Additionally, the PEX 8548 switch’s JTAG interface can be connected to the PCI Express
board edge connector JTAG pins, through 0-Ohm resistors.
There is no “standard” JTAG header pin arrangement; therefore, JTAG header type and pin assignments
are arbitrary. The header and pin assignment chosen for the PEX 8548RDK is compatible with the Corelis
JTAG single TAP cable (AS00790050-A0).
Pin 1 - TRST#
Pin 3 - TDI
Pin 5 - TDO
Pin 7 - TMS
Pin 9 - TCK
Figure 11. JTAG Header (Top View)
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
12 © 2007 PLX Technology, Inc. All Rights Reserved.

3.12 I2C Interface
The PEX 8548 switch provides a two-wire, I2C-compatible Slave mode interface with 3-bit addressing.
Through this out-of-band channel, users can read, write, and configure the PEX 8548 switch’s internal
registers, and monitor Error Counters and port status. The PEX 8548RDK provides two headers that
enable chaining together of multiple boards – a 2x5-pin header (JP1) and a 2x2-pin header (JP2).
There is no “standard” I2C header pin arrangement; therefore, I2C header type and pin assignments
are arbitrary. The header and pin assignment chosen for the 2x5 pin header is compatible with the
Aardvark I2C/SPI cable. (Refer to Figure 12.) I2C address selection is determined by the SW4
switch settings.
The I2C headers (JP1 and JP2) can be connected to five different objects:
PEX 8548 switch’s I2C interface
SMBus interface on the three PCI Express connectors (P1, J1, and J2)
Pull-up resistor network
The connection to the I2C headers is through analog switches that are controlled by DIP switch SW3. Five
LEDs (DS13 through DS17) indicate (turn On) when an associated object is connected to the I2C headers.
(Refer to Figure 13.)
Figure 12. I2C Header (Top View)
Figure 13. I2C Configuration Control
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. 13

4Mechanical Architecture
Figure 14 illustrates the PEX 8548RDK board and component placement.
Figure 14. PEX 8548RDK Mechanical Outline
PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
14 © 2007 PLX Technology, Inc. All Rights Reserved.