PEX 8548-AA RDK Hardware Reference Manual, Version 1.2
© 2007 PLX Technology, Inc. All Rights Reserved. iii
Contents
Preface ..........................................................................................................................................................v
Notice .........................................................................................................................................................v
About This Manual .....................................................................................................................................v
Revision History .........................................................................................................................................v
1General Information ............................................................................................................................... 1
1.1 PEX 8548 Switch Features.............................................................................................................. 2
1.2 PEX 8548RDK Features.................................................................................................................. 2
2System Architecture ............................................................................................................................... 3
3Hardware Architecture ........................................................................................................................... 4
3.1 PEX 8548 PCI Express Switch........................................................................................................ 4
3.2 PCI Express Upstream Port PCI Express Connection.................................................................... 4
3.3 PCI Express Downstream Port Connections................................................................................... 5
3.3.1 Downstream Port Breakout Add-In Boards............................................................................... 7
3.4 PCI Express Hot Plug Circuitry........................................................................................................ 8
3.5 Reference Clock Circuitry................................................................................................................ 8
3.6 PERST# Circuitry ............................................................................................................................ 8
3.7 Port Status Indicator LEDs .............................................................................................................. 9
3.8 Strapping Switches – SW7, SW5, SW4, SW6, SW8, and SW3.................................................... 10
3.9 Power Circuitry .............................................................................................................................. 11
3.10 Serial EEPROM Interface.............................................................................................................. 12
3.11 JTAG Interface .............................................................................................................................. 12
3.12 I2C Interface ................................................................................................................................... 13
4Mechanical Architecture....................................................................................................................... 14
4.1 Monitoring Point, LED Indicator, and Control Summary................................................................ 15
4.1.1 Monitoring Points .................................................................................................................... 15
4.1.2 LED Indicators......................................................................................................................... 16
4.1.3 Controls................................................................................................................................... 17
4.2 Board Layout Information .............................................................................................................. 18
4.2.1 Trace Routing Design Rules ................................................................................................... 18
4.2.2 Power Decoupling ................................................................................................................... 18
4.2.3 PCB Layer Stackup................................................................................................................. 19
5Frequently Asked Questions................................................................................................................ 20
6Bill of Materials..................................................................................................................................... 21
7Schematics........................................................................................................................................... 27
8References........................................................................................................................................... 37
