PEX 8604 Quick Start Hardware Design Guide – Version 1.3
Copyright © 2009 by PLX Technology, Inc. All rights reserved 4
Table 1. Receiver Equalization Settings
SerDes NReceiver Equalizer[3:0] Equalization
0000b Off
0010b Low
0110b Medium
1110b High
1.3 Reference Clock
The Reference Clock is a key component to a Link that was often overlooked by system designers in first
generation PCI Express systems. The Reference Clock provides a 100 MHz base frequency for the PLL. The PLL
provides a frequency synthesis function, generating the higher speed clocks required to transmit data at a rate of
either 2.5 GT/s or 5.0 GT/s. In designs that implement digital CDRs, the PLL output also provides the Reference
Clocks to the CDR circuit; hence, jitter on the Reference Clock can affect both the Transmitter and Receiver
components.
The PLL has a low-pass, jitter-filter transfer function from its reference input to the high speed output clocks;
therefore, it is important to minimize the low-frequency jitter in the pass band of the PLL. Low-frequency jitter
below the PLL loop bandwidth passes directly to output clocks, which, in turn, drives the Transmitter and CDR
circuits. Jitter at the loop bandwidth is especially critical, given most PLLs have some amount of gain at the cut-off
frequency. High-frequency jitter on the Reference Clock input above the loop bandwidth is typically attenuated,
and is therefore of less concern.
The jitter transfer function of a CDR circuit is modeled as a high-pass filter. Low-frequency jitter, including Spread-
Spectrum Clock (SSC) modulation, is tracked by the CDR circuit, whereas higher-frequency jitter content causes
eye closure at the Receiver. The cut-off frequency of the CDR high-pass function is usually less than the cut-off
frequency of the Transmitter PLL low-pass function. The pass band between these cut-off frequencies is where
Reference Clock jitter causes the most problems.
In PCI Express, the cut-off frequency of the PLL is specified to be between 1.5 to 22 MHz for 2.5 GT/s and 8 to
16 MHz for 5.0 GT/s data rates. The purpose of these bandwidth ranges is to limit the difference in PLL bandwidth
on the two sides of a Link. This is especially important for common clock systems, where the amount of jitter
appearing at the CDR is defined by the difference function between the Tx and Rx PLLs.
Another mechanism that can increase jitter seen by a Receiver in common clocked systems is the fixed phase
difference (transport delay delta) between Transmitter data at the CDR input and a Receiver’s recovered clock,
relative to the 100 MHz Reference Clock source. This delay should not exceed 12ns per PCI Express
specification. The delay budget includes on-chip and off-chip delays. In general terms, all Reference Clock nets in
a system should be matched within 38.1 cm (15 in.). Figure 3 illustrates Reference Clock transport delay delta.
The PEX 8604 PEX_REFCLKn/p signal is the Reference Clock Input buffer. It has an internal DC-biasing circuit,
and hence, should be AC-coupled from the RefClk source driver. Use 0.01 to 0.1 µF capacitors (0603 or 0402-
size) to AC-couple the Reference Clock input, as illustrated in Figure 4.
