PLX Technology PEX 8114RDK-R Quick user guide

PEX 8114RDK-R
Hardware Reference Manual
For Board Revision 100
Version 3.2
February 2008
Website: www.plxtech.com
Technical Support: www.plxtech.com/support
Copyright © 2008 by PLX Technology, Inc. All Rights Reserved – Version 3.2
February 19, 2008

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
ii © 2008 PLX Technology, Inc. All Rights Reserved.
© 2008 PLX Technology, Inc. All Rights Reserved.
PLX Technology, Inc. retains the right to make changes to this product at any time, without notice.
Products may have minor variations to this publication, known as errata. PLX assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of
PLX Technology, Inc.
Other brands and names are the property of their respective owners.
Order Number: PEX 8114-RDK/R-HRM-P1-3.2

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. iii
Contents
1General Information................................................................................................... 1
1.1 PEX 8114 Features.............................................................................................. 2
1.2 PEX 8114RDK-R Features................................................................................... 2
2System Architecture .................................................................................................. 3
3Hardware Architecture............................................................................................... 5
3.1 PEX 8114 Bridge Device...................................................................................... 5
3.2 JTAG Interface..................................................................................................... 5
3.3 Serial EEPROM Interface..................................................................................... 5
3.3.1 Serial EEPROM Contents............................................................................... 5
3.4 Strapping Switches .............................................................................................. 6
3.4.1 Switch SW3 – PCIXCAP Control .................................................................... 6
3.4.2 Switch SW5 – Strapping and RefClk Pin Control............................................ 6
3.5 PCI Express Interface.......................................................................................... 7
3.5.1 RefClk............................................................................................................. 7
3.5.2 PERST#.......................................................................................................... 7
3.5.3 Lane Status LED Indicators............................................................................ 7
3.5.4 Hot Plug.......................................................................................................... 7
3.6 PCI-X Interface..................................................................................................... 8
3.6.1 PCI RST#........................................................................................................ 8
3.7 Power................................................................................................................... 8
3.7.1 Board Power................................................................................................... 8
3.7.2 PEX 8114 Bridge Device Power ..................................................................... 8
3.7.2.1 PEX 8114 Voltage Generation................................................................ 8
3.7.2.2 PEX 8114 Voltage Sequencing............................................................... 9
3.7.3 PCI Express Power......................................................................................... 9
4Mechanical Architecture .......................................................................................... 10
4.1 Monitoring Point, LED Indicator, and Control Summary..................................... 10
4.1.1 Monitoring Points.......................................................................................... 10
4.1.2 LED Indicators.............................................................................................. 11
4.1.3 Controls ........................................................................................................ 11
4.2 Layout Information ............................................................................................. 12
4.2.1 Trace Routing Design Rules......................................................................... 12
4.2.2 Power Decoupling......................................................................................... 12
4.2.3 PCB Layer Stackup ...................................................................................... 13
5References.............................................................................................................. 14
6Bill of Materials and Schematics.............................................................................. 15

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
iv © 2008 PLX Technology, Inc. All Rights Reserved.
Figures
Figure 1. PEX 8114RDK-R – Component Side View.......................................................1
Figure 2. PEX 8114RDK-R Functional Block Diagram ....................................................4
Figure 3. JTAG (JP1) Header (Viewed from Top)............................................................5
Figure 4. SW3 PCIXCAP Switches..................................................................................6
Figure 5. SW5 Strapping and RefClk Generator Switches ..............................................6
Figure 6. Decoupling Capacitor Footprints ....................................................................12
Figure 7. PEX 8114RDK-R 12-Layer PCB Stackup.......................................................13
Tables
Table 1. PEX 8114RDK-R Monitoring Points.................................................................10
Table 2. PEX 8114RDK-R LED Indicators.....................................................................11
Table 3. PEX 8114RDK-R Controls...............................................................................11

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. v
Preface
Notice
This manual contains PLX Confidential and Proprietary information. The contents of this manual may not
be copied nor duplicated in any form, in whole or in part, without prior written consent from PLX
Technology, Inc.
PLX provides the information and data included in this manual for your benefit, but it is not possible to
entirely verify and test all the information, in all circumstances, particularly information relating to non-PLX
manufactured products. PLX makes neither warranty nor representation relating to the quality, content, or
adequacy of this information. The information in this manual is subject to change without notice. Although
every effort has been made to ensure the accuracy of this manual, PLX shall not be liable for any errors,
incidental or consequential damages in connection with the furnishing, performance, or use of this manual
or examples herein. PLX assumes no responsibility for damage or loss resulting from the use of this
manual, for loss or claims by third parties, which may arise through the use of the PEX 8114RDK-R, or for
any damage or loss caused by deletion of data as a result of malfunction or repair.
About This Manual
This manual describes the PLX PEX 8114RDK-R, the PEX 8114 Reverse Bridge RDK Board Rapid
Development Kit, from a hardware perspective. It contains a description of all major functional circuit
blocks on the PEX 8114RDK-R and also is a reference for the creation of software for this product. This
manual also includes a complete Bill of Materials and Schematics.

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
vi © 2008 PLX Technology, Inc. All Rights Reserved.
Revision History
Date Version Comments
April 2005 1.0 Initial release. Supports Board Revision 001.
April 2005 1.1 Update to support Board Revision 100.
July 2005 1.2
•Added missing greater than/less than symbols for Section 3.3 bullets.
•Rewrote Section 3.4.2.
•Section 3.5.1, changed capacitor reference to “AC coupling” and clock
synthesizer frequency information.
•Section 3.5.4, changed referenced pin to 5.
•Deleted Section 3.6.1 (PCI CLK) and Section 3.4.3 (RefClk Control).
•Removed SW4 and revised most content related to SW5.
•Updated Figure 1, Figure 4, and Figure 5.
•Removed Figure 7 and renumbered subsequent figures.
April 2006 2.0
•Updated to reflect use of PEX 8114BA device.
•Updated Figure 1, Figure 4, and Figure 5.
•Section 3.3, changed “SW4, pin 2” reference to “SW5, pin 1.”
•Section 3.5.1, corrected SW5 pin references (2 places).
•Section 3.7.1, changed VTT value to +1.3 to +1.8 VDC.
•Updated Bill of Materials and Schematics.
November 2006 3.0
•Updated to reflect use of PEX 8114BB device.
•Miscellaneous changes and enhancements throughout manual.
•Updated Bill of Materials and Schematics.
•Removed references to Non-Transparent mode.
March 2007 3.1 •Updated to reflect use of PEX 8114BC device.
•Updated Bill of Materials and Schematics.
February 2008 3.2 •Updated to reflect use of PEX 8114BD device.
•Updated Bill of Materials and Schematics.

1 General Information
The PLX PEX 8114RDK-R is a Rapid Development Kit based on the PLX ExpressLane™ PEX 8114 PCI
Express-to-PCI/PCI-X Bridge device implementing Reverse Bridge mode. The PEX 8114RDK-R is a
complete hardware and software development platform to facilitate getting designs up and running quickly,
lowering risk and time-to-market. The PEX 8114RDK-R allows the PEX 8114 bridge device PCI or PCI-X
interface to be connected to a Host system slot, by way of a standard PCI/PCI-X board edge connector
(the PEX 8114RDK-R is designed to plug into a PCI or PCI-X motherboard slot). In Reverse Bridge mode,
the secondary side of the PEX 8114 bridge device is the PCI Express downstream port.
The PEX 8114RDK-R also allows for a single PCI Express adapter to be plugged into the downstream
port, by way of a standard PCI Express Card Electromechanical (CEM) slot located on the
PEX 8114RDK-R.
Figure 1. PEX 8114RDK-R – Component Side View
PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. 1

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
2 © 2008 PLX Technology, Inc. All Rights Reserved.
1.1 PEX 8114 Features
Supports Reverse and Forward Bridging
Note: The PEX 8114RDK-R is for Reverse Bridge mode designs. For Forward Bridge mode
designs, refer to the PEX 8114RDK-F.
Single PCI Express port capable of x4, x2, or x1 link width
Single PCI-X Bus segment supporting PCI-X protocol at 64-bit/133 MHz and/or PCI Local Bus
Specification, Revision 3.0
Standard 256-ball PBGA package (17 x 17 mm)
Advanced PCI Express features supported include Advanced Flow Control, Advanced Error
Reporting, Integrated Hot Plug, ECRC and Poison Bit, Automatic Polarity, and Lane Reversal
Fully integrated PCI Express PHY with 8b/10b encoding, hardware link training, and low-power
programmable SerDes
Compliant to the following specifications:
PCI Local Bus Specification, Revision 3.0
PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
PCI Express Base Specification, Revision 1.0a
1.2 PEX 8114RDK-R Features
PLX PCI Express-to-PCI/PCI-X bridge device
Form factor based on PCI-X Electrical and Mechanical Addendum to the PCI Local Bus
Specification, Revision 2.0a
Single 64-bit PCI/PCI-X board edge connector for insertion into standard 64-bit PCI or PCI-X
motherboard slot
Single PCI Express slot on secondary side – slot is PCI Express Card Electromechanical (CEM)
Specification, Revision 1.1-compliant and accommodates PCI Express adapters with slot
connector widths up to x16
Note: Reverse Bridge mode supports a maximum downstream PCI Express link width of x4;
however, all PCI Express functions plugged into the downstream slot automatically link train to
the largest common link width supported by both devices. The following PCI Express adapter link
widths can be accommodated with this RDK – x1, x2, x4, x8, and x16.
Socketable serial EEPROM for easy configuration
Lane Status Indicator LEDs for easy visual inspection of PCI Express link and lane status
Auxiliary ATX four-pin hard-drive connector for additional power requirements
DIP switches for PEX 8114 hardware configuration
On-board PCI Express RefClk generator
On-board probing points
On-board manual Reset switches

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. 3
2 System Architecture
The PEX 8114RDK-R assists customers in evaluating PLX Technology’s PEX 8114 PCI Express-to-
PCI/PCI-X Bridge device, and facilitates early development of customer designs with the PEX 8114. The
usage configuration is reverse bridging between a PCI/PCI-X baseboard and a PCI Express add-in board.
The PEX 8114RDK-R is designed to showcase all features of the PEX 8114 when operating in Reverse
Bridge mode.
The PEX 8114RDK-R’s form factor is based on the PCI-X Electrical and Mechanical Addendum to the
PCI Local Bus Specification, Revision 2.0a. The PEX 8114RDK-R is able to plug into a standard +3.3V
PCI or PCI-X slot of a Host system and supports PCI/PCI-X traffic of up to 64-bit transfers, at up to
133 MHz. (Refer to Figure 2.) The PCI Express interface is provided by an x16 PCI Express straddle-
mount slot connector, into which a PCI Express board can be inserted. Only the first four lanes of the slot
are routed to the PEX 8114, and each lane is capable of up to 2.5 Gbps. The PEX 8114RDK-R appears
to the Host as a PCI-to-PCI bridge. A PCI Express board plugged into the PEX 8114RDK-R appears to
the Host to be sitting on a PCI Bus behind a PCI-to-PCI bridge. The Host system can treat the PCI
Express board as a standard PCI board. The PEX 8114RDK-R supports PCI Express Hot Plug.
PEX 8114RDK-R power, as well as +3.3 VDC to the PCI Express slot connector, is provided through the
PCI/PCI-X board edge connector. Power to the PCI Express straddle-mount slot connector for +12 VDC,
up to 2.3A draw, can be from an on-board +5 VDC to +12 VDC converter that draws from +5 VDC
provided by the PCI/PCI-X board edge connector. For heavier loads, +12 VDC can be provided from an
ATX supply, by way of a standard four-pin hard-drive header.
Note: This voltage converter is not operable on current versions of the PEX 8114RDK-R. PCI Express
+12 VDC must be obtained from the 4-pin hard-drive header.
The PEX 8114RDK-R has a Hot Plug interface device on the PCI Express port to support PCI Express
Hot Plug.

Figure 2. PEX 8114RDK-R Functional Block Diagram
PEX 8114RDK-R Hardware Reference Manual, Version 3.2
4 © 2008 PLX Technology, Inc. All Rights Reserved.

3 Hardware Architecture
There are several subsystems on the PEX 8114RDK-R. Among them are a power system that powers the
PEX 8114, a Hot Plug circuit for the PCI Express straddle-mount slot connector, a Reference Clock
generator, and controls and indicators. The following sections describe each PEX 8114RDK-R subsystem.
3.1 PEX 8114 Bridge Device
The PEX 8114 is housed in a 17 x 17 mm 256-ball PBGA package. Ball pitch is 1.0 mm. No additional
cooling is required.
3.2 JTAG Interface
The PEX 8114 has a JTAG interface, which is connected to a 2 x 5 header. (Refer to Figure 3.)
There is no “standard” JTAG header pin arrangement; therefore, JTAG header type and pin assignments
are somewhat arbitrary. The header and pin assignment chosen for the PEX 8114RDK-R is compatible
with the Corelis JTAG single TAP cable (AS00790050-A0).
Pin 1 - TRST#
Pin 3 - TDI
Pin 5 - TDO
Pin 7 - TMS
Pin 9 - TCK
Figure 3. JTAG (JP1) Header (Viewed from Top)
3.3 Serial EEPROM Interface
The PEX 8114 has an SPI EEPROM interface, which can be used to load Configuration data from a serial
EEPROM at power-up. This interface is connected to an 8-pin DIP socket (U1), which houses the serial
EEPROM. Switch SW5 – pin 1 – indicates to the PEX 8114 that the serial EEPROM is present when this
switch is closed. (Refer to Figure 5.)
1 KB of serial EEPROM storage is sufficient.
If the application requires Expansion ROM space, up to a 64-KB serial EEPROM can be used. The serial
EEPROM must complete loading within 10 ms, and must be capable of being clocked at 7.8 MHz (the
clock frequency output by the PEX 8114). Serial EEPROM I/O signaling levels must meet the following
values, to be compatible with the PEX 8114 TTL I/O levels:
V
IL < 0.4V
V
IH > 2.4V
V
OL < 0.8V
V
OH > 2.0V
The Atmel AT25xxxA family of serial EEPROMs is one possible family of serial EEPROMs that can be
used. The PEX 8114RDK-R includes a pre-programmed AT25640A serial EEPROM.
3.3.1 Serial EEPROM Contents
Refer to the PEX 8114BC/BD Data Book, Appendix A, “Serial EEPROM Map.”
PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. 5

3.4 Strapping Switches
The PEX 8114RDK-R has two DIP switches – SW3 and SW5 – that are used to control various
PEX 8114RDK-R configurations.
3.4.1 Switch SW3 – PCIXCAP Control
Switch SW3 has two switches, which determine the PCI/PCI-X board edge connector PCIXCAP pin value.
This signal is also passed to the PEX 8114, to communicate expected PCI/PCI-X Bus speed. Figure 4
illustrates the switch, a table listing the PCIXCAP switch combinations, and the circuit used.
Figure 4. SW3 PCIXCAP Switches
3.4.2 Switch SW5 – Strapping and RefClk Pin Control
Switch SW5 has eight switches, which determine some Strapping ball values to the PEX 8114, some
PCI/PCI-X Bus speed control signals, and some RefClk generator control signals. Figure 5 illustrates the
SW5 switch assignments, in their default positions.
1 2 3 4 5 6 7 8
OPEN
Figure 5. SW5 Strapping and RefClk Generator Switches
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6 © 2008 PLX Technology, Inc. All Rights Reserved.

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. 7
3.5 PCI Express Interface
The PCI Express interface is provided by an x16 female straddle-mount slot connector (J5). Only the first
four lanes are routed to the PEX 8114. The PCI Express straddle-mount slot connector provides +12 VDC
and +3.3 VDC, RefClk, and PERST# to PCI Express add-in boards. The PCI Express lanes are laid out
as 100-Ohm, controlled-impedance, stripline-differential pairs. Within pair, trace-length mismatch is not
greater than 0.127 mm (0.005 inches). Pair-to-pair, trace-length mismatch is less than 6.35 mm
(0.25 inches).
3.5.1 RefClk
PCI Express RefClk is generated on-board by a clock synthesizer, using a 25-MHz crystal for the seed
frequency. The PEX 8114RDK-R uses the ICS9FG108G part from Integrated Device Technology, though
any comparable synthesizer is sufficient. RefClk is fanned out to the PEX 8114 and the PCI Express
straddle-mount slot connector. RefClk must, and does, pass through AC-coupling capacitors before
entering the PEX 8114. Valid values for the AC-coupling capacitors are the same as for the PCI Express
Base Specification, Revision 1.0a recommendation (75 to 200 nF, with package sizes of 0603 or 0402).
The PEX 8114RDK-R uses 0.1 µF values, in 0402 packages.
RefClk to the PEX 8114 can be manually disabled by SW5, pin 6. RefClk to the PCI Express
straddle-mount slot connector is enabled by the PEX 8114 HP_CLKEN# signal. The clock synthesizer
frequency is determined by pull-up/pull-down resistors. Output enabling and Spread-Spectrum enabling
are controlled by SW5, pins 8 and 7, respectively. (Refer to Section 3.4.2, “Switch SW5 – Strapping and
RefClk Pin Control.”) RefClk routing is laid out as a 100-Ohm, controlled-impedance, stripline-differential
pair. Trace-length mismatch within this pair is less than 0.127 mm (0.005 inches).
3.5.2 PERST#
PERST# to the PCI Express straddle-mount slot connector (J5) is directly controlled by the PEX 8114 Hot
Plug interface. PERST# to the PEX 8114 is controlled by the PEX 8114RDK-R Power Good indicator
(DS10).
3.5.3 Lane Status LED Indicators
Four green surface-mount LEDs (DS6, DS7, DS8, and DS9) are attached to the four PEX 8114
PEX_LANE_GOOD[3:0]# balls, respectively, to indicate lane status. A lane is active when its LED is
turned On.
3.5.4 Hot Plug
The PEX 8114 supports PCI Express Hot Plug. The PEX 8114RDK-R circuitry provides a pushbutton
(SW1) for initiating a Hot Plug event, LED indicators for Attention (DS2) and Power (DS1), a switch to
mimic a Manually operated Retention Latch, (HP_MRL#, SW5 – pin 5), and a power isolation circuit (U3)
for the x16 PCI Express straddle-mount slot connector. The PEX 8114 Hot Plug Controller controls the
PCI Express slot connector On/Off, which includes control of connector power, RefClk, and PERST#
enable/disable sequencing.

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
8 © 2008 PLX Technology, Inc. All Rights Reserved.
3.6 PCI-X Interface
The PCI/PCI-X interface is a male board edge connector that complies with the PCI-X Electrical and
Mechanical Addendum to the PCI Local Bus Specification, Revision 2.0a. The interface can operate in a
PCI/PCI-X 64-bit slot, but only at +3.3V. The interface operates at up to PCI-X 133 MHz. The interface
also provides the PEX 8114RDK-R with power, as well as +3.3 VDC to the PCI Express straddle-mount
slot connector.
3.6.1 PCI RST#
PCI RST# into the PEX 8114 is generated by ANDing three signals:
PEX 8114 Power Good signal from the Power Sequencer
PCI RST# from the PCI/PCI-X board edge connector
Manual PCI RST#, generated by the SW7 pushbutton
PCI RST# timing generated by the Power Good signal can be adjusted by way of the Power Sequencer.
3.7 Power
The PEX 8114RDK-R has three power domains:
PEX 8114RDK-R board power for support circuitry
PEX 8114 bridge device power
PCI Express x16 straddle-mount slot connector power
3.7.1 Board Power
+3.3 VDC from the PCI/PCI-X board edge connector is used to generate voltages for the PEX 8114, and
power the Power Sequencer IC (U12) used to turn On voltages to the PEX 8114. This voltage also
powers circuitry that is not directly connected to the PEX 8114.
If voltages are applied to the PEX 8114 +3.3V VIO balls (such as PCI signals, Strapping balls, and so
forth) without the PEX 8114 VDD33 balls being powered, the internal power ring begins to energize and a
value of approximately +1.8V appears at the VDD33 balls. This is not known to cause a problem;
however, the PEX 8114RDK-R ensures that this condition never occurs.
3.7.2 PEX 8114 Bridge Device Power
PEX 8114 power consists of:
VDD_CORE +1.0 ±0.1 VDC
VTT +1.3 to +1.8 VDC
VIO +3.3 ±0.3 VDC
3.7.2.1 PEX 8114 Voltage Generation
VDD10 and VDD10S are tied together and supplied by the VDD_CORE power plane. +3.3 VDC is
provided to the PEX 8114RDK-R by way of the PCI/PCI-X board edge connector and passed to VIO.
+3.3 VDC is also used to generate VDD_CORE and VTT. The PEX 8114 VTT voltage is
jumper-selectable (JP7) and can be fixed at +1.5 VDC (jumper pins 1 and 2), or adjustable by way of a
potentiometer (R69) (jumper pins 2 and 3).
The two PEX 8114 analog voltages, VDD33A and VDD10A, power internal core and SerDes PLLs. These
voltages are delivered to the PEX 8114 from the VIO and VDD_CORE voltages, through LC filtering
circuits.

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. 9
3.7.2.2 PEX 8114 Voltage Sequencing
All three voltages (+3.3, VTT, and +1.0 VDC) can be sequentially turned On by the Power Sequencer IC
(U12), which controls three MOSFET switches (Q3, Q5, and Q6). Optimal power sequence is from lowest
to highest voltage. The Power Sequencer monitors under-voltage conditions, and turns Off PEX 8114
power when a fault is detected. Power-up sequencing is initiated by a one-shot Supervisor IC (U24) with a
150-ms timeout, powered by the +3.3 VDC from the PCI/PCI-X board edge connector. Power sequencing
can also be manually initiated, using pushbutton SW8. Red LED DS4 indicates when the
PEX 8114RDK-R is receiving +3.3 VDC; however, the sequencer is not enabled. This LED momentarily
blinks On when the PEX 8114RDK-R is first powered up.
Alternatively, the Power Sequencer can be bypassed by removing the Q3, Q5, and Q6 MOSFET switches
and installing fuses F3 (3.0A), F7 (3.0A), and F5 (0.5A), respectively. To date, this power-up method has
been successfully implemented without experiencing problems. If current draw measurements are
needed, F3, F7, and F5 can be populated with current-sense resistors instead.
3.7.3 PCI Express Power
The PEX 8114RDK-R, as per the PCI Express Base Specification, Revision 1.0a, must provide +3.3V and
12V power to the PCI Express female straddle-mount slot connector. An on-board Hot Plug power switch,
controlled by the PEX 8114, turns the slot connector power On/Off. +3.3 VDC is provided by the PCI/PCI-
X board edge connector. Power to the PCI Express slot connector for +12 VDC, up to 2.3A draw, can be
from an on-board +5 to +12 VDC converter that draws from +5 VDC provided by the PCI/PCI-X board
edge connector. For heavier loads, +12 VDC can be provided from an ATX supply, by way of a standard
4-pin hard-drive header.
Note: This voltage converter is not operable on current versions of the PEX 8114RDK-R. PCI Express
+12 VDC must be obtained from the 4-pin hard-drive header.

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
10 © 2008 PLX Technology, Inc. All Rights Reserved.
4 Mechanical Architecture
4.1 Monitoring Point, LED Indicator, and Control Summary
This section summarizes the PEX 8114RDK-R interfaces that are used for monitoring, indicating, and
controlling PEX 8114 performance.
4.1.1 Monitoring Points
Table 1. PEX 8114RDK-R Monitoring Points
Footprint/
Silkscreen
Label Function
C27, plus side Monitors +3.3 VDC on the PCI Express straddle-mount slot connector, J5.
C28, plus side Monitors +12 VDC on the PCI Express straddle-mount slot connector, J5.
F3 Test Point via at this footprint can be used to monitor VDD_CORE voltage to the
PEX 8114.
F5 Test Point via at this footprint can be used to monitor VTT voltage to the PEX 8114.
F7 Test Point via at this footprint can be used to monitor VIO voltage to the PEX 8114.
L8 Test Point via at this footprint can be used to monitor VDD10A voltage to the
PEX 8114.
L9 Test Point via at this footprint can be used to monitor VDD33A voltage to the
PEX 8114.

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. 11
4.1.2 LED Indicators
Table 2. PEX 8114RDK-R LED Indicators
Location/
Silkscreen
Label Color Function
DS1 Green
Hot Plug HP_PWRLED# signal Hot Plug indicator for slot J5:
LED is turned On – Slot J5 is powered On.
LED is turned On and blinking – Slot J5 is in the process of being
powered On or Off.
LED is turned Off – Slot J5 is powered Off.
DS2 Amber
Hot Plug HP_ATNLED# signal Hot Plug indicator for slot J5:
LED is turned On – Slot J5 has an operational problem.
LED is turned On and blinking – A Hot Plug event for Slot J5
is occuring.
LED is turned Off – Slot J5 is in standard operation.
DS3 Red Turned On when pushbutton SW7 is pushed.
DS4 Red
Turned On when pushbutton SW8 is pushed.
Turned On when the PEX 8114RDK-F is receiving +3.3 VDC, but the Power
Sequencer is turned Off.
DS5 Green
Indicates that PEX 8114 power is On, and PERST# to the PEX 8114 is
de-asserted.
DS9, DS8,
DS7, DS6 Green PEX_LANE_GOOD[3:0]# status indicators for Lanes 3, 2, 1, or 0, respectively. Turned On when the associated lane is active.
DS10 Green
Power Good indicator. Turned On when the PCI Express straddle-mount slot
connector power is good.
4.1.3 Controls
Table 3. PEX 8114RDK-R Controls
Location/
Silkscreen
Label Function
SW1 Hot Plug Attention Button. Momentary SPST pushbutton control.
SW3 DIP switch control of PCIXCAP. (Refer to Section 3.4.1, “Switch SW3 – PCIXCAP
Control.”)
SW5 DIP switch control of some Strapping ball values to the PEX 8114, some PCI/PCI-X Bus speed control signals, and some RefClk generator control signals. (Refer to
Section 3.4.2, “Switch SW5 – Strapping and RefClk Pin Control.”)
SW7 Manual initiation of PCI Reset# to PEX 8114. Momentary SPST pushbutton control.
SW8 Manual initiation of PEX 8114 power-up sequence. Momentary SPST pushbutton
control.
JP7, R69 PEX 8114 VTT voltage is jumper-selectable and can be fixed at +1.5 VDC (jumper JP7, pins 1 and 2), or adjustable by way of a potentiometer (jumper JP7, pins 2 and 3
and potentiometer R69).

4.2 Layout Information
4.2.1 Trace Routing Design Rules
The characteristic trace impedances are within the PCI Express Base Specification, Revision 1.0a-
defined spec (100 Ohm ±5%) for differential, and within the PCI Express to PCI/PCI-X Bridge
Specification, Revision 1.0-defined spec (57 Ohm ±5%) for the single-ended.
4.2.2 Power Decoupling
Power decoupling is provided by two means – plane capacitance (provided by the PCB stackup) and
discrete decoupling capacitors. Plane capacitance filters noise above approximately 100 MHz. The
footprints for the discrete decoupling capacitors are designed such that the inductance between the pad
and plane is reduced by careful via placement. (Refer to Figure 6.)
Figure 6. Decoupling Capacitor Footprints
PEX 8114RDK-R Hardware Reference Manual, Version 3.2
12 © 2008 PLX Technology, Inc. All Rights Reserved.

4.2.3 PCB Layer Stackup
The PEX 8114RDK-R is a 12-layer, 63-mil thick PCB, as illustrated in Figure 7. The target signal
impedance for all routing layers is 57 Ohm ±5% single-ended impedance and 100 Ohm ±5% differential.
This PCB stackup was chosen for the following reasons:
Power/ground plane arrangement provides capacitance to filter supply voltage noise above
100 MHz
Differential pair routing layers and plane layers arrangement provides shielding for the
PCI Express signals
Figure 7. PEX 8114RDK-R 12-Layer PCB Stackup
PEX 8114RDK-R Hardware Reference Manual, Version 3.2
© 2008 PLX Technology, Inc. All Rights Reserved. 13

PEX 8114RDK-R Hardware Reference Manual, Version 3.2
14 © 2008 PLX Technology, Inc. All Rights Reserved.
5 References
The following is a list of documentation to provide further details.
PLX Technology, Inc.
870 W Maude Avenue, Sunnyvale, CA 94085 USA
Tel: [phone] or 408 774-9060, Fax: [phone], http://www.plxtech.com
PEX 8114BC/BD Data Book, Version 3.1 or higher
PEX 8114BD Errata, Revision 1.0 or higher
PEX 8114BB Design Checklist Application Note, Version 1.0 or higher
PEX 8114RDK-F Hardware Reference Manual
PCI Special Interest Group (PCI-SIG)
3855 SW 153rd Drive, Beaverton, OR 97006 USA
Tel: [phone], Fax: [phone], http://www.pcisig.com
PCI Local Bus Specification, Revision 2.3
PCI Local Bus Specification, Revision 3.0
PCI Express Card Electromechanical (CEM) Specification, Revision 1.1
PCI to PCI Bridge Architecture Specification, Revision 1.1
PCI Bus Power Management Interface Specification, Revision 1.2
PCI Express Base Specification, Revision 1.0a
PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0
PCI-X Addendum to PCI Local Bus Specification, Revision 1.0b
PCI-X Addendum to PCI Local Bus Specification, Revision 2.0a
PCI-X Electrical and Mechanical Addendum to the PCI Local Bus Specification,
Revision 2.0a