PLX PCI-Proto Lab/PLX-S User manual

PCI-Proto Lab/PLX-S
Technical Manual
HK Meßsysteme GmbH
Köpenicker Str. 325
12555 Berlin Germany
November 2007

2
Contents
Page
1. An Overview _______________________________________________________ 3
2. Hardware __________________________________________________________ 3
2.1. PCI9030 from PL Technology________________________________________ 4
2.1.1. The PCI Bus Interface _______________________________________________ 4
2.1.2. Local bus Interface __________________________________________________ 4
2.2. JTAG Support ______________________________________________________ 5
2.3. EEPROM __________________________________________________________ 5
3. Example Application_________________________________________________ 5
4. Some Tips for Use ___________________________________________________ 5
5. Software ___________________________________________________________ 7
6. Appendix __________________________________________________________ 8
6.1. Block Diagram______________________________________________________ 9
6.2. Electronic Circuit __________________________________________________ 10
6.3. Connection Diagrams _______________________________________________ 11
6.4. Connection Tables__________________________________________________ 13
6.5. Solder jumper settings ______________________________________________ 17
6.6. Connection Diagram EPLD __________________________________________ 18
6.7. Component Diagram________________________________________________ 19
6.8. Oscillograms ______________________________________________________ 20
6.9. Source Code EPLD M4A3-64/32 ______________________________________ 26
6.9.1. ABEL based Source Code ___________________________________________ 26
6.9.2. VHDL based Source Code ___________________________________________ 26
6.10. Delivery Addresses _________________________________________________ 27
6.11. Web Addresses ____________________________________________________ 28
6.12. Technical Product Features __________________________________________ 28
Note:
In this shortened manual version the chapters 6.2, 6.9 are not included.

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1. An Overview
PCI-Proto LAB/PLX-S is an efficient aid for developing add-on boards for personal com-
puters and other computer systems which are equipped with a PCI bus.
This board makes a quick and uncomplicated test of newly developed electronic circuits on
the PCI bus possible.
PCI-Proto LAB/PLX-S works with the universal PCI Target Controller PCI9030 from PLX
Technology, Inc., which controls typical PCI operation modes and complies with the PCI Lo-
cal Bus Specification Revision 2.2.
The board is assembled, tested and ready for immediate operation. The system designer can
mount his own hardware directly on the user area and start with the tests. This means that you
can minimize dealing with the signal plays and the technical properties (timing etc.) of the
PCI bus system.
PCI-Proto LAB/PLX-S is a long PCI board manufactured in four layers. It can be trans-
formed into a short board when cutting it off at the marked place.
PCI-Proto LAB/PLX-S is designed as a universal board that supports either 3.3V or 5V PCI
bus operation.
It's operating voltage for all electronic circuits is 3.3V. PCI-Proto LAB/PLX-S will work at
older PCI slots with 5V only, if a Low Drop voltage regulator for 3.3V main supply is
mounted at the board. The user can set reset (depending on the board) special solder jumpers
to archive his board supply from 5V or 3.3V at the used PCI slot.
The connection for 3.3V and ground is made through each of its own layers. For the 5V sup-
ply there is a grid structure on the component side.
PCI-Proto LAB/PLX-S is delivered with premounted bracket. The user may retro-equip it
with a 15-pin sub-D connector and a BNC connector.
We have added to PCI-Proto LAB/PLX-S's hardware documentation electronic schemes,
component and connection diagrams, EPLD source texts and oscillograms.
2. Hardware
As an introductory description, we will consider the block diagram (Appendix 6.1.).
Functionally, the hardware is broken down into three parts:
- PCI controller,
- serial EEPROM,
- Example application with 32bit latches and EPLD.

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2.1. PCI9030 from PLX Technolog
The PLX PCI9030 is a 32-bit, 33-MHz PCI Bus general purpose PCI Target device. It acts as
a PCI bridge between the PCI bus and the user circuits. The PLX pci9030 handles all of the
PCI signaling and software interfacing and translates the PCI bus cycles to a simple control,
address, data general interface for easy connectivity of memory and I O devices.
It has two interfaces for this purpose which are designated as following:
− the PCI bus interface
− the Local bus interface
The interfaces of the PCI controller are of varying importance for the user of
PCI-Proto LAB/PLX-S and they are described next.
2.1.1. The PCI Bus Interface
The PCI bus interface serves the purpose of coupling the controller to the PCI bus. It’s inter-
face is completely wired with the PCB edge connector on PCI-Proto LAB/PLX-S. The user
needs no effort.
2.1.2. Local bus Interface
The Local bus interface is important for the user because this is where the switching applica-
tions are connected. It is universally designed and allows the operation of hardware periphery
with data bus ranges of 8, 16 or 32bits. Local bus interface supports up to 32bits of local data
and up to 28bits of latched local addresses.
User specific systems control the data exchange effectively through the local bus interface
with the aid of classical signals such as ALE, LBEx, LAx, READY, WAIT or LW RD.
The periphery connected to it may consist of a microprocessor system or, in the simplest case,
be formed as a data latch.
The construction of the PCI controller also supports the integration of memories. It is possible
to address up to 256 Mbytes memory or up to 256 Bytes I O per local address space where
four user specific local address spaces are possible.
Application specific chip selects and general purpose I O pins are available to make user de-
signs easier and help to keep the peripheral hardware costs low.
PCI9030 chip has a set of registers to store initializing data, to effect the settings, to activate
and deactivate the operating modes and to exchange data.
For BIOS expansion you may connect ROM's with parallel interface to PCI9030.
PCI-Proto LAB/PLX-S uses a serial EEPROM with a size of 2 Kbytes which is installed on
the PCB. It contains configuration data for the controller and may be edit and overwritten
with PlxMon software program delivered with PLX SDK.
There is also the possibility of generating interrupts from the local side as well as the PCI
side.

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2.2. JTAG Support
The PCI bus has connections which may be used for `boundary scan` test processes.
PCI-Proto LAB/PLX-S also designated as `JTAG pins` makes these lines to the user on a pin
header.
2.3. EEPROM
The serial EEPROM is used in the initializing phase (when booting the host computer). It
contains obligatory configuration data which initialize the PCI controller specifically for the
PCI-Proto LAB/PLX-S application. It is possible to read in, edit and write down the
EEPROM content with the aid of the software program PlxMon which is delivered with
PLX SDK.
3. Example Application
PCI-Proto LAB/PLX-S has an example application which has the purpose of showing the
user how various hardware requirements (I O and memory access, high- and low-active signal
plays) can be adjusted. The application example makes it possible to write and read data long
words (32bit data) without greater hardware expenditures. For this purpose, a simple control
signal decoder has been created which provides control signals for writing and reading data.
PCI-Proto LAB/PLX-S is equipped with latches for intermediate storage of 32bit data input
or output. The additionally required logic is placed in a EPLD device, which also reserves
space for user-specific modifications. It can be programmed 'in system' with a simple connec-
tion cable over the computer parallel port. The source texts for EPLD are a component of this
documentation. Software for EPLD programming is available from your local Lattice sales
office normally without additional costs or as download from Lattice`s WEB presentation.
4. Some Tips for Use
In order to successfully design PCI hardware development with PCI-Proto LAB/PLX-S, it is
absolutely necessary to study this documentation and the technical manual on the PCI control-
ler. If it is not enclosed in the PCI-Proto LAB/PLX-S product, you can request it at no cost
from:
PLX Technology / SA or Scantec – Topas /Germany.
You will find the addresses and telephone numbers of the companies mentioned in the appen-
dix of this documentation.
You will also find information and tips how to work with the PCI controller on the Internet.
A technical manual on the PCI9030 is available as a PDF file. It can be downloaded at PLXs
web sides and you will also find some web addresses are also enclosed in the appendix.

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The following information is supposed to help avoid errors and make work with
PCI-Proto LAB/PLX-S easier. We will list them here without putting them any specific or-
der.
− PCI-Proto LAB/PLX-S is initialized in such a fashion that there are four I O and memory
address regions. They make the following accesses possible:
PCI region 0 mem mapped, used for host access to Local Runtime DMA registers
PCI region 1 I O mapped, used for host access to Local Runtime DMA registers
PCI region 2 I O mapped, address range 16 bytes, corresponds with local
address space 0
PCI region 3 mem mapped, address range 16 bytes, corresponds with local
address space 1
PCI region 4 disabled, corresponds with local address space 2, not used in
prototype boards delivered state
PCI region 5 disabled, corresponds with local address space 3, not used in
prototype boards delivered state
− The bus range of both local spaces (0 and 1) is initialized to 32 bit. It is possible to access
the latches installed as an example application with 32 bit, 16 bit and 8 bit read -or write
commands. You can access to the latches with I O (use base address of PCI -Region 2) or
memory based commands (use base address of PCI region 3).
− If you read and write 32 bit data you can use the address offset 0 only, if you read and
write 16 bit data you can use the address offset 0 or 2 and if you read and write 8 bit data
you might use the address offsets 0, 1, 2 or 3.
− PCI-Proto LAB/PLX-S has its own Vendor ID, Device ID, Sub vendor ID and Sub sys-
tem ID. The Vendor ID (10B5h) and Device ID (9030h) is given by the PCI-SIG to PLX
Technology and should not be changed. The Sub device ID (9030h) was issued from PLX
Technology for the used type of PCI controller and should not be changed too. The Sub
system ID (2263h) was issued specifically for the product PCI-Proto LAB/PLX-S. The
user may apply for his own Sub system ID from PLX Technology for his application. Ask
your local PLX dealer for this reason.

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5. Software
Matching Product Software is optionally available with PCI-Proto LAB/PLX-S.
PLX SDK (original manufacturer: PLX Technology), includes Host API Libraries (Applica-
tion Programming Interface) for the PCI controller, WindowsXP 2000 NT 98 Linux drivers
and some source codes examples.
PLX SDK comes with a useful monitor program PlxMon. This program makes it possible to
read and write data in BYTE, WORD and DWORD formats over I O or memory accesses.
The on board installed Example Application hardware is accessible with the PlxMon program
too. PlxMon makes it easy to change PCI controller configurations and initialisations, allows
the user to read and write the contents of the serial configuration EEPROM and much more.
There are two different variations to get access to the data latches:
- I O commands (use PCI address region 2, corresponds with local address space 0) or
- Memory commands (use PCI address region 3, corresponds with local address space 1).
The following address offsets are defined for the Example Application:
for 32bit data access:
offset 0h data bits 0 -31, byte lane 0, 1, 2, 3
for 16bit data access:
offset 0h data bits 0 -15, byte lane 0, 1
offset 2h data bits 15 -31, byte lane 2, 3
for 8bit data access:
offset 0h data bits 0 -7, byte lane 0
offset 1h data bits 8 -15, byte lane 1
offset 2h data bits 16 -23, byte lane 2
offset 3h data bits 24 -31, byte lane 3
The user finds further information about handling and use of the PLX SDK and the accompa-
nying software on the disk containing manuals and documentation.
The PLX SDK software package is not accompanying part of the PCI-Proto LAB/PLX-S
product. It must be ordered separately from our company.

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6. Appendix

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6.1. Block Diagram

10
6.2. Electronic Circuit
In this shortened manual version this chapter is not included.

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6.3. Connection Diagrams
Connection Diagram Component Side

12
Connection Diagram Solder Side

13
6.4. Connection Tables
Connection Table Pin Header JP3, JP5
Pin Name Pin
Name
01 +3,3V 02 +5V
03 out_data 00 04 out_data 01
05 out_data 02 06 out_data 03
07 out_data 04 08 out_data 05
09 out_data 06 10 out_data 07
11 GND 12 GND
13 out_data 08 14 out_data 09
15 out_data 10 16 out_data 11
17 out_data 12 18 out_data 13
19 out_data 14 20 out_data 15
21 +3,3V 22 +5V
Connection Table Pin Header JP3 (User bus/ data output 0 - 15)
Pin Name Pin
Name
01 +5V 02 +3,3V
03 out_data 31 04 out_data 30
05 out_data 29 06 out_data 28
07 out_data 27 08 out_data 26
09 out_data 25 10 out_data 24
11 GND 12 GND
13 out_data 23 14 out_data 22
15 out_data 21 16 out_data 20
17 out_data 19 18 out_data 18
19 out_data 17 20 out_data 16
21 +5V 22 +3,3V
Connection Table Pin Header JP5 (User bus/ data output 16 - 31)

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Connection Table Pin Header JP6, JP8
Pin Name Pin
Name
01 +5V 02 +3,3V
03 in_data 17 04 in_data 16
05 in_data 19 06 in_data 18
07 in_data 21 08 in_data 20
09 in_data 23 10 in_data 22
11 GND 12 GND
13 in_data 25 14 in_data 24
15 in_data 27 16 in_data 26
17 in_data 29 18 in_data 28
19 in_data 31 20 in_data 30
21 +5V 22 +3,3V
Connection Table Pin Header JP6 (User bus/ data input 16 - 31)
Pin Name Pin
Name
01 +3,3V 02 +5V
03 in_data 14 04 in_data 15
05 in_data 12 06 in_data 13
07 in_data 10 08 in_data 11
09 in_data 08 10 in_data 09
11 GND 12 GND
13 in_data 06 14 in_data 07
15 in_data 04 16 in_data 05
17 in_data 02 18 in_data 03
19 in_data 00 20 in_data 01
21 +3,3V 22 +5V
Connection Table Pin Header JP8 (User bus/ data input 0 - 15)

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Connection Table Pin Header JP4, JP7, JP1, JP2
Pin Name Pin
Name
01 +5V 02 +3,3V
03 LD 00 04 LD 01
05 LD 02 06 LD 03
07 LD 04 08 LD 05
09 LD 06 10 LD 07
11 GND 12 GND
13 LD 08 14 LD 09
15 LD 10 16 LD 11
17 LD 12 18 LD 13
19 LD 14 20 LD 15
21 +5V 22 +3,3V
Connection Table Pin Header JP4 (Local bus/ data 0 - 15)
Pin Name Pin
Name
01 +5V 02 +3,3V
03 LD 16 04 LD 17
05 LD 18 06 LD 19
07 LD 20 08 LD 21
09 LD 22 10 LD 23
11 GND 12 GND
13 LD 24 14 LD 25
15 LD 26 16 LD 27
17 LD 28 18 LD 29
19 LD 30 20 LD 31
21 +5V 22 +3,3V
Connection Table Pin Header JP7 (Local bus/ data 16 - 31)
Pin Name Pin
Name
01 TDI_S 02 TDO_S
03 TCK_S 04 TMS_S
Connection Table Pin Header JP1 (JTAG- Support)
Pin Name Pin
Name
01 TCK_C 02 TMS_C
03 TDO_C 04 TRST_C
05 TDI_C 06 GND
Connection Table Pin Header JP2 (JTAG- Support)

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Connection Table Pin Header JP20, JP21
Pin Name PCI9030
Functions
Pin Name PCI9030
Functions
01 +5V power supply
02 LA 02 output
03 LA 03 output 04 LA 04 output
05 LA 05 output 06 LA 06 output
07 LA 07 output 08 LA 08 output
09 LA 09 output 10 LA 10 output
11 LA 11 output 12 LA 12 output
13 LA 13 output 14 LA 14 output
15 LA 15 output 16 LA 16 output
17 LA 17 output 18 LA 18 output
19 LA 19 output 20 LA 20 output
21 LA 21 output 22 LA 22 output
23 LA 23 output 24 GP7 LA24 input output
25 GP6 LA25 input output 26 GP5 LA26 input output
27 GP4 LA27 input output 28 GP3 CS3 input output
29 GP2 CS2 input output 30 GP1 LLK input output
31 GP0 WT input output 32 GND power supply
Connection Table Pin Header JP20 (Local bus/ addresses 0 -31)
Pin Name PCI9030
Functions
Pin Name PCI9030
Functions
01 LPMESET
input 02 LCLK input
03 +5V power supply 04 +3,3V power supply
05 CPCISW input 06 BTERM input
07 LBE0 output 08 WR output
09 LBE1 output 10 RD output
11 LBE2 output 12 ALE output
13 LBE3 output 14 GP3 CS3 input output
15 READY input 16 LGNT output
17 GND power supply 18 LWRD output
19 ADS output 20 LREQ input
21 BLAST output 22 GP8 input output
23 GP2 CS2 input output 24 BCLKO output
25 GP0 WT input output 26 LRESET output
27 ENUM output 28 LINTI1 input
29 CS0 output 30 LINTI2 input
31 CS1 output 32 GP1 LLK input output
33 LPMINT output 34 LEDON output
Connection Table Pin Header JP21 (Local bus/ control signals)

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6.5. Solder jumper settings
Function Jumper
SJ
default
setting open closed
1 closed motherboard JTAG chain broken Motherboard JTAG chain closed
2 closed Card Power Requirement Indication
PRSNT1# is open (high)
Card Power Requirement Indication
PRSNT1# is low
3 open Card Power Requirement Indication
PRSNT2# is open (high)
Card Power Requirement Indication
PRSNT2# is low
4 open MODE input pin (PCI9030) is low MODE input pin (PCI9030) is high
5 open not user function not user function
6 closed +3.3V Main Supply active
1)
+5V Main Supply active
1)
7 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
8 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
9 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
10 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
11 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
12 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
13 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
14 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
15 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
16 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
17 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
18 open +5V Main Supply active
1)
+3.3V Main Supply active
1)
19 closed Output latch `Data 8-15` at tristate
2)
Output latch `Data 8-15` active
2)
20 closed Output latch `Data 0-7` at tristate
2)
Output latch `Data 0-7` active
2)
21 closed Output latch `Data 24-31`at tristate
2)
Output latch `Data 24-31` active
2)
22 closed Output latch 'Data 16-23' at tristate
2)
Output latch 'Data 16-23' active
2)
23 closed Input latch 'Data 16-23' locked
2)
Input latch 'Data 16-23' transparent
2)
24 closed Input latch 'Data 24-31' locked
2)
Input latch 'Data 24-31' transparent
2)
25 closed Input latch 'Data 0-7' locked
2)
Input latch 'Data 0-7' transparent
2)
26 closed Input latch 'Data 8-15' locked
2)
Input latch 'Data 8-15' transparent
2)
1)
Close SJ6 and let SJ7–SJ18 open for +5V main supply, close SJ7–SJ18 and let SP6 open for +3.3V main supply.
To prevent electric damages never close SJ6 and SJ7-SJ18 at the same time.
Presence of +3.3V supply at the used slot connector is signalized by Indicator LED D1 (yellow LED).
2)
Open SJ19- 26 for access to the OE- and LE- signals from additional electrical circuits.

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6.6. Connection Diagram EPLD
Socket Diagram M4A3-64 32 Solder Side
Pin Name M4A3-64 32
Functions
Pin
Name M4A3-64 32
Functions
1 GND power supply 23 GND power supply
2 LREQ output 24 CS1 input (inactive)
3 BTERM output 25 CS0 input (inactive)
4 ALE input (inactive) 26 GP2 CS2 in- output (inactive)
5 BLAST input (inactive) 27 GP3 CS3 in- output (inactive)
6 LWRD input 28 not used I O20
7 LA2 input 29 not used I O21
8 ADS input 30 LBE3 input
9 LA3 input 31 LBE2 input
10 TDI ISP-Interface 32 TDS ISP-Interface
11 GP1 LLK
in- output (inactive) 33 LCLK CLK1 I1
12 GND power supply 34 GND power supply
13 TCLK ISP-Interface 35 TDO ISP-Interface
14 IOE3 output 36 LBE1 input
15 IOE2 output 37 LBE0 input
16 IOE1 output 38 GP0 WT in- output (inactive)
17 IOE0 output 39 LRESET input
18 OLE0 output 40 WR input (inactive)
19 OLE1 output 41 RD input (inactive)
20 OLE3 output 42 READY output
21 OLE2 output 43 LGNT input (inactive)
22 +3,3V power supply 44 +3,3V power supply

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6.7. Component Diagram

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6.8. Oscillograms