ICP DAS USA PIO-D56 User manual

PIO-D56/D24
User’s Manual
Warranty
All products manufactured by ICP DAS are warranted
against defective materials for a period of one year from
the date of delivery to the original purchaser.
Warning
ICP DAS assumes no liability for damages
consequent to the use of this product. ICP DAS reserves
the right to change this manual at any time without notice.
The information furnished by ICP DAS is believed to be
accurate and reliable. However, no responsibility is
assumed by ICP DAS for its use, nor for any infringements
of patents or other rights of third parties resulting from its
use.
Copyright
Copyright 2004 by ICP DAS. All rights are reserved.
Trademark
The names used for identification only may be
registered trademarks of their respective companies.
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 1

Tables of Content
1. INTRODUCTION............................................................................................4
1.1 FEATURES................................................................................................................. 4
1.2 SPECIFICATIONS ....................................................................................................... 5
1.3 PRODUCT CHECK LIST ............................................................................................. 5
2. HARDWARE CONFIGURATION ...............................................................6
2.1 BOARD LAYOUT....................................................................................................... 6
2.2 I/O PORT LOCATION................................................................................................. 7
2.3 PIN ASSIGNMENT...................................................................................................... 8
2.4 ENABLE I/O OPERATION ........................................................................................ 10
2.4.1 DI/O Port Architecture (CON3).................................................................... 10
2.4.2 DI Port Architecture (CON2)........................................................................ 12
2.4.3 DO Port Architecture (CON1) ...................................................................... 13
2.5 INTERRUPT OPERATION.......................................................................................... 14
2.6 DAUGHTER BOARDS............................................................................................... 15
2.6.1. DB-37............................................................................................................ 15
2.6.2. DN-37 & DN-50............................................................................................ 15
2.6.3. DB-8125........................................................................................................ 16
2.6.4. ADP-20/PCI.................................................................................................. 16
2.6.5. DB-24P, DB-24PD Isolated Input Board...................................................... 17
2.6.6. DB-24R, DB-24RD Relay Board................................................................... 18
2.6.7. DB-24PR, DB-24POR, DB-24C.................................................................... 19
2.6.8. Daughter Board Comparison Table.............................................................. 20
3. I/O CONTROL REGISTER.........................................................................21
3.1 HOW TO FIND THE I/O ADDRESS............................................................................ 21
3.2 THE ASSIGNMENT OF I/O ADDRESS ....................................................................... 24
3.3 THE I/O ADDRESS MAP.......................................................................................... 26
3.3.1. RESET\ Control Register............................................................................... 27
3.3.2. AUX Control Register ................................................................................... 27
3.3.3. AUX data Register......................................................................................... 27
3.3.4. INT Mask Control Register ........................................................................... 28
3.3.5. Aux Status Register........................................................................................ 28
3.3.6. Interrupt Polarity Control Register............................................................... 28
3.3.7. I/O Selection Control Register...................................................................... 29
3.3.8. Read/Write 8-bit data Register...................................................................... 30
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 2

4. SOFTWARE INSTALLATION...................................................................31
4.1 SOFTWARE INSTALLING PROCEDURE..................................................................... 31
4.2 PNPDRIVER INSTALLATION .................................................................................. 31
5. DLL FUNCTION DESCRIPTION ..............................................................32
5.1 TABLE OF ERRORCODE AND ERRORSTRING.......................................................... 33
5.2 FUNCTION DESCRIPTIONS ...................................................................................... 33
5.3 FUNCTIONS OF TEST......................................................................................... 35
5.3.1 PIODIO_GetDllVersion................................................................................ 35
5.3.2 PIODIO_ShortSub ........................................................................................ 35
5.3.3 PIODIO_FloatSub ........................................................................................ 35
5.4 DIGITAL I/O FUNCTIONS .................................................................................... 36
5.4.1. PIODIO_OutputByte..................................................................................... 36
5.4.2. PIODIO_InputByte........................................................................................ 36
5.4.3. PIODIO_OutputWord................................................................................... 37
5.4.4. PIODIO_InputWord...................................................................................... 37
5.5 DRIVER RELATIVE FUNCTIONS.............................................................................. 38
5.5.1. PIODIO_GetDriverVersion .......................................................................... 38
5.5.2. PIODIO_DriverInit....................................................................................... 38
5.5.3. PIODIO_SearchCard.................................................................................... 39
5.5.4. PIODIO_DriverClose ................................................................................... 39
5.5.5. PIODIO_GetConfigAddressSpace................................................................ 40
5.6 INTERRUPT FUNCTION..................................................................................... 41
5.6.1 PIODIO_IntResetCount ................................................................................ 41
5.6.2 PIODIO_IntGetCount................................................................................... 41
5.6.3 PIODIO_IntInstall ........................................................................................ 42
5.6.4 PIODIO_IntRemove...................................................................................... 43
5.6.5 Architecture of Interrupt mode...................................................................... 43
5.6.6 Program Architecture.................................................................................... 44
6. DEMO PROGRAMS FOR WINDOWS......................................................45
6.1 DIGITAL INTPUT AND OUTPUT................................................................................ 46
6.2 INTERRUPT OF P2C0............................................................................................... 46
APPENDIX.................................................................................................................47
APPENDIX A. RELATED DOS SOFTWARE.......................................................................... 47
A-1 Where is the related software ............................................................................ 47
A-2 DOS LIB Function............................................................................................. 48
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 3

1. Introduction
The PIO-D56/PIO-D24 provides 56/24 TTL digital I/O lines. The PIO-
D56 consists of one 24-bit bi-directional port, one 16-bit input port and one 16-
bit output port. However, PIO-D24 only contains the 24-bit bi-directional port.
The 24-bit port supports three 8-bit groups, which are PA, PB and PC,
respectively. Each 8-bit group can be individually configured to function as
digital input or output port. Each group in a 24-bit bi-directional port is
configured as digital inputs once the power is turned on or if a reset has been
executed.
DB-24PD is the daughter board, which is designed to connect the input
port for either isolation purposes or to interface to the output port for relay
control. PIO-D24 has one D-sub connector. However, The PIO-D56 contains
one D-sub connector and two 20-pin flat cables. The flat cable can be
connected to an ADP-20/PCI adapter. The adapter can be fixed onto the
chassis. This product can be installed into a 5V PCI bus and supports actual
“Plug & Play” technology.
1.1 Features
•PCI bus
•Up to 56/24(PIO-D56/PIO-D24) digital I/O channels lines
•All I/O lines buffered on the board
•3 Eight-bit groups independently selectable for I/O on 24-bit port
•Input / Output ports can be configured via software control
•Double side SMD, short card.
•Connects directly to DB-24PR, DB-24PD, DB-24RD,
DB-24PRD, DB-16P8R, DB-24POR, DB-24SSR, DB-24C or any OPTO-22
compatible daughter board
•4 interrupt sources: P2C0, P2C1, P2C2, P2C3
•One DB37 connector, two 20-pin flat cable connectors (only for PIO-D56)
•High driving capability
•Automatically detected by Windows 95/98/2000/XP
•No base address or IRQ switches to set
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 4

1.2 Specifications
•All inputs are TTL compatible
Logic high voltage : 2.4V (Min.)
Logic low voltage : 0.8V (Max.)
•All outputs are TTL compatible
OPTO-22 output (CON3):
Sink current : 64mA (Max.)
Source current : 32mA(Max.)
16-channel output (CON1):
Sink current : 8mA (Max.)
Source current : 0.4mA(Max.)
•Environmental :
Operating Temperature: 0°C to 60°C
Storage Temperature: -20°C to 80°C
Humidity: 0 to 90% non-condensing
•Dimensions: 143mm X 105mm
•Power Consumption: +5V @ 530mA/420mA(PIO-D56/PIO-D24)
1.3 Product Check List
In addition to this manual, the package includes the following items:
•One PIO-D56(or PIO-D24) card
•One company floppy diskette or CD
•One release note
It is recommended to read the release note first. All important information will
be given in the release in the following order:
1. Where you can find the software driver & utility.
2. How to install the software & utility
3. Where the diagnostic program is.
4. FAQ’s.
Attention:
If any of these items is missing or damaged, contact the dealer from whom
you purchased the product. Save the shipping materials and carton in case
you want to ship or store the product in the future.
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 5

2. Hardware configuration
2.1 Board Layout
Figure2.1
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 6

2.2 I/O Port Location
The PIO-D56/PIO-D24 consists of one 24-bit bi-directional port, one 16-bit
input port and one 16-bit output port (only for PIO-D56). The 24-bit port
supports three 8-bit groups, which are PA, PB and PC, respectively. Each 8-
bit group can be configured as a D/I or D/O port via the software. Note that
when the PC is first turned on or if a reset has been executed, all ports are set
as D/I ports. The I/O port location is given as follows:
Table 2.1
Connector of PIO-D56/D24 PA0 ~ PA7 PB0 ~ PB7 P2C0 ~ PC7
CON3 (DI/O) Port0 Port1 Port2
Table 2.2
Connector of PIO-D56 Description
CON1 D/O
CON2 D/I
Refer to Sec. 2.1 for board layout & I/O port location.
Note : P2C0, P2C1, P2C2 and P2C3 can be used as interrupt signal source.
Refer to Sec. 2.5 for more information.
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 7

2.3 Pin Assignment
The Pin assignments for all connectors on the PIO-D56/D24 are
represented in Tables 2.3, 2.4 and 2.5. All signal sources for each digital input
or output pin (channel) is TTL compatible.
Table 2.3 CON3: 37 pin D-type female connector(for Port0, Port1, Port2).
Pin Number Description Pin Number Description
1 N.C. 20 VCC
2 N.C. 21 GND
3 P1B7 22 P2C7
4 P1B6 23 P2C6
5 P1B5 24 P2C5
6 P1B4 25 P2C4
7 P1B3 26 P2C3
8 P1B2 27 P2C2
9 P1B1 28 P2C1
10 P1B0 29 P2C0
11 GND 30 P0A7
12 N.C. 31 P0A6
13 GND 32 P0A5
14 N.C. 33 P0A4
15 GND 34 P0A3
16 N.C. 35 P0A2
17 GND 36 P0A1
18 VCC 37 P0A0
19 GND XXXXXXX This pin not available
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 8

Table 2.4 CON1 : 20-pin header (only for PIO-D56)
Pin Number Description Pin Number Description
1 DO0 2 DO1
3 DO2 4 DO3
5 DO4 6 DO5
7 DO6 8 DO7
9 DO8 10 DO9
11 DO10 12 DO11
13 DO12 14 DO13
15 DO14 16 DO15
17 GND 18 GND
19 Vcc 20 +12V
Table 2.5 CON2 : 20-pin header (only for PIO-D56)
Pin Number Description Pin Number Description
1 DI0 2 DI1
3 DI2 4 DI3
5 DI4 6 DI5
7 DI6 8 DI7
9 DI8 10 DI9
11 DI10 12 DI11
13 DI12 14 DI13
15 DI14 16 DI15
17 GND 18 GND
19 Vcc 20 +12V
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 9

2.4 Enable I/O Operation
When the PC is turned on, all operations involved with digital I/O
channels(CON1, CON2, CON3) are disabled. Note that the digital I/O
channels are enabled or disabled by the RESET\ signal. (Refer to Sec. 3.3.1
for more information related to this).
2.4.1 DI/O Port Architecture (CON3)
The power-on states for all DI/O ports(CON3) are given as follows:
•D/I/O operations for each port are disabled.
•D/I/O ports are all configured as Digital input ports.
•D/O latch register outputs are all undefined.
The user has to perform some initialization before using these digital
I/O ports. The recommended steps are given as follows:
Step 1: Find the address-mapping for PIO/PISO cards. (Refer to Sec.3.1)
Step 2: Enable all Digital I/O operations. (Refer to Sec. 3.3.1).
Step 3:Configure the three ports (in CON3) to their expected D/I/O states
& send their initial values to every D/O port (Refer to Sec. 3.3.7
and Sec.3.3.8)
For more information on the initial procedure for digital I/O ports,
please refer to the DEMO1.C demo program.
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 10

The digital I/O (CON3) control architecture for the PIO-D56/D24 is
demonstrated in Figure 2.2. The operation method used for the control signal
is presented below.
•RESET\ is in the Low-state Æall D/I/O operations are disabled
•RESET\ is in the High-state Æall D/I/O operations are enabled.
•If D/I/O is configured as a D/I port ÆD/I= external input signal
•If D/I/O is configured as a D/O port ÆD/I = read back of D/O
•If D/I/O is configured as a D/I port Æsending data to a Digital input port
will only change the D/O latch register. The latched data will be output
when the port is configured as digital output and is activated right away.
Figure2.2 DI/O Port Architecture(CON3)
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 11

2.4.2 DI Port Architecture (CON2)
The digital input (CON2) control architecture for the PIO-D56 is
demonstrated in Figure 2.3.
•RESET\ is in the Low-state Æall DI operations are disabled
•RESET\ is in the High-state Æall DI operations are enabled
Figure2.3 DI Port Architecture (CON2)
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 12

2.4.3 DO Port Architecture (CON1)
The digital output (CON1) control architecture for the PIO-D56 is
demonstrated in Figure 2.4.
•RESET\ is in the Low-state Æall DO operations are disabled
•RESET\ is in the High-state Æall DO operations are enabled
The power-on states are as follows:
•All DO operations are disabled
•All output latches are cleared to Low-Level
Figure2.4 DO Port Architecture (CON1)
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 13

2.5 Interrupt Operation
The P2C0, P2C1, P2C2 and P2C3 can be used as interrupt signal source.
Refer to Sec. 2.1 for P2C0/P2C1/P2C2/P2C3 location. The interrupt of the
PIO-D56/PIO-D24 is level-trigger & Active_High. The interrupt signal can be
programmable as inverted or non-inverted. The procedures for how to
configure the interrupt signal source are given as follows:
1. Make sure the initial level is high or Low from the signal source.
2. If the initial state is High, please select the inverted setting for interrupt
signal source (Section. 3.3.6). If the initial state is Low, please select the
non-inverted setting for interrupt signal source (Section. 3.3.6)
3. Enable the interrupt function (Section. 3.3.4)
4. If the interrupt signal is active, the interrupt service routine will be started
up.
Note that DEMO3.C & DEMO4.C are demo programs for a single interrupt
source and DEMO5.C is the demo program for four interrupt sources in the
DOS operating system. If only one interrupt signal source is used, the
interrupt service routine does not need to identify the interrupt source. (Refer
to DEMO3.C & DEMO4.C). However, if there are more than one interrupt
source, the interrupt service routine has to identify the active signals in the
following manner: (refer to DEMO5.C)
1.Read the new status of the interrupt signal sources
2.Compare the new status with the old status to identify the active signals
3.If P2C0 is active, service P2C0 & non-inverter/inverted the P2C0 signal
4.If P2C1 is active, service P2C1 & non-inverted/inverted the P2C1 signal
5.If P2C2 is active, service P2C2 & non-inverted/inverted the P2C2 signal
6.If P2C3 is active, service P2C3 & non-inverted/inverted the P2C3 signal
7.Update the interrupt status.
Limitation: if the interrupt signal is too short, the new status may be the
same as the old status. So the interrupt signal must be held active until the
interrupt service routine has been executed. This hold time is different for
differing operating systems. The hold time can be as short as a micro-second
or as long as 1 second. In general, 20ms is enough for all O.S.
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 14

2.6 Daughter Boards
2.6.1. DB-37
The DB-37 is a general purpose daughter board for D-sub 37 pins. It is
designed for easy wire connection via pin-to-pin.
Figure 2.5 DB-37
2.6.2. DN-37 & DN-50
The DN-37 is a general purpose daughter board for DB-37 pins with DIN-
Rail Mountings. The DN-50 is designed for 50-pin flat-cable headers win DIN-
Rail mountings. They are also designed for easy wire connection via pin-to-pin.
Figure 2.6 DN-37/DN-50
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 15

2.6.3. DB-8125
The DB-8125 is a general purpose screw terminal board. It is designed for
easy wire connection. The DB-8125 consists of one DB-37 & two 20-pin flat-
cable headers.
Figure 2.7 DB-1825
2.6.4. ADP-20/PCI
The ADP-20/PCI is an extender for the 20-pin header. The one side of
the ADP-20/PCI can be connected to a 20-pin header. The other side can be
mounted onto the PC chassis as is depicted by the following:
Figure 2.8 ADP-20/PCI
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 16

2.6.5. DB-24P, DB-24PD Isolated Input Board
The DB-24P is a 24-channel isolated digital input daughter board. The
optically isolated inputs of the DB-24P consist of a bi-directional optocoupler
with a resistor for current sensing. You can use the DB-24P to sense DC
signals from TTL levels up to 24V or use the DB-24P to sense a wide range of
AC signals. You can also use this board to isolate the computer from large
common-mode voltage, ground loops and transient voltage spikes that often
occur in industrial environments, as shown in Figure 2.9. Table 2.4 is the
comparison of DB-24P and DB-24PD.
Figure 2.9
Table 2.6
DB-24P DB-24PD
50-pin flat-cable header Yes Yes
D-sub 37-pin header No Yes
Other specifications Same
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 17

2.6.6. DB-24R, DB-24RD Relay Board
The DB-24R, 24-channel relay output board, consists of 24 form-C
relays for efficiently controlling the switch with the use of an appropriately
loaded program. The relays are energized by applying a 12V/24V voltage
signal to the appropriate relay channel on the 50-pin flat-cable connector.
There are 24 enunciator LEDs for each relay channel and the LED light will go
on when their associated relay has been activated. The control scheme is
illustrated below.
Figure 2.10
Table 2.7
DB-24R DB-24RD
50-pin flat-cable header Yes Yes
D-sub 37-pin header No Yes
Other specifications Same
Table 2.8
DB-24R, DB-24RD 24*Relay (120V, 0.5A)
DB-24PR,DB-24PRD 24* Power Relay (250V, 5A)
DB-24POR 24*PhotoMOS Relay (350V, 01.A)
DB-24SSR 24*SSR (250VAC, 4A)
DB-24C 24*O.C. (30V, 100 mA)
DB-16P8R 16*Relay (120V, 0.5A) + 8*isolated input
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 18

2.6.7. DB-24PR, DB-24POR, DB-24C
Table 2.9
DB-24PR 24*power relay, 5A/250V
DB-24POR 24*PhotoMOS relay, 0.1A/350VAC
DB-24C 24*open collector, 100mA per channel, 30V max.
The DB-24PR, 24-channel power relay output board, consists of 8 form-
C and 16 form-A electromechanical relays for efficiently controlling the switch
with the use of an appropriately loaded program. The contact of each relay
can allow 5A current load at 250ACV/30VDCV. The relay is energized by
applying a 5 voltage signal to the associate relay channel on the 20-pin flat-
cable connector (just used 16 relays) or 50-pin flat-cable connector (OPTO-22
compatible, for DIO-24 series). 24 enunciator LEDs for indicating the status of
for each relay and the corresponding LED light will go on when their
associated relay has been activated. To avoid overloading your PC’s power
supply, this board needs a +12VDC or +24VDC external power supply, as
shown in figure 2.11.
Figure 2.11
Note:
1. 50-Pin connector(OPTO-22 compatible), for DIO-24, DIO-48, DIO-144,
PIO-D144, PIO-D96, PIO-D56, PIO-D48, PIO-D24,PIO-D168
2. 20-Pin connector for 16 channel digital output, A-82X, A-62X, DIO-64,
ISO-DA16/DA8,
3. Channel: 16 Form A Relay , 8 Form C Relay.
4. Relay: switching up to 5A at 110ACV / 5A at 30DCV.
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 19

2.6.8. Daughter Board Comparison Table
Table 2.10
20-pin flat-cable 50-pin flat-cable D-sub 37-pin
DB-37 No No Yes
DN-37 No No Yes
ADP-37/PCI No Yes Yes
ADP-50/PCI No Yes No
DB-24P No Yes No
DB-24PD No Yes Yes
DB-16P8R No Yes Yes
DB-24R No Yes No
DB-24RD No Yes Yes
DB-24C Yes Yes Yes
DB-24PR Yes Yes No
Db-24PRD No Yes Yes
DB-24POR Yes Yes Yes
DB-24SSR No Yes Yes
Note : There is no 50-pin flat cable header in the PIO-D56/PIO-D24. The PIO-
D56/PIO-D24 has one DB-37 connector and two 20 pin flat-cable headers
(only for PIO-D56).
PIO-D56/PIO-D24 User’s Manual (Ver.2.3, JUN/2004, PPH-005-23) ---- 20