rtd ERES35105HR User manual

RTD Embedded Technologies, Inc.
AS9100 and ISO 9001 Certified
ERES35105HR
PCI Express Dual Synchro/Resolver/LVDT Interface
User’s Manual
BDM-610020152 Rev. A

RTD Embedded Technologies, Inc.
103 Innovation Boulevard
State College, PA 16803 USA
Telephone: [phone]
Fax: [phone]
www.rtd.com
[email protected]
[email protected]

RTD Embedded Technologies, Inc. | www.rtd.com iii ERES35105 User’s Manual
Revision History
Rev A Initial Release
Advanced Analog I/O, Advanced Digital I/O, aAIO, aDIO, a2DIO, Autonomous SmartCal, “Catch the Express”, cpuModule, dspFramework, dspModule, eBuild, expressMate, ExpressPlatform, “MIL Value for COTS
prices”, multiPort, PlatformBus, and PC/104EZ are trademarks, and “Accessing the Analog World”, dataModule, IDAN, HiDAN, HiDANplus, RTD, the RTD logo, and StackNET are registered trademarks of RTD
Embedded Technologies, Inc. (formerly Real Time Devices, Inc.). PS/2 is a trademark of International Business Machines Inc. PCI, PCI Express, and PCIe are trademarks of PCI-SIG. PC/104, PC/104-Plus, PCI-104,
PCIe/104, PCI/104-Express and 104 are trademarks of the PC/104 Consortium. All other trademarks appearing in this document are the property of their respective owners.
Failure to follow the instructions found in this manual may result in damage to the product described in this manual, or other components of the system. The procedure set forth in this manual shall only be performed
by persons qualified to service electronic equipment. Contents and specifications within this manual are given without warranty, and are subject to change without notice. RTD Embedded Technologies, Inc. shall not
be liable for errors or omissions in this manual, or for any loss, damage, or injury in connection with the use of this manual.
Copyright © 2019 by RTD Embedded Technologies, Inc. All rights reserved.

RTD Embedded Technologies, Inc. | www.rtd.com iv ERES35105 User’s Manual
Table of Contents
1Introduction 7
Product Overview........................................................................................................................................................................ 7
Board Features ........................................................................................................................................................................... 7
Ordering Information................................................................................................................................................................... 7
Contact Information .................................................................................................................................................................... 8
1.4.1 Sales Support 8
1.4.2 Technical Support 8
2Specifications 9
Operating Conditions .................................................................................................................................................................. 9
Electrical Characteristics ............................................................................................................................................................ 9
3Board Connection 10
Board Handling Precautions ..................................................................................................................................................... 10
Physical Characteristics............................................................................................................................................................ 11
Connectors and Jumpers.......................................................................................................................................................... 12
3.3.1 External I/O Connectors 12
J1: Sensor Input / Output 12
3.3.2 Bus Connectors 13
CN1 (Top) & CN2 (Bottom): PCIe Connector 13
3.3.3 Jumpers 13
Steps for Installing .................................................................................................................................................................... 14
4IDAN Connections 15
Module Handling Precautions................................................................................................................................................... 15
Physical Characteristics............................................................................................................................................................ 15
Connector Locations................................................................................................................................................................. 16
Connectors................................................................................................................................................................................ 16
4.4.1 External I/O Connectors 17
Sensor Input / Output 17
4.4.2 Bus Connectors 17
CN1 (Top) & CN2 (Bottom): PCIe Connector 17
Steps for Installing .................................................................................................................................................................... 18
5Functional Description 19
Block Diagram........................................................................................................................................................................... 19
PCIe Switch .............................................................................................................................................................................. 19
Resolver to Digital Converter.................................................................................................................................................... 19
5.3.1 Bandwidth Filters 20
Front End .................................................................................................................................................................................. 20
On-Board Excitation.................................................................................................................................................................. 20
EPLD......................................................................................................................................................................................... 20
6Board Configuration 21
Sensor Input Connections ........................................................................................................................................................ 21
6.1.1 Resolver Input 21
Input Connections 21
Jumper Configuration 21
6.1.2 Synchro Input 22
Input Connections 22
Jumper Configuration 22

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6.1.3 2-Wire LVDT Input 23
Input Connections 23
Jumper Configuration 23
6.1.4 3-Wire LVDT Input 24
Input Connections 24
Jumper Configuration 24
6.1.5 Direct Input 25
Input Connections 25
Jumper Configuration 25
Reference Input ........................................................................................................................................................................ 26
6.2.1 Internally Generated Reference 26
Connections 26
Jumper Configuration 26
6.2.2 Differential Externally Generated Reference 27
Connections 27
Jumper Configuration 27
6.2.3 Single-Ended Externally Generated Reference 27
Connections 27
Jumper Configuration 27
7Register Address Space 28
Identifying the Board................................................................................................................................................................. 28
Index and Data Registers ......................................................................................................................................................... 28
7.2.1 GPIOAB_CTRL (Read/Write) 28
7.2.2 GPIOCD_CTRL (Read/Write) 28
7.2.3 SELECT (Read/Write) 28
7.2.4 INDEX_DATA (Read/Write) 29
Accessing the Board Registers................................................................................................................................................. 29
7.3.1 Reading from a Board Register 29
7.3.2 Writing to a Board Register 30
7.3.3 Reading Shift Register Status 31
Board Registers ........................................................................................................................................................................ 31
7.4.1 BUILD_NUM_LS, BUILD_NUM_MS (Read-Only) 31
7.4.2 SR_SELECT (Read/Write) 31
7.4.3 SR_DATA_OUT (Read/Write) 32
7.4.4 SR_DATA_IN (Read-Only) 32
7.4.5 CHx_SETUP_STATUS (Read/Write, Read-Only) 32
7.4.6 CHx_POSITION (Read-Only) 32
Shift Register ............................................................................................................................................................................ 33
7.5.1 Performing a Shift Register Command 33
7.5.2 Channel x Mode (0x00 and 0x02) 33
Output Data 33
Input Data 33
Modes 34
7.5.3 Channel x Velocity Trim (0x01 and 0x03) 34
Output Data 34
Input Data 34
7.5.4 Excitation Frequency (0x04) 35
Output Data 35
Input Data 35
7.5.5 Excitation Amplitude (0x05) 35
Output Data 35
Input Data 35
8Troubleshooting 36
9Additional Information 37
PC/104 Specifications............................................................................................................................................................... 37
PCI and PCI Express Specification .......................................................................................................................................... 37
10 Limited Warranty 38

RTD Embedded Technologies, Inc. | www.rtd.com vi ERES35105 User’s Manual
Table of Figures
Figure 1: Board Dimensions ................................................................................................................................................................................... 11
Figure 2: Board Connections .................................................................................................................................................................................. 12
Figure 3: Jumper Locations .................................................................................................................................................................................... 13
Figure 4: Example 104™Stack............................................................................................................................................................................... 14
Figure 5: IDAN Dimensions .................................................................................................................................................................................... 15
Figure 6: IDAN Front Panel Connector Locations .................................................................................................................................................. 16
Figure 7: Example IDAN System ............................................................................................................................................................................ 18
Figure 8: ERES35105 Block Diagram .................................................................................................................................................................... 19
Figure 9: 2-Wire LVDT Schematic .......................................................................................................................................................................... 23
Figure 10: 3-Wire LVDT Schematic ........................................................................................................................................................................ 24
Table of Tables
Table 1: Ordering Options ........................................................................................................................................................................................ 7
Table 2: Operating Conditions .................................................................................................................................................................................. 9
Table 3: Electrical Characteristics ............................................................................................................................................................................ 9
Table 4: J1 Input / Output Pin Assignments .......................................................................................................................................................... 12
Table 5: IDAN-ERES35105HR-xS Panel Connectors and Mating Connectors ..................................................................................................... 16
Table 6: IDAN Input / Output Pin Assignments ..................................................................................................................................................... 17
Table 7: Bandwidth Filters ...................................................................................................................................................................................... 20
Table 8: Resolver Input Connections...................................................................................................................................................................... 21
Table 9: Resolver Jumper Settings......................................................................................................................................................................... 21
Table 10: Synchro Input Connections..................................................................................................................................................................... 22
Table 11: Synchro Jumper Settings........................................................................................................................................................................ 22
Table 12: 2-Wire LVDT Input Connections............................................................................................................................................................. 23
Table 13: 2-Wire LVDT Jumper Settings................................................................................................................................................................ 23
Table 14: 3-Wire LVDT Input Connections............................................................................................................................................................. 24
Table 15: 3-Wire LVDT Jumper Settings................................................................................................................................................................ 24
Table 16: Direct Input Connections ........................................................................................................................................................................ 25
Table 17: Direct Input Jumper Settings .................................................................................................................................................................. 25
Table 18: Internal Reference Connections ............................................................................................................................................................. 26
Table 19: Internal Reference Jumper Settings ....................................................................................................................................................... 26
Table 20: Differential External Reference Connections.......................................................................................................................................... 27
Table 21: Differential External Reference Jumper Settings.................................................................................................................................... 27
Table 22: Single-Ended External Reference Connections ..................................................................................................................................... 27
Table 23: Single-Ended External Reference Jumper Settings ............................................................................................................................... 27
Table 24: Identifying the ERES35105..................................................................................................................................................................... 28
Table 25: Index and Data Registers ....................................................................................................................................................................... 28
Table 26: Board Registers ...................................................................................................................................................................................... 31
Table 27: Channel Mode Shift Register.................................................................................................................................................................. 33
Table 28: Channel Modes....................................................................................................................................................................................... 34
Table 29: Velocity Trim Shift Register .................................................................................................................................................................... 34
Table 30: Excitation Amplitude Shift Register ........................................................................................................................................................ 35
Table 31: Excitation Amplitude Values ................................................................................................................................................................... 35

RTD Embedded Technologies, Inc. | www.rtd.com 7ERES35105 User’s Manual
1Introduction
Product Overview
The ERES35105 provides a direct interface to two Synchro/Resolver/LVDT channels on the compact PC/104 form factor with a stackable PCI
Express bus. Both sensor input channels are independently configurable with jumpers. An onboard solid state Scott-T circuitry provides a
precision conversion from Synchro to Resolver signals. Onboard precision thin-film resistor divider networks for 2.0, 11.8 or 90.0 VRMS
configurations.
The onboard programmable sine wave oscillator reference outputs a 0 - 7VRMS excitation signal with a programmable frequency range of 0 Hz
to 10 kHz.
Board Features
•PC/104 form factor
•PCIe/104 stackable bus structure
oPCIe/104 Universal Connector
oUses a PCIe x1 link
oRepopulates the PCIe bus
•2 Independent Channels
•Directly interfaces to Synchros, Resolvers and LVDTs
•Connection to 2.0V/11.8V/90.0V sensors
•Programmable resolution 10/12/14/16 - bits
•+5V only operation
•Programmable sine wave excitation
o0 Hz to 10 kHz frequency range
o0V to 7VRMS voltage range
oUp to 100mA drive current at 85C
•Dual software selectable filters can be changed on-the-fly
oHigh Resolution mode for 16-bit resolution
oHigh Velocity mode for tracking rate up to 320 rps
oOther filter options available
•Synthesized reference corrects for phase shift up to 45 degrees
•Loss of signal detection
•Single-ended or Differential Inputs
•PCI Express (PCIe) x1 Upstream Interface to CPU
Ordering Information
The ERES35105 is available with the following options:
Table 1: Ordering Options
Part Number
Description
ERES35105HR-1
PCIe/104 Two-Channel, 11.8 VRMS Synchro/Resolver to Digital Peripheral Module
ERES35105HR-2
PCIe/104 Two-Channel, 90.0 VRMS Synchro/Resolver to Digital Peripheral Module
ERES35105HR-3
PCIe/104 Two-Channel, 2.0 VRMS Synchro/Resolver to Digital Peripheral Module
IDAN- ERES35105HR-1S
PCIe/104 Two-Channel, 11.8 VRMS Synchro/Resolver to Digital Peripheral Module in IDAN enclosure
IDAN- ERES35105HR-2S
PCIe/104 Two-Channel, 90.0 VRMS Synchro/Resolver to Digital Peripheral Module in IDAN enclosure
IDAN- ERES35105HR-3S
PCIe/104 Two-Channel, 2.0 VRMS Synchro/Resolver to Digital Peripheral Module in IDAN enclosure
The Intelligent Data Acquisition Node (IDAN™) building block can be used in just about any combination with other IDAN building blocks to
create a simple but rugged 104™ stack. This module can also be incorporated in a custom-built RTD HiDAN™ or HiDANplus®High Reliability
Intelligent Data Acquisition Node. Contact RTD sales for more information on our high reliability systems.

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Contact Information
1.4.1 SALES SUPPORT
For sales inquiries, you can contact RTD Embedded Technologies sales via the following methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]
1.4.2 TECHNICAL SUPPORT
If you are having problems with your system, please try the steps in the Troubleshooting section of this manual on page 28.
For help with this product, or any other product made by RTD, you can contact RTD Embedded Technologies technical support via the
following methods:
Phone: [phone] Monday through Friday, 8:00am to 5:00pm (EST).
E-Mail: [email protected]

RTD Embedded Technologies, Inc. | www.rtd.com 9ERES35105 User’s Manual
2Specifications
Operating Conditions
Table 2: Operating Conditions
Symbol
Parameter
Test Condition
Min
Max
Unit
Vcc5
5V Supply Voltage
4.75
5.25
V
Vcc3
3.3V Supply Voltage
n/a
n/a
V
Vcc12
12V Supply Voltage
n/a
n/a
V
Vcc-12
-12V Supply Voltage
n/a
n/a
V
Ta
Operating Temperature
-40
+85
C
Ts
Storage Temperature
-55
+125
C
RH
Relative Humidity
Non-Condensing
0
90%
%
MTBF
Mean Time Before Failure
Telcordia Issue 2
30°C, Ground benign, controlled
TBD
Hours
Electrical Characteristics
Table 3: Electrical Characteristics
Symbol
Parameter
Test Condition
Min
Max
Unit
P
Power Consumption
Vcc5 = 5.0V
3.5
W
Icc5
5V Input Supply Current
Active
700
mA
PCIe Bus
Differential Output Voltage
0.8
1.2
V
DC Differential TX Impedance
95.2
116.9
Ω
Differential Input Voltage
0.175
3.3
V
DC Differential RX Impedance
92.7
115.8
Ω
Electrical Idle Detect Threshold
61
173
mV
Excitation Output (Per Channel)
Output Frequency
0
10k
Hz
Output Voltage
7
VRMS
Output Current
100
mARMS
Reference Input
Frequency Range
0
10k
Hz
Voltage
JPx20, JPx21 (1-2)
4.5
14.0
VRMS
Voltage
JPx20, JPx21 (2-3)
30.0
99.0
VRMS
Channel Inputs
Frequency Range
0
10k
Hz
Voltage (Operating)
2V Configuration
1.7
2.3
VRMS
Voltage (Operating)
11.8V Configuration
10.0
13.4
VRMS
Voltage (Operating)
90V Configuration
76.5
103.5
VRMS
Voltage (Absolute Max)
2V Configuration
-5
+5
V
Voltage (Absolute Max)
11.8V Configuration
-30
+30
V
Voltage (Absolute Max)
90V Configuration
-225
+225
V

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3Board Connection
NOTE: It may be necessary to disable PCIe Active State Power Management
(ASPM) in the BIOS setup utility for correct operation. This is typically
in the “Advanced/PCI Express/Port #” menu. Contact your CPU
vendor for details.
Board Handling Precautions
To prevent damage due to Electrostatic Discharge (ESD), keep your board in its antistatic bag until you are ready to install it into your system.
When removing it from the bag, hold the board at the edges, and do not touch the components or connectors. Handle the board in an antistatic
environment, and use a grounded workbench for testing and handling of your hardware.

RTD Embedded Technologies, Inc. | www.rtd.com 11 ERES35105 User’s Manual
Physical Characteristics
STEP model is available upon request; contact RTD Tech Support for more information.
•Weight: Approximately 0.16 lbs. (72 g)
•Dimensions: 90.17 mm L x 95.89 mm W (3.550 in L x 3.775 in W)
•Stand-off Height: 0.600 inches (15.240 mm)
Figure 1: Board Dimensions

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Connectors and Jumpers
Figure 2: Board Connections
3.3.1 EXTERNAL I/O CONNECTORS
J1: Sensor Input / Output
The main connector for all of the I/O is J1. It includes the connections for the Synchro/Resolver/LVDT inputs, reference inputs, excitation
outputs, and some test signals. The pin assignments are shown in the Table below.
Table 4: J1 Input / Output Pin Assignments
Pin Name
#
#
Pin Name
GND
2
1
CH0_EXCITATION
GND
4
3
CH0_SINE+
GND
6
5
CH0_COSINE+
CH0_REF_IN-
8
7
CH0_REF_IN+
GND
10
9
CH1_EXCITATION
GND
12
11
CH1_SINE+
GND
14
13
CH1_COSINE+
CH1_REF_IN-
16
15
CH1_REF_IN+
CH1_VELOCITY
18
17
CH0_VELOCITY
CH0_S3
20
19
CH0_S1
CH0_S4
22
21
GND
CH0_S2_SYNCHRO
24
23
CH0_S2_RESOLVER
CH1_REF_IN+
24
25
CH0_REF_IN+
CH1_S3
28
27
CH1_S1
CH1_S4
30
29
GND
CH1_S2_SYNCHRO
32
31
CH1_S2_RESOLVER
GND
34
33
GND
CN1 & CN2: PCIe Connector
J1: Input / Output

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3.3.2 BUS CONNECTORS
CN1 (Top) & CN2 (Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express
Specification. (See PC/104 Specifications on page 37)
The ERES35105 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector.
3.3.3 JUMPERS
On all jumpers, pin 1 is designated by a thick white silkscreen line, and a square pad on the PCB. The jumpers are discussed in the following
sections of this manual.
The jumper settings are described in Section 6 starting on page 21.
Figure 3: Jumper Locations
JP116
JP115
JP117
JP119
JP121
JP118
JP120
JP114
JP111
JP112
JP110
JP113
JP216
JP215
JP217
JP219
JP221
JP218
JP220
JP214
JP211
JP212
JP210
JP213
JP121
JP122

RTD Embedded Technologies, Inc. | www.rtd.com 14 ERES35105 User’s Manual
Steps for Installing
NOTE: It may be necessary to disable PCIe Active State Power Management
(ASPM) in the BIOS setup utility for correct operation. This is typically
in the “Advanced/PCI Express/Port #” menu. Contact your CPU
vendor for details.
1. Always work at an ESD protected workstation, and wear a grounded wrist-strap.
2. Turn off power to the PC/104 system or stack.
3. Select and install stand-offs to properly position the module on the stack.
4. Remove the module from its anti-static bag.
5. Check that pins of the bus connector are properly positioned.
6. Check the stacking order; make sure all of the busses used by the peripheral cards are connected to the cpuModule.
7. Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack.
8. Gently and evenly press the module onto the PC/104 stack.
9. If any boards are to be stacked above this module, install them.
10. Attach any necessary cables to the PC/104 stack.
11. Re-connect the power cord and apply power to the stack.
12. Boot the system and verify that all of the hardware is working properly.
Figure 4: Example 104™Stack

RTD Embedded Technologies, Inc. | www.rtd.com 15 ERES35105 User’s Manual
4IDAN Connections
Module Handling Precautions
To prevent damage due to Electrostatic Discharge (ESD), keep your module in its antistatic bag until you are ready to install it into your system.
When removing it from the bag, hold the module by the aluminum enclosure, and do not touch the components or connectors. Handle the
module in an antistatic environment, and use a grounded workbench for testing and handling of your hardware.
Physical Characteristics
•Weight: Approximately 0.21 Kg (0.46 lbs.)
•Dimensions: 152.0 mm L x 130.0 mm W x 17.0 mm H (5.98 in L x 5.12 in W x 0.67 in H)
Figure 5: IDAN Dimensions

RTD Embedded Technologies, Inc. | www.rtd.com 16 ERES35105 User’s Manual
Connector Locations
The diagram below shows the connector locations for the headers of the ERES35105 as they are brought out on the front panels of the IDAN-
ERES35105HR-xS. For a full description of each connector on the ERES35105, refer to the External I/O Connectors section of this manual on
page 3.3.112.
Figure 6: IDAN Front Panel Connector Locations
Connectors
Table 5: IDAN-ERES35105HR-xS Panel Connectors and Mating Connectors
Board
Designator
Function
Connector
Description
IDAN Panel Connector
Mating Connector
J1
Sensor Input / Output
37-pin D (socket)
AMP / TE Connectivity
1658610-1
AMP / TE Connectivity
1658608-1
J1
eresModule
.00
.35 [9mm]
.00
2.56 [65mm]
Pin 1
Pin 21
Pin 37
Pin 19

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4.4.1 EXTERNAL I/O CONNECTORS
Sensor Input / Output
The IDAN connector includes the connections for the Synchro/Resolver/LVDT inputs, reference inputs, excitation outputs, and some test
signals. The pin assignments are shown in the Table below.
Table 6: IDAN Input / Output Pin Assignments
IDAN Pin #
Pin Name
J1 Pin #
1
CH0_EXCITATION
1
2
CH0_SINE+
3
3
CH0_COSINE+
5
4
CH0_REF_IN+
7
5
CH1_EXCITATION
9
6
CH1_SINE+
11
7
CH1_COSINE+
13
8
CH1_REF_IN+
15
9
CH0_VELOCITY
17
10
CH0_S1
19
11
GND
21
12
CH0_S2_RESOLVER
23
13
CH0_REF_IN+
25
14
CH1_S1
27
15
GND
29
16
CH1_S2_RESOLVER
31
17
GND
33
18
RESERVED
-
19
RESERVED
-
20
GND
2
21
GND
4
22
GND
6
23
CH0_REF_IN-
8
24
GND
10
25
GND
12
26
GND
14
27
CH1_REF_IN-
16
28
CH1_VELOCITY
18
29
CH0_S3
20
30
CH0_S4
22
31
CH0_S2_SYNCHRO
24
32
CH1_REF_IN+
26
33
CH1_S3
28
34
CH1_S4
30
35
CH1_S2_SYNCHRO
32
36
GND
34
37
RESERVED
-
4.4.2 BUS CONNECTORS
CN1 (Top) & CN2 (Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express
Specification. (See PC/104 Specifications on page 37)
The ERES35105 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector.

RTD Embedded Technologies, Inc. | www.rtd.com 18 ERES35105 User’s Manual
Steps for Installing
1. Always work at an ESD protected workstation, and wear a grounded wrist-strap.
2. Turn off power to the IDAN system.
3. Remove the module from its anti-static bag.
4. Check that pins of the bus connector are properly positioned.
5. Check the stacking order; make sure all of the busses used by the peripheral cards are connected to the cpuModule.
6. Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack.
7. Gently and evenly press the module onto the IDAN system.
8. If any boards are to be stacked above this module, install them.
9. Finish assembling the IDAN stack by installing screws of an appropriate length.
10. Attach any necessary cables to the IDAN system.
11. Re-connect the power cord and apply power to the stack.
12. Boot the system and verify that all of the hardware is working properly.
Figure 7: Example IDAN System

RTD Embedded Technologies, Inc. | www.rtd.com 19 ERES35105 User’s Manual
5Functional Description
Block Diagram
The Figure below shows the functional block diagram of the ERES35105. The various parts of the block diagram are discussed in the following
sections.
Figure 8: ERES35105 Block Diagram
PCIe Switch
The PCI Express Switch provides the bus interface to the ERES35105. The switch includes GPIO that are accessible from its Configuration
Space, which is configured as a generic bus. This is a low speed interface that does not provide support for interrupts or DMA.
The PCIe Switch also provides lane repopulation. One lane is used as the uplink to the CPU. On the opposite side of the board it is replaced
by a lane from the switch. This allows a virtually limitless number of boards to be added to the system.
Resolver to Digital Converter
The RD-19231 is a mixed signal CMOS IC containing analog input and digital output sections. Precision analog circuitry is merged with digital
logic to form a complete high-performance tracking resolver-to-digital converter. For user flexibility and convenience, the converter bandwidth,
dynamics, and velocity scaling are externally set with passive components.
The converter front-end consists of differential sine and cosine input amplifiers. The Control Transformer (CT) compares the analog input
signals with the digital output, resulting in an error signal proportional to the sine of the angular difference. The CT uses a combination of
amplifiers, switches, logic and capacitors in precision ratios to perform the calculation.
PCIe Switch
PCIe Bus
J1 I/O Connector
PCIe x1
Link
Repopulated PCIe x1
EPLD
RD19231
Resolver to Digital
Converter
RD19231
Resolver to Digital
Converter
Front
End
Front
End
On-Board
Excitation

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The converter accuracy is limited by the precision of the computing elements in the CT. Instead of a traditional precision resistor network, this
converter uses capacitors with precisely controlled ratios. Sampling techniques are used to eliminate errors due to voltage drift and op-amp
offsets.
The error processing is performed using the industry standard technique for Type II tracking converters. The DC error is integrated yielding a
velocity voltage which in turn drives a voltage controlled oscillator (VCO). This VCO is an incremental integrator (constant voltage input to
position rate output) which, together with the velocity integrator, forms a Type II servo feedback loop. A lead in the frequency response is
introduced to stabilize the loop and another lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and
above. The settings of the various error processor gains and break frequencies are done with external resistors and capacitors so that the
converter loop dynamics can be easily controlled.
5.3.1 BANDWIDTH FILTERS
The Resolver to Digital Converter circuit includes two selectable bandwidth filters. The filter characteristics are shown in the Table below. For
other bandwidth filter configurations, contact RTD Tech Support.
Table 7: Bandwidth Filters
Description
Filter
Channel
SHIFT
Maximum Excitation
Frequency
Resolution
Bandwidth
Maximum
Tracking Rate
High Resolution
1
1
10 kHz
16-bit (Synchro/Resolver)
14-bit (LVDT)
180 Hz
1200 rpm
High Velocity
2
0
10 kHz
12-bit (Synchro/Resolver)
10-bit (LVDT)
750 Hz
19200 rpm
Front End
The front end consists of a precision resistor pack that sets the input voltage range (2V, 11.8V, or 90V). It also includes the jumpers to
configure the board for different sensors.
Sensor signals must be converted to SIN and COS resolver signals that can be directly be interfaced by the Resolver-to-Digital converters. The
classical transformer coupled connection is often too cumbersome to use. The ERES35105 module uses an operational amplifier and precision
resistors to implement the Solid State Scott-T circuit. The most important design criteria in this connection are the perfect matching of the
resistors. Precision is maintained by using a special trimmed resistor network together with the op-amps. These resistor networks are available
for the three standard voltage levels of 2V, 11.8V and 90V. The resistor network value ratios are pre-trimmed to produce the 2VRMS input signal
required by the converters.
You may separately purchase resistor networks for the standard voltages from RTD. They may be easily configured channel-by-channel by
inserting the correct resistor network into the onboard sockets. The resistor networks are used as follows:
DDC-49530 are used with 11.8V inputs
DDC-49590 are used with 90V inputs
DDC-76037 are used with 2V inputs
On-Board Excitation
The on-board excitation can be used in certain applications to provide a reference to the sensors. It consists of a Programmable Waveform
Generator and two output amplifiers. Both channels must use the same excitation frequency, but the output levels can be individually adjusted.
EPLD
The EPLD provides glue logic between the PCIe interface and the on-board functions.