Qorvo Pac5526 User manual

Power Application Controller®

Rev 1.0 –Jan 17, 2020

PAC5526 Device User Guide

Power Application Controller®

Multi-Mode Power ManagerTM

Configurable Analog Front EndTM

Application Specific Power DriversTM

Arm®Cortex®-M4F Controller Core

 
 
Power Application Controller®
 
 -2- Copyright 2020 © Qorvo, Inc. 
 Rev 1.0 –Jan 17, 2020 
 
TABLE OF CONTENTS 
 
1OVERVIEW .......................................................................................................................12 
2STYLE AND FORMATTING CONVENTIONS....................................................................13 
2.1 Number Representation..............................................................................................13 
2.2 Formatting Styles........................................................................................................13 
3ARCHITECTURAL BLOCK DIAGRAM ..............................................................................14 
4ANALOG REGISTER ACCESS.........................................................................................15 
4.1 Overview.....................................................................................................................15 
4.2 Functional Description ................................................................................................15 
4.3 USART Configuration .................................................................................................16 
4.4 Protocol ......................................................................................................................16 
4.5 Write Register Example ..............................................................................................16 
4.6 Read Register Example..............................................................................................18 
5PAC5526 IO.......................................................................................................................19 
5.1 Overview.....................................................................................................................19 
5.2 ADC Channels............................................................................................................20 
5.3 Digital Peripheral Pins.................................................................................................21 
5.4 Analog Interrupts ........................................................................................................22 
6PAC5526 ADC MUXes ......................................................................................................23 
6.1 System Block Diagram................................................................................................23 
6.2 ADC MUX...................................................................................................................24 
6.3 AFE MUX....................................................................................................................25 
6.4 PWRMON MUX..........................................................................................................27 
7EMUX................................................................................................................................28 
8POWER MANAGER..........................................................................................................30 
8.1 Overview.....................................................................................................................30 
8.2 Features .....................................................................................................................30 
8.3 System Block Diagram................................................................................................31 
8.4 Functional Description ................................................................................................31 
8.5 VP Low Warning.........................................................................................................31 

 
 
Power Application Controller®
 
 -3- Copyright 2020 © Qorvo, Inc. 
 Rev 1.0 –Jan 17, 2020 
 
6 Power Manager Faults................................................................................................32 
7 Temperature Warnings and Faults..............................................................................32 
8 Register Summary......................................................................................................34 
9 Register Detail............................................................................................................35 
9.1 SOC.FAULT.........................................................................................................35 
9.2 SOC.STATUS......................................................................................................35 
9.3 SOC.MISC...........................................................................................................37 
9.4 SOC.PWRCTL.....................................................................................................38 
9.5 SOC.FAULTINTEN..............................................................................................39 
9.6 SOC.WATCHDOG...............................................................................................40 
9.7 SOC.SYSCONF...................................................................................................41 
9CONFIGURABLE ANALOG FRONT-END.........................................................................42 
1 Overview.....................................................................................................................42 
2 Features .....................................................................................................................42 
3 System Block Diagram................................................................................................43 
4 Enabling the CAFE .....................................................................................................44 
5 Entering Hibernate Mode............................................................................................44 
6 Hibernate wake-up using Wake-Up Timer...................................................................44 
7 Hibernate wake-up using Push-Button........................................................................44 
8 DAC output.................................................................................................................45 
9 VREF Output ..............................................................................................................45 
10 Hard Reset .................................................................................................................45 
11 General-Purpose Register ..........................................................................................45 
12 AIO10 .........................................................................................................................46 
12.1 System Block Diagram.........................................................................................46 
12.2 AIO1, AIO0 Digital I/O Mode................................................................................47 
12.3 AIO1, AIO0 Differential Amplifier Mode................................................................47 
12.4 AIO1, AIO0 ADC Sampling..................................................................................47 
12.5 AIO1, AIO0 Protection .........................................................................................48 
13 AIO32 .........................................................................................................................50 
13.1 System Block Diagram.........................................................................................50 
13.2 AIO3, AIO2 Digital I/O Mode................................................................................51 

 
 
Power Application Controller®
 
 -4- Copyright 2020 © Qorvo, Inc. 
 Rev 1.0 –Jan 17, 2020 
 
13.3 AIO3, AIO2 Differential Amplifier Mode................................................................51 
13.4 AIO3, AIO2 ADC Sampling..................................................................................51 
13.5 AIO3, AIO2 Protection .........................................................................................52 
13.6 AIO2/AIO7 Buffer.................................................................................................53 
14 AIO54 .........................................................................................................................54 
14.1 System Block Diagram.........................................................................................54 
14.2 AIO5, AIO4 Digital I/O Mode................................................................................55 
14.3 AIO4, AIO5 Differential Amplifier Mode................................................................55 
14.4 AIO5, AIO4 ADC Sampling..................................................................................55 
14.5 AIO5, AIO4 Protection .........................................................................................56 
15 AIO6...........................................................................................................................58 
15.1 System Block Diagram.........................................................................................59 
15.2 AIO6 Digital I/O Mode..........................................................................................60 
15.3 AIO6 Amplifier Mode............................................................................................60 
15.4 AIO6 Comparator Mode.......................................................................................60 
15.5 AIO6 Special Mode..............................................................................................61 
16 AIO7...........................................................................................................................62 
16.1 System Block Diagram.........................................................................................63 
16.2 AIO7 Digital I/O Mode..........................................................................................64 
16.3 AIO7 Amplifier Mode............................................................................................64 
16.4 AIO7 Comparator Mode.......................................................................................64 
16.5 AIO7 Special Mode..............................................................................................65 
16.6 AIO2/AIO7 Buffer.................................................................................................67 
17 AIO8...........................................................................................................................68 
17.1 System Block Diagram.........................................................................................69 
17.2 AIO8 Digital I/O Mode..........................................................................................70 
17.3 AIO8 Amplifier Mode............................................................................................70 
17.4 AIO8 Comparator Mode.......................................................................................70 
17.5 AIO8 Special Mode..............................................................................................71 
18 AIO9...........................................................................................................................73 
18.1 System Block Diagram.........................................................................................74 
18.2 AIO9 Digital I/O Mode..........................................................................................75 

 
 
Power Application Controller®
 
 -5- Copyright 2020 © Qorvo, Inc. 
 Rev 1.0 –Jan 17, 2020 
 
18.3 AIO9 Amplifier Mode............................................................................................75 
18.4 AIO9 Comparator Mode.......................................................................................75 
18.5 AIO9 Special Mode..............................................................................................76 
19 Register Summary......................................................................................................78 
20 Register Detail............................................................................................................80 
20.1 SOC.CFGAIO0....................................................................................................80 
20.2 SOC.CFGAIO1....................................................................................................81 
20.3 SOC.CFGAIO2....................................................................................................82 
20.4 SOC.CFGAIO3....................................................................................................83 
20.5 SOC.CFGAIO4....................................................................................................84 
20.6 SOC.CFGAIO5....................................................................................................85 
20.7 SOC.CFGAIO6....................................................................................................86 
20.8 SOC.CFGAIO7....................................................................................................87 
20.9 SOC.CFGAIO8....................................................................................................88 
20.10 SOC.CFGAIO9.................................................................................................89 
20.11 SOC.SIGSET...................................................................................................90 
20.12 SOC.HPDACH.................................................................................................91 
20.13 SOC.HPDACL..................................................................................................91 
20.14 SOC.LPDACH..................................................................................................91 
20.15 SOC.LPDACL ..................................................................................................91 
20.16 SOC.SHCFG1..................................................................................................92 
20.17 SOC.SHCFG2..................................................................................................93 
20.18 SOC.PROTINTEN............................................................................................94 
20.19 SOC.PROTSTAT .............................................................................................95 
20.20 SOC.DOUTSIG0..............................................................................................96 
20.21 SOC.DOUTSIG1..............................................................................................97 
20.22 SOC.DINSIG0..................................................................................................98 
20.23 SOC.DINSIG1..................................................................................................98 
20.24 SOC.CFGIO1...................................................................................................99 
20.25 SOC.SIGINTEN .............................................................................................100 
20.26 SOC.SIGINTF................................................................................................101 
20.27 SOC.BLANKING ............................................................................................102 

 
 
Power Application Controller®
 
 -6- Copyright 2020 © Qorvo, Inc. 
 Rev 1.0 –Jan 17, 2020 
 
20.29 SOC.SPECCFG0...........................................................................................103 
20.30 SOC.SPECCFG1...........................................................................................104 
20.31 SOC.SPECCFG2...........................................................................................106 
20.32 SOC.SPECCFG3...........................................................................................106 
20.33 SOC.GP0.......................................................................................................107 
APPLICATION SPECIFIC POWER DRIVER................................................................108 
1 Features ...................................................................................................................108 
2 System Block Diagram..............................................................................................109 
3 Functional Description ..............................................................................................110 
4 High-Side Gate Drivers.............................................................................................110 
5 Low-Side Gate Drivers..............................................................................................111 
6 Enabling the ASPD...................................................................................................112 
7 Gate Driver Safe State..............................................................................................112 
8 Driver Protection.......................................................................................................112 
9 Cycle by Cycle Current Limit.....................................................................................113 
10 Gate Driver Short Protection..................................................................................115 
11 VP UVLO Configuration.........................................................................................115 
12 Break-before-make Configuration..........................................................................115 
13 Gate Driver Programmable Current.......................................................................116 
14 Register Summary.................................................................................................120 
15 Register Detail.......................................................................................................121 
15.1 SOC.CFGDRV1.............................................................................................121 
15.2 SOC.CFGDRV2.............................................................................................122 
15.3 SOC.CFGDRV3.............................................................................................123 
15.4 SOC.STATDRV..............................................................................................124 
15.5 SOC.DRVILIMLS............................................................................................125 
15.6 SOC.DRVILIMHS...........................................................................................126 
15.7 SOC.CFGDRV4.............................................................................................127 
15.8 SOC.DRV_FLT ..............................................................................................127 
15.9 SOC.ENDRV..................................................................................................128 
15.10 SOC.WDTPASS.............................................................................................128 
LEGAL INFORMATION................................................................................................129 

Power Application Controller®

Rev 1.0 –Jan 17, 2020

 
 
Power Application Controller®
 
 -8- Copyright 2020 © Qorvo, Inc. 
 Rev 1.0 –Jan 17, 2020 
 
LIST OF FIGURES 
Figure 3-1 PAC5526 Architectural Block Diagram.....................................................................14 
Figure 4-1 PAC5526 Register Access.......................................................................................15 
Figure 4-2 Analog Peripheral Register Write Timing .................................................................17 
Figure 4-3 Analog Peripheral Register Read Timing .................................................................18 
Figure 5-1 GPIO and DPM Block Diagram................................................................................19 
Figure 6-1 PAC5526 ADC MUX inputs......................................................................................23 
Figure 7-1 EMUX Timing Diagram ............................................................................................29 
Figure 8-1 Power Manager System Block Diagram...................................................................31 
Figure 9-1 CAFE System Block Diagram ..................................................................................43 
Figure 9-2 AIO10 Block Diagram...............................................................................................46 
Figure 9-3 AIO32 Block Diagram...............................................................................................50 
Figure 9-4 AIO54 Block Diagram...............................................................................................54 
Figure 9-5 AIO6 System Block Diagram....................................................................................59 
Figure 9-6 AIO7 System Block Diagram....................................................................................63 
Figure 9-7 AIO8 System Block Diagram....................................................................................69 
Figure 9-8 AIO9 System Block Diagram....................................................................................74 
Figure 10-1 ASPD System Block Diagram..............................................................................109 
Figure 10-2 High-Side Gate Driver Block Diagram..................................................................110 
Figure 10-3 Low-Side Gate Driver Block Diagram...................................................................111 
Figure 10-4 Cycle by Cycle Current Limit................................................................................113 
Figure 10-5 High-side Gate Driver Waveforms........................................................................116 
Figure 10-6 Low-side Gate Driver Waveforms.........................................................................117 
 
 

Power Application Controller®

Rev 1.0 –Jan 17, 2020

LIST OF TABLES

Table 5-1 PAC5526 ADC Input Pins .........................................................................................20

Table 5-2 PAC5526 Digital Peripheral Pins...............................................................................21

Table 6-1 PAC5526 ADC MUX channels..................................................................................24

Table 6-2 PAC5526 ADC MUX channels..................................................................................26

Table 6-3 PAC5526 ADC MUX channels..................................................................................27

Table 8-1 Power Manager Fault Handling.................................................................................32

Table 8-2 Power Manager Register Summary...........................................................................34

Table 9-1 Hibernate Wake-Up Timer Options ...........................................................................44

Table 9-2 AIO2/AIO7 Buffer Input Select...................................................................................53

Table 9-3 AIO2/AIO7 Buffer Input Select...................................................................................67

Table 9-4 CAFE Register Summary..........................................................................................78

Table 10-1 ASPD Controlled-Current Time Configuration.......................................................118

Table 10-2 ASPD Controlled-Current Time Configuration.......................................................119

Table 10-3 ASPD Register Summary......................................................................................120

 
 
Power Application Controller®
 
 -10-Copyright 2020 © Qorvo, Inc. 
 Rev 1.0 –Jan 17, 2020 
 
LIST OF REGISTERS 
Register 8-1 SOC.FAULT (Fault Condition, 00h).......................................................................35 
Register 8-2 SOC.STATUS (System Status, 01h).....................................................................35 
Register 8-3 SOC.MISC (SOC Miscellaneous Configuration, 02h)............................................37 
Register 8-4 SOC.PWRCTL (Power Control, 03h)....................................................................38 
Register 8-5 SOC.FAULTINTEN (Fault interrupt enable, 04h) ..................................................39 
Register 8-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05h)......................................40 
Register 8-7 SOC.SYSCONF (System Configuration, 2Bh) ......................................................41 
Register 9-1 SOC.CFGAIO0 (AIO0 Configuration, 06h)............................................................80 
Register 9-2 SOC.CFGAIO1 (AIO1 Configuration, 07h)............................................................81 
Register 9-3 SOC.CFGAIO2 (AIO2 Configuration, 08h)............................................................82 
Register 9-4 SOC.CFGAIO3 (AIO3 Configuration, 09h)............................................................83 
Register 9-5 SOC.CFGAIO4 (AIO4 Configuration, 0Ah)............................................................84 
Register 9-6 SOC.CFGAIO5 (AIO5 Configuration, 0Bh)............................................................85 
Register 9-7 SOC.CFGAIO6 (AIO6 Configuration, 0Ch) ...........................................................86 
Register 9-8 SOC.CFGAIO7 (AIO7 Configuration, 0Dh) ...........................................................87 
Register 9-9 SOC.CFGAIO8 (AIO8 Configuration, 0Eh)............................................................88 
Register 9-10 SOC.CFGAIO9 (AIO9 Configuration, 0Fh)..........................................................89 
Register 9-11 SOC.SIGSET (Signal Manager Configuration, 10h)............................................90 
Register 9-12 SOC.HPDACH (HPDAC High Setting, 11h)........................................................91 
Register 9-13 SOC.HPDACL (HPDAC Low Setting, 12h) .........................................................91 
Register 9-14 SOC.LPDACH (LPDAC High Setting, 13h).........................................................91 
Register 9-15 SOC.LPDAC1 (LPDAC Low Setting, 14h)...........................................................91 
Register 9-16 SOC.SHCFG1 (Sample and Hold Configuration, 15h)........................................92 
Register 9-17 SOC.SHCFG2 (Sample and Hold Configuration 2, 16h).....................................93 
Register 9-18 SOC.PROTINTEN (Protection Interrupt Enable, 17h).........................................94 
Register 9-19 SOC.PROTSTAT (Protection Interrupt Status, 18h)............................................95 
Register 9-20 SOC.DOUTSIG0 (Digital Output 0, 19h).............................................................96 
Register 9-21 SOC.DOUTSIG1 (Digital Output 1,1Ah)..............................................................97 
Register 9-22 SOC.DINSIG0 (Digital Input 0, 1Bh) ...................................................................98 
Register 9-23 SOC.DINSIG1 (Digital Input 1, 1Ch)...................................................................98 
Register 9-24 SOC.CFGIO1 (AIO10-AIO13 Configuration 1, 1Dh)............................................99 
Register 9-25 SOC.SIGINTEN (AIO Interrupt Enable, 1Fh).....................................................100 
Register 9-26 SOC.SIGINTF (AIO Interrupt Flag, 20h)............................................................101 
Register 9-27 SOC.BLANKING (Comparator Blanking Configuration, 21h).............................102 
Register 9-28 SOC.SPECCFG0 (AIO7 Comparator Hysteresis Configuration, 22h) ...............103 
Register 9-29 SOC.SPECCFG1 (AIO8/9 Comparator Hysteresis Configuration, 23h).............104 
Register 9-30 SOC.SPECCFG2 (AIO7/8 Comparator MUX Input Configuration, 24h) ............106 
Register 9-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25h)...............106
Register 9-32 SOC.GP0 (General-Purpose Register Space, 26h)...........................................107 
Register 10-1 SOC.CFGDRV1 (Driver Configuration 1, 27h) ..................................................121 