Qorvo PAC5556 User manual

Power Application Controller®
-1- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
PAC5556 Device User Guide
Power Application Controller®
Configurable Analog Front EndTM
Application Specific Power DriversTM
Arm®Cortex®-M4F Controller Core

Power Application Controller®
-2- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
TABLE OF CONTENTS
1OVERVIEW .......................................................................................................................11
2STYLE AND FORMATTING CONVENTIONS....................................................................12
2.1 Number Representation..............................................................................................12
2.2 Formatting Styles........................................................................................................12
3ARCHITECTURAL BLOCK DIAGRAM ..............................................................................13
4INFO2 FLASH MEMORY MAP..........................................................................................14
5ANALOG REGISTER ACCESS.........................................................................................15
5.1 Overview.....................................................................................................................15
5.2 Functional Description ................................................................................................15
5.3 USART Configuration .................................................................................................16
5.4 Protocol ......................................................................................................................16
5.5 Write Register Example ..............................................................................................16
5.6 Read Register Example..............................................................................................17
6PAC5556 IO.......................................................................................................................18
6.1 Overview.....................................................................................................................18
6.2 ADC Channels............................................................................................................19
6.3 Digital Peripheral Pins.................................................................................................20
7PAC5556 ADC MUXes ......................................................................................................22
7.1 System Block Diagram................................................................................................22
7.2 ADC MUX...................................................................................................................23
7.3 AFE MUX....................................................................................................................23
7.4 PWRMON MUX..........................................................................................................25
8EMUX................................................................................................................................27
9CONFIGURABLE POWER MANAGER .............................................................................29
9.1 Features .....................................................................................................................29
9.2 System Block Diagram................................................................................................29
9.3 Functional Description ................................................................................................30
9.4 High-Voltage Buck (HV-BUCK)...................................................................................30
9.5 VP Low Warning.........................................................................................................30

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
9.6 Power Manager Faults................................................................................................31
9.7Temperature Warnings and Faults..............................................................................32
9.8 Register Summary......................................................................................................33
9.9 Register Detail............................................................................................................34
9.9.1 SOC.FAULT.........................................................................................................34
9.9.2 SOC.STATUS......................................................................................................35
9.9.3 SOC.MISC...........................................................................................................36
9.9.4 SOC.PWRCTL.....................................................................................................37
9.9.5 SOC.FAULTENABLE...........................................................................................38
9.9.6 SOC.WATCHDOG...............................................................................................39
9.9.7 SOC.SYSCONF...................................................................................................40
10 CONFIGURABLE ANALOG FRONT-END......................................................................41
10.1 Features .....................................................................................................................41
10.2 System Block Diagram................................................................................................42
10.3 Functional Description ................................................................................................43
10.4 Enabling the CAFE.....................................................................................................43
10.5 Entering Hibernate Mode............................................................................................43
10.6 Hibernate wake-up using the Wake-Up Timer.............................................................43
10.7 Hibernate wake-up using Push-Button........................................................................44
10.8 DAC Output ................................................................................................................44
10.9 VREF Output ..............................................................................................................44
10.10 AIO10......................................................................................................................46
10.10.1 System Block Diagram.....................................................................................47
10.10.2 AIO1, AIO0 Digital I/O Mode ............................................................................48
10.10.3 AIO1, AIO0 Differential Amplifier Mode ............................................................48
10.11 AIO32......................................................................................................................51
10.11.1 System Block Diagram.....................................................................................52
10.11.2 AIO3, AIO2 Digital I/O Mode ............................................................................53
10.11.3 AIO3, AIO2 Differential Amplifier Mode ............................................................53
10.12 AIO54......................................................................................................................56
10.12.1 System Block Diagram.....................................................................................57
10.12.2 AIO5, AIO4 Digital I/O Mode ............................................................................58

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
10.12.3 AIO4, AIO5 Differential Amplifier Mode ............................................................58
10.13 AIO6........................................................................................................................61
10.13.1 System Block Diagram.....................................................................................62
10.13.2 AIO6 Digital I/O Mode ......................................................................................63
10.13.3 AIO6 Amplifier Mode........................................................................................63
10.13.4 AIO6 Comparator Mode ...................................................................................63
10.13.5 AIO6 Special Mode ..........................................................................................64
10.14 AIO7........................................................................................................................65
10.14.1 System Block Diagram.....................................................................................66
10.14.2 AIO7 Digital I/O Mode ......................................................................................68
10.14.3 AIO7 Amplifier Mode........................................................................................68
10.14.4 AIO7 Comparator Mode ...................................................................................68
10.14.5 AIO7 Special Mode ..........................................................................................69
10.15 AIO8........................................................................................................................72
10.15.1 System Block Diagram.....................................................................................73
10.15.2 AIO8 Digital I/O Mode ......................................................................................74
10.15.3 AIO8 Amplifier Mode........................................................................................74
10.15.4 AIO8 Comparator Mode ...................................................................................74
10.15.5 Comparator Reference.....................................................................................74
10.15.6 AIO8 Special Mode ..........................................................................................75
10.16 AIO9........................................................................................................................78
10.16.1 System Block Diagram.....................................................................................79
10.16.2 AIO9 Digital I/O Mode ......................................................................................80
10.16.3 AIO9 Amplifier Mode........................................................................................80
10.16.4 AIO9 Special Mode ..........................................................................................82
10.17 Register Summary...................................................................................................84
10.18 Register Detail.........................................................................................................85
10.18.1 SOC.CFGAIO0.................................................................................................85
10.18.2 SOC.CFGAIO1.................................................................................................86
10.18.3 SOC.CFGAIO2.................................................................................................87
10.18.4 SOC.CFGAIO3.................................................................................................88
10.18.5 SOC.CFGAIO4.................................................................................................89

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
10.18.6 SOC.CFGAIO5.................................................................................................90
10.18.7 SOC.CFGAIO6.................................................................................................91
10.18.8 SOC.CFGAIO7.................................................................................................92
10.18.9 SOC.CFGAIO8.................................................................................................93
10.18.10 SOC.CFGAIO9.................................................................................................94
10.18.11 SOC.SIGSET...................................................................................................95
10.18.12 SOC.HPDACH.................................................................................................96
10.18.13 SOC.HPDACL..................................................................................................96
10.18.14 SOC.LPDACH..................................................................................................96
10.18.15 SOC.LPDACL ..................................................................................................96
10.18.16 SOC.SHCFG1..................................................................................................97
10.18.17 SOC.SHCFG2..................................................................................................98
10.18.18 SOC.PROTINTEN............................................................................................99
10.18.19 SOC.PROTSTAT ...........................................................................................100
10.18.20 SOC.DOUTSIG0............................................................................................101
10.18.21 SOC.DOUTSIG1............................................................................................101
10.18.22 SOC.DINSIG0................................................................................................102
10.18.23 SOC.DINSIG1................................................................................................102
10.18.24 SOC.CFGIO1.................................................................................................103
10.18.25 SOC.SIGINTEN .............................................................................................104
10.18.26 SOC.SIGINTF................................................................................................105
10.18.27 SOC.BLANKING ............................................................................................106
10.18.29 SOC.SPECCFG0...........................................................................................107
10.18.30 SOC.SPECCFG1...........................................................................................108
10.18.31 SOC.SPECCFG2...........................................................................................109
10.18.32 SOC.SPECCFG3...........................................................................................110
11 APPLICATION SPECIFIC POWER DRIVER................................................................111
11.1 Features ...................................................................................................................111
11.2 System Block Diagram..............................................................................................112
11.3 Functional Description ..............................................................................................113
11.4 High-Side Gate Drivers.............................................................................................113
11.5 Low-Side Gate Drivers..............................................................................................114

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Rev 2.2 –Nov 25, 2020
11.6 Enabling the ASPD...................................................................................................115
11.7 Driver Protection.......................................................................................................115
11.8 Cycle by Cycle Current Limit.....................................................................................116
11.9 Boot-strap Pre-Charge..............................................................................................118
11.10 Low-side Gate Driver Short Protection ..................................................................118
11.11 VP UVLO Configuration.........................................................................................118
11.12 Register Summary.................................................................................................119
11.13 Register Detail.......................................................................................................120
11.13.1 SOC.CFGDRV1.............................................................................................120
11.13.2 SOC.CFGDRV2.............................................................................................121
11.13.3 SOC.CFGDRV3.............................................................................................122
11.13.4 SOC.STATDRV..............................................................................................123
11.13.5 SOC.CFGDRV4.............................................................................................124
11.13.6 SOC.DRV_FLT ..............................................................................................124
11.13.7 SOC.ENDRV..................................................................................................124
11.13.8 SOC.WDTPASS.............................................................................................125
12 LEGAL INFORMATION................................................................................................126

Power Application Controller®
-7- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
LIST OF FIGURES
Figure 3-1 PAC5556 Architectural Block Diagram.....................................................................13
Figure 5-1 PAC5556 Register Access.......................................................................................15
Figure 5-2 Analog Peripheral Register Write Timing .................................................................17
Figure 5-3 Analog Peripheral Register Read Timing .................................................................17
Figure 6-1 GPIO and DPM Block Diagram................................................................................18
Figure 7-1 PAC5556 ADC MUX inputs......................................................................................22
Figure 8-1 EMUX Timing Diagram ............................................................................................28
Figure 9-1 CPM System Block Diagram....................................................................................29
Figure 10-1 CAFE System Block Diagram ................................................................................42
Figure 10-2 AIO10 Block Diagram.............................................................................................47
Figure 10-3 AIO32 Block Diagram.............................................................................................52
Figure 10-4 AIO54 Block Diagram.............................................................................................57
Figure 10-5 AIO6 System Block Diagram..................................................................................62
Figure 10-6 AIO7 System Block Diagram..................................................................................66
Figure 10-7 AIO8 System Block Diagram..................................................................................73
Figure 10-8 AIO9 System Block Diagram..................................................................................79
Figure 11-1 ASPD System Block Diagram..............................................................................112
Figure 11-2 ASPD High-Side Gate Drivers..............................................................................113
Figure 11-3 ASPD Low-Side Gate Drivers ..............................................................................114
Figure 11-3 Cycle by Cycle Current Limit................................................................................116

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
LIST OF TABLES
Table 6-1 PAC5556 ADC Input Pins .........................................................................................19
Table 6-2 PAC5556 Digital Peripheral Pins...............................................................................20
Table 7-1 PAC5556 ADC MUX channels..................................................................................23
Table 7-2 PAC5556 ADC MUX channels..................................................................................25
Table 7-3 PAC5556 ADC MUX channels..................................................................................26
Table 9-1 CPM Register Summary............................................................................................33
Table 10-1 CAFE Register Summary........................................................................................84
Table 11-1 ASPD Register Summary......................................................................................119

Power Application Controller®
-9- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
LIST OF REGISTERS
Register 9-1 SOC.FAULT (Fault Condition, 00h).......................................................................34
Register 9-2 SOC.STATUS (System Status, 01h).....................................................................35
Register 9-3 SOC.MISC (SOC Miscellaneous Configuration, 02h)............................................36
Register 9-4 SOC.PWRCTL (Power Control, 03h)....................................................................37
Register 9-5 SOC.FAULTENABLE (Fault mask, 04h)...............................................................38
Register 9-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05h)......................................39
Register 9-7 SOC.SYSCONF (System Configuration, 2Bh) ......................................................40
Register 10-1 SOC.CFGAIO0 (AIO0 Configuration, 06h)..........................................................85
Register 10-2 SOC.CFGAIO1 (AIO1 Configuration, 07h)..........................................................86
Register 10-3 SOC.CFGAIO2 (AIO2 Configuration, 08h)..........................................................87
Register 10-4 SOC.CFGAIO3 (AIO3 Configuration, 09h)..........................................................88
Register 10-5 SOC.CFGAIO4 (AIO4 Configuration, 0Ah)..........................................................89
Register 10-6 SOC.CFGAIO5 (AIO5 Configuration, 0Bh)..........................................................90
Register 10-7 SOC.CFGAIO6 (AIO6 Configuration, 0Ch) .........................................................91
Register 10-8 SOC.CFGAIO7 (AIO7 Configuration, 0Dh) .........................................................92
Register 10-9 SOC.CFGAIO8 (AIO8 Configuration, 0Eh)..........................................................93
Register 10-10 SOC.CFGAIO9 (AIO9 Configuration, 0Fh)........................................................94
Register 10-11 SOC.SIGSET (Signal Manager Configuration, 10h)..........................................95
Register 10-12 SOC.HPDACH (HPDAC High Setting, 11h)......................................................96
Register 10-13 SOC.HPDACL (HPDAC Low Setting, 12h) .......................................................96
Register 10-14 SOC.LPDACH (LPDAC High Setting, 13h) .......................................................96
Register 10-15 SOC.LPDAC1 (LPDAC Low Setting, 14h).........................................................96
Register 10-16 SOC.SHCFG1 (Sample and Hold Configuration, 15h)......................................97
Register 10-17 SOC.SHCFG2 (Sample and Hold Configuration 2, 16h)...................................98
Register 10-18 SOC.PROTINTEN (Protection Interrupt Enable, 17h) .......................................99
Register 10-19 SOC.PROTSTAT (Protection Interrupt Status, 18h)........................................100
Register 10-20 SOC.DOUTSIG0 (Digital Output 0, 19h).........................................................101
Register 10-21 SOC.DOUTSIG1 (Digital Output 1,1Ah)..........................................................101
Register 10-22 SOC.DINSIG0 (Digital Input 0, 1Bh) ...............................................................102
Register 10-23 SOC.DINSIG1 (Digital Input 1, 1Ch)...............................................................102
Register 10-24 SOC.CFGIO1 (AIO10-AIO13 Configuration 1, 1Dh)........................................103
Register 10-25 SOC.SIGINTEN (AIO Interrupt Enable Configuration, 1Fh).............................104
Register 10-26 SOC.SIGINTF (AIO Interrupt Flag, 20h)..........................................................105
Register 10-27 SOC.BLANKING (Comparator Blanking Configuration, 21h)...........................106
Register 10-28 SOC.SPECCFG0 (AIO7 Comparator Hysteresis Configuration, 22h)..............107
Register 10-29 SOC.SPECCFG1 (AIO8/9 Comparator Hysteresis Configuration, 23h)...........108
Register 10-30 SOC.SPECCFG2 (AIO7/8 Comparator MUX Input Configuration, 24h) ..........109
Register 10-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25h) .............110
Register 11-1 SOC.CFGDRV1 (Driver Configuration 1, 27h) ..................................................120
Register 11-2 SOC.CFGDRV2 (Driver Configuration 2, 28h) ..................................................121
Register 11-3 SOC.CFGDRV3 (Driver Configuration 3, 29h) ..................................................122

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
Register 11-4 SOC.STATDRV (Driver Status, 2Ah) ................................................................123
Register 11-5 SOC.CFGDRV4 (Driver Configuration 4, 7Bh)..................................................124
Register 11-6 SOC.DRV_FLT (Driver Fault Flag, 7Ch)...........................................................124
Register 11-7 SOC.ENDRV (Driver Manager Enable, 7Dh) ....................................................124
Register 11-8 SOC.WDTPASS (WDT Password, 7Eh)...........................................................125

Power Application Controller®
-11- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
1 OVERVIEW
This document is the PAC5556 Device User Guide. It details the operation of the analog
peripherals in the PAC5556.
For detailed information on the MCU and Digital Peripherals in the PAC5556, see the PAC55XX
Family User Guide.

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
2 STYLE AND FORMATTING CONVENTIONS
This chapter describes the formatting and styles used throughout this document.
2.1 Number Representation
Numbers other than decimal will have a postfix indicator. All numbers use little endian
formatting, with the most significant bit/digit to the left. Digits for binary and hexadecimal
representation are grouped with a single space every four digits to improve readability. Binary
numbers use “b” as a postfix and hexadecimal numbers use “h” as a postfix.
For example, 1011b binary = Bh hexadecimal = 11 decimal.
2.2 Formatting Styles
TYPE
EXAMPLE
DESCRIPTION
Register Name
RTCCTL
Register names use a capital letter and boldface type.
Register Bit(s)
RTCCTL.RTCCLKDIV
Register bits are always represented with the register name
separated with a period.
Function selected by
register bit(s)
[RTCCTL.RTCCLKDIV]
Within text blocks, functions selected with a register bit setting are
set in brackets. For example [RTCCTL.RTCCLKDIV] means divider
settings /2 to /65536.
Pin Function
PA5
Pin functions use capital letters
Internal signals
PWMA3
Internal signals use italicized font.
Formulas
CLK = FCLK / DIV
Formulas use monospaced text.
Links
Link
Hyperlinks are underlined and blue.
CPU Mnemonic
MRS
CPU Mnemonic uses monospaced text.
Operands
{Rd, }, Rn, Rm
Operands use monospaced italic text.
Code examples
b loopA
Code examples use monospaced text.

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
3 ARCHITECTURAL BLOCK DIAGRAM
For Below is an architecture block diagram of the PAC5556 device.
Figure 3-1 PAC5556 Architectural Block Diagram
IO
128kB FLASH
32kB SRAM
CLOCK
CONTROL
RTC/Calendar
GPIO
USART (3)
I2C
CAN
SYSTEM
CONTROL
APB/AHB
PAC5556
Power Application Controller
PX.Y
DEBUG/
ETM
ARM
CORTEX-M4F
CORE
TIMERS (4)
DEAD TIME
(16)
PWM/CC (32)
PWM ENGINE
PX.Y
PX.Y
PX.Y
PX.Y
PX.Y
BRIDGE
WWDT
DTSE
DATA ACQUISITION
AND SEQUENCER
12-BIT
ADC
MUX
PAC SOC BUS
3 x 1kB FLASH
CONFIGURABLE
POWER MANAGER
HIGH-
VOLTAGE
CONTROLLER
(HV-BUCK)
LINEAR
REGULATORS
VSS
SW
MEDIUM-
VOLTAGE
REGULATOR
(MV-BUCK) VSYS
VCCIO
VCORE
VCC33
DXBx
DXHx
DXSx
HSGD (3)
DRLx
LSGD (3)
APPLICATION
SPECIFIC
POWER
DRIVERS
CONFIGURABLE
ANALOG
FRONT-END
AIO
CONTROL
(10)
DAC (2)
PGA/
CMP (4 )
DIFF-PGA
PCMP (3)
AMPx/
CMPx/
PHCx
DAxP/
PCMPx
DAxN
ADx/PCx
AIOx
BUF6
PBTN
BST_CHG
SRC
DRM
CSM
VM
BST
VP
VCC18
GP TIMER (2)
CRC

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
4 INFO2 FLASH MEMORY MAP

Power Application Controller®
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5 ANALOG REGISTER ACCESS
5.1 Overview
All analog registers in the PAC5556 are accessible through a SOC bus in the device. Unlike
registers in the MCU (SRAM and digital peripheral registers), these analog registers are not
memory mapped.
The block diagram below shows the different system busses that the MCU uses to access the
different system registers.
Figure 5-1 PAC5556 Register Access
SWD
Cortex-M4F
MCU
PAC5556
Debug
Port AHB/APB
Bridge Analog
Peripherals
GPIOAUSARTA
Memory
Controller
JTAG
AHB APB
Other
Digital
Peripherals
DPM
GPIO[A..G]
The PAC5556 contains two register buses: the AHB bus and the APB bus.
The AHB bus allows the MCU and Debug Port access to FLASH and SRAM via the Memory
Controller. To access other digital peripheral connected to the APB bus, there is a bridge from
the AHB to the APB bus so that the MCU or Debug Port can perform memory-mapped register
access to all digital peripherals. Some digital peripherals such as timers are flexibly connected
to IO using the DPM bus.
To access the Analog peripherals, the USARTA SPI peripheral is used to generate read and
write transactions to the Analog registers using the DPM and GPIOA.
5.2 Functional Description
External programming interfaces such as JTAG and SWD or the Arm®Cortex®-M4F MCU may
perform memory-mapped accesses to USART A through the AHB and APB busses on the
device.
USART A is a serial communication peripheral that supports a SPI-like protocol that can be
used to communicate to the Analog Peripherals for read and write transactions. The Digital

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
Peripheral MUX (DPM) may be configured to connect the USART A SPI signals to GPIO A,
where they are connected to the Analog peripherals.
5.3 USART Configuration
USART A acts as a SPI bus master to communicate with the Analog Peripherals. The USART A
signals that are used for this communication are:
▪USASCLK –USART A SPI Clock
▪USAMOSI –USART A Master-Out/Slave-In
▪USAMISO –USART A Master-In/Slave-Out
▪USASS –USART A Slave Select
In order to communicate with the Analog Peripherals, the USART A should have the following
configuration:
▪8-bit mode
▪SCLK active high
▪CPH is sample/setup
▪SS active low
When communicating with the Analog Peripherals, the maximum SCLK frequency is 25MHz.
5.4 Protocol
The protocol for communicating with the Analog Peripherals is a simple two-byte protocol.
The first byte is always the address, which includes a 7-bit address [7:1] and a write bit [0]. For
write operations, the write bit [0] is set to 1b. For read operations, the write bit [0] is set to 0b.
For write operations, the 2nd byte will be the 8-bit data to write to the given address.
For read operations, the 2nd byte is ignored and MISO will contain the 8-bit data read from the
given address.
5.5 Write Register Example
To write the HPDACH register (address 11h) with the value 28h, issue the following
transactions to USART A:
▪Write SSPADAT with the value 23h (11h << 1 | 1b for write transaction)
▪Write SSPADAT with the value 28h
The timing diagram from a write operation is shown below.

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Figure 5-2 Analog Peripheral Register Write Timing
5.6 Read Register Example
To read the contents of the HPDACH register, issue the following transactions to USART A:
▪Write SSPADAT with the value 22h (11h << 1 | 0b for read transaction)
▪Write SSPADAT with a dummy character
▪Read last data from MISO from SSPADAT, this is the register value
The timing diagram from a read operation is shown below.
Figure 5-3 Analog Peripheral Register Read Timing
For more information on how to configure the DPM to support the USART A peripheral for
communicating with the Analog Registers, see the PAC55XX Family User Guide.

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
6 PAC5556 IO
6.1 Overview
The Digital Peripheral MUX (DPM) on the PAC55XX family allows flexible assignment of
peripheral functions to IO pins.
Each member of the family has a different set of IO pins that are available. It is important during
application design that the designer consider the available IO pins to make sure the necessary
peripherals will be available.
Below is a diagram of the GPIO and MUX structure.
Figure 6-1 GPIO and DPM Block Diagram
Each IO can be configured to select 1 of up to 8 digital peripheral signals. Some IOs also may
be used as an ADC input. For information on how to configure the IO for each of these
situations, see the PAC55XX Family User Guide.
The PAC5556 has the following IO pins available for application use:
▪PA[7:0], PC[6:4] –Reserved for MMPM, ASPD, CAFE
▪PB[2:0] –Reserved for ASPD
▪PE[7:0]
▪PF[7:0]

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Rev 2.2 –Nov 25, 2020
6.2 ADC Channels
The ADC channels that are available on the PAC5556 are shown in the table below.
Table 6-1 PAC5556 ADC Input Pins
ADC Channel
IO PIN
ADC0
PG71
ADC4
PF4
ADC5
PF5
ADC6
PF6
ADC7
PF7
1
Available for sampling channels in the CAFE only

Power Application Controller®
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Rev 2.2 –Nov 25, 2020
6.3 Digital Peripheral Pins
The digital peripheral functions that are available in the PAC5556 are shown below.
Table 6-2 PAC5556 Digital Peripheral Pins
PORT
Pin
GPIOxMUXS.Py
000b
001b
010b
011b
100b
101b
110b
111b
GPIOA
P0
GPIOA0
P1
GPIOA1
EMUXD
P2
GPIOA2
EMUXC
P3
GPIOA3
USASCLK
USBSCLK
P4
GPIOA4
USAMOSI
USBMOSI
P5
GPIOA5
USAMISO
USBMISO
P6
GPIOA6
USASS
USBSS
P7
GPIOA7
GPIOB
P0
GPIOB0
TAPWM0
TBPWM0
P1
GPIOB1
TAPWM1
TBPWM1
P2
GPIOB2
TAPWM2
TBPWM2
P4
GPIOB4
TAPWM4
TBPWM4
P5
GPIOB5
TAPWM5
TBPWM5
P6
GPIOB6
TAPWM6
TBPWM6
GPIOC
P4
GPIOC4
TBPWM4
TCPWM4
TCQEPIDX
USBMOSI
USCSCLK
CANRXD
I2CSCL
P5
GPIOC5
TBPWM5
TCPWM5
TCQEPPHA
USBMISO
USCSS
CANTXD
I2CSDA
P6
GPIOC6
TBPWM6
TCPWM6
TCQEPPHB
USBSCLK
USCMOSI
EMUXD
GPIOE
P0
GPIOE0
TCPWM4
TDPWM0
TAIDX
TBIDX
USCSCLK
I2CSCL
EMUXC
P1
GPIOE1
TCPWM5
TDPWM1
TAPHA
TBPHA
USCSS
I2CSDA
EMUXD
P2
GPIOE2
TCPWM6
TDPWM2
TAPHB
TBPHB
USCMOSI
CANRXD
EXTCLK
P3
GPIOE3
TCPWM7
TDPWM3
FRCLK
USCMISO
CANTXD
P4
GPIOE4
TCPWM4
TDPWM4
TDQEPIDX
USBSCLK
USDMOSI
I2CSCL
P5
GPIOE5
TCPWM5
TDPWM5
TDQEPPHA
USBSS
USDMISO
I2CSDA
P6
GPIOE6
TCPWM6
TDPWM6
TDQEPPHB
USBMOSI
USDSCLK
CANRXD
P7
GPIOE7
TCPWM7
TDPWM7
USBMISO
USDSS
CANTXD
GPIOF
P0
GPIOF0
TCPWM0
TDPWM0
TMS/SWDCLK
TBIDX
USBSCLK
TRACECLK
P1
GPIOF1
TCPWM1
TDPWM1
TMS/SWDIO
TBPHA
USBSS
TRACED0
P2
GPIOF2
TCPWM2
TDPWM2
TDI
TBPHB
USBMOSI
TRACED1
P3
GPIOF3
TCPWM3
TDPWM3
TDO
FRCLK
USBMISO
TRACED2
P4
GPIOF4
TCPWM4
TDPWM4
TCIDX
USDSCLK
TRACED3
EMUXC