Qorvo PAC5556 User manual

Power Application Controller®
-1- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
PAC5556 Device User Guide
Power Application Controller®
Configurable Analog Front EndTM
Application Specific Power DriversTM
Arm®Cortex®-M4F Controller Core

Power Application Controller®
-2- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
TABLE OF CONTENTS
1OVERVIEW .......................................................................................................................11
2STYLE AND FORMATTING CONVENTIONS....................................................................12
2.1 Number Representation..............................................................................................12
2.2 Formatting Styles........................................................................................................12
3ARCHITECTURAL BLOCK DIAGRAM ..............................................................................13
4INFO2 FLASH MEMORY MAP..........................................................................................14
5ANALOG REGISTER ACCESS.........................................................................................15
5.1 Overview.....................................................................................................................15
5.2 Functional Description ................................................................................................15
5.3 USART Configuration .................................................................................................16
5.4 Protocol ......................................................................................................................16
5.5 Write Register Example ..............................................................................................16
5.6 Read Register Example..............................................................................................17
6PAC5556 IO.......................................................................................................................18
6.1 Overview.....................................................................................................................18
6.2 ADC Channels............................................................................................................19
6.3 Digital Peripheral Pins.................................................................................................20
7PAC5556 ADC MUXes ......................................................................................................22
7.1 System Block Diagram................................................................................................22
7.2 ADC MUX...................................................................................................................23
7.3 AFE MUX....................................................................................................................23
7.4 PWRMON MUX..........................................................................................................25
8EMUX................................................................................................................................27
9CONFIGURABLE POWER MANAGER .............................................................................29
9.1 Features .....................................................................................................................29
9.2 System Block Diagram................................................................................................29
9.3 Functional Description ................................................................................................30
9.4 High-Voltage Buck (HV-BUCK)...................................................................................30
9.5 VP Low Warning.........................................................................................................30

Power Application Controller®
-3- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
9.6 Power Manager Faults................................................................................................31
9.7Temperature Warnings and Faults..............................................................................32
9.8 Register Summary......................................................................................................33
9.9 Register Detail............................................................................................................34
9.9.1 SOC.FAULT.........................................................................................................34
9.9.2 SOC.STATUS......................................................................................................35
9.9.3 SOC.MISC...........................................................................................................36
9.9.4 SOC.PWRCTL.....................................................................................................37
9.9.5 SOC.FAULTENABLE...........................................................................................38
9.9.6 SOC.WATCHDOG...............................................................................................39
9.9.7 SOC.SYSCONF...................................................................................................40
10 CONFIGURABLE ANALOG FRONT-END......................................................................41
10.1 Features .....................................................................................................................41
10.2 System Block Diagram................................................................................................42
10.3 Functional Description ................................................................................................43
10.4 Enabling the CAFE.....................................................................................................43
10.5 Entering Hibernate Mode............................................................................................43
10.6 Hibernate wake-up using the Wake-Up Timer.............................................................43
10.7 Hibernate wake-up using Push-Button........................................................................44
10.8 DAC Output ................................................................................................................44
10.9 VREF Output ..............................................................................................................44
10.10 AIO10......................................................................................................................46
10.10.1 System Block Diagram.....................................................................................47
10.10.2 AIO1, AIO0 Digital I/O Mode ............................................................................48
10.10.3 AIO1, AIO0 Differential Amplifier Mode ............................................................48
10.11 AIO32......................................................................................................................51
10.11.1 System Block Diagram.....................................................................................52
10.11.2 AIO3, AIO2 Digital I/O Mode ............................................................................53
10.11.3 AIO3, AIO2 Differential Amplifier Mode ............................................................53
10.12 AIO54......................................................................................................................56
10.12.1 System Block Diagram.....................................................................................57
10.12.2 AIO5, AIO4 Digital I/O Mode ............................................................................58

Power Application Controller®
-4- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
10.12.3 AIO4, AIO5 Differential Amplifier Mode ............................................................58
10.13 AIO6........................................................................................................................61
10.13.1 System Block Diagram.....................................................................................62
10.13.2 AIO6 Digital I/O Mode ......................................................................................63
10.13.3 AIO6 Amplifier Mode........................................................................................63
10.13.4 AIO6 Comparator Mode ...................................................................................63
10.13.5 AIO6 Special Mode ..........................................................................................64
10.14 AIO7........................................................................................................................65
10.14.1 System Block Diagram.....................................................................................66
10.14.2 AIO7 Digital I/O Mode ......................................................................................68
10.14.3 AIO7 Amplifier Mode........................................................................................68
10.14.4 AIO7 Comparator Mode ...................................................................................68
10.14.5 AIO7 Special Mode ..........................................................................................69
10.15 AIO8........................................................................................................................72
10.15.1 System Block Diagram.....................................................................................73
10.15.2 AIO8 Digital I/O Mode ......................................................................................74
10.15.3 AIO8 Amplifier Mode........................................................................................74
10.15.4 AIO8 Comparator Mode ...................................................................................74
10.15.5 Comparator Reference.....................................................................................74
10.15.6 AIO8 Special Mode ..........................................................................................75
10.16 AIO9........................................................................................................................78
10.16.1 System Block Diagram.....................................................................................79
10.16.2 AIO9 Digital I/O Mode ......................................................................................80
10.16.3 AIO9 Amplifier Mode........................................................................................80
10.16.4 AIO9 Special Mode ..........................................................................................82
10.17 Register Summary...................................................................................................84
10.18 Register Detail.........................................................................................................85
10.18.1 SOC.CFGAIO0.................................................................................................85
10.18.2 SOC.CFGAIO1.................................................................................................86
10.18.3 SOC.CFGAIO2.................................................................................................87
10.18.4 SOC.CFGAIO3.................................................................................................88
10.18.5 SOC.CFGAIO4.................................................................................................89

Power Application Controller®
-5- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
10.18.6 SOC.CFGAIO5.................................................................................................90
10.18.7 SOC.CFGAIO6.................................................................................................91
10.18.8 SOC.CFGAIO7.................................................................................................92
10.18.9 SOC.CFGAIO8.................................................................................................93
10.18.10 SOC.CFGAIO9.................................................................................................94
10.18.11 SOC.SIGSET...................................................................................................95
10.18.12 SOC.HPDACH.................................................................................................96
10.18.13 SOC.HPDACL..................................................................................................96
10.18.14 SOC.LPDACH..................................................................................................96
10.18.15 SOC.LPDACL ..................................................................................................96
10.18.16 SOC.SHCFG1..................................................................................................97
10.18.17 SOC.SHCFG2..................................................................................................98
10.18.18 SOC.PROTINTEN............................................................................................99
10.18.19 SOC.PROTSTAT ...........................................................................................100
10.18.20 SOC.DOUTSIG0............................................................................................101
10.18.21 SOC.DOUTSIG1............................................................................................101
10.18.22 SOC.DINSIG0................................................................................................102
10.18.23 SOC.DINSIG1................................................................................................102
10.18.24 SOC.CFGIO1.................................................................................................103
10.18.25 SOC.SIGINTEN .............................................................................................104
10.18.26 SOC.SIGINTF................................................................................................105
10.18.27 SOC.BLANKING ............................................................................................106
10.18.29 SOC.SPECCFG0...........................................................................................107
10.18.30 SOC.SPECCFG1...........................................................................................108
10.18.31 SOC.SPECCFG2...........................................................................................109
10.18.32 SOC.SPECCFG3...........................................................................................110
11 APPLICATION SPECIFIC POWER DRIVER................................................................111
11.1 Features ...................................................................................................................111
11.2 System Block Diagram..............................................................................................112
11.3 Functional Description ..............................................................................................113
11.4 High-Side Gate Drivers.............................................................................................113
11.5 Low-Side Gate Drivers..............................................................................................114

Power Application Controller®
-6- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
11.6 Enabling the ASPD...................................................................................................115
11.7 Driver Protection.......................................................................................................115
11.8 Cycle by Cycle Current Limit.....................................................................................116
11.9 Boot-strap Pre-Charge..............................................................................................118
11.10 Low-side Gate Driver Short Protection ..................................................................118
11.11 VP UVLO Configuration.........................................................................................118
11.12 Register Summary.................................................................................................119
11.13 Register Detail.......................................................................................................120
11.13.1 SOC.CFGDRV1.............................................................................................120
11.13.2 SOC.CFGDRV2.............................................................................................121
11.13.3 SOC.CFGDRV3.............................................................................................122
11.13.4 SOC.STATDRV..............................................................................................123
11.13.5 SOC.CFGDRV4.............................................................................................124
11.13.6 SOC.DRV_FLT ..............................................................................................124
11.13.7 SOC.ENDRV..................................................................................................124
11.13.8 SOC.WDTPASS.............................................................................................125
12 LEGAL INFORMATION................................................................................................126

Power Application Controller®
-7- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
LIST OF FIGURES
Figure 3-1 PAC5556 Architectural Block Diagram.....................................................................13
Figure 5-1 PAC5556 Register Access.......................................................................................15
Figure 5-2 Analog Peripheral Register Write Timing .................................................................17
Figure 5-3 Analog Peripheral Register Read Timing .................................................................17
Figure 6-1 GPIO and DPM Block Diagram................................................................................18
Figure 7-1 PAC5556 ADC MUX inputs......................................................................................22
Figure 8-1 EMUX Timing Diagram ............................................................................................28
Figure 9-1 CPM System Block Diagram....................................................................................29
Figure 10-1 CAFE System Block Diagram ................................................................................42
Figure 10-2 AIO10 Block Diagram.............................................................................................47
Figure 10-3 AIO32 Block Diagram.............................................................................................52
Figure 10-4 AIO54 Block Diagram.............................................................................................57
Figure 10-5 AIO6 System Block Diagram..................................................................................62
Figure 10-6 AIO7 System Block Diagram..................................................................................66
Figure 10-7 AIO8 System Block Diagram..................................................................................73
Figure 10-8 AIO9 System Block Diagram..................................................................................79
Figure 11-1 ASPD System Block Diagram..............................................................................112
Figure 11-2 ASPD High-Side Gate Drivers..............................................................................113
Figure 11-3 ASPD Low-Side Gate Drivers ..............................................................................114
Figure 11-3 Cycle by Cycle Current Limit................................................................................116

Power Application Controller®
-8- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
LIST OF TABLES
Table 6-1 PAC5556 ADC Input Pins .........................................................................................19
Table 6-2 PAC5556 Digital Peripheral Pins...............................................................................20
Table 7-1 PAC5556 ADC MUX channels..................................................................................23
Table 7-2 PAC5556 ADC MUX channels..................................................................................25
Table 7-3 PAC5556 ADC MUX channels..................................................................................26
Table 9-1 CPM Register Summary............................................................................................33
Table 10-1 CAFE Register Summary........................................................................................84
Table 11-1 ASPD Register Summary......................................................................................119

Power Application Controller®
-9- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
LIST OF REGISTERS
Register 9-1 SOC.FAULT (Fault Condition, 00h).......................................................................34
Register 9-2 SOC.STATUS (System Status, 01h).....................................................................35
Register 9-3 SOC.MISC (SOC Miscellaneous Configuration, 02h)............................................36
Register 9-4 SOC.PWRCTL (Power Control, 03h)....................................................................37
Register 9-5 SOC.FAULTENABLE (Fault mask, 04h)...............................................................38
Register 9-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05h)......................................39
Register 9-7 SOC.SYSCONF (System Configuration, 2Bh) ......................................................40
Register 10-1 SOC.CFGAIO0 (AIO0 Configuration, 06h)..........................................................85
Register 10-2 SOC.CFGAIO1 (AIO1 Configuration, 07h)..........................................................86
Register 10-3 SOC.CFGAIO2 (AIO2 Configuration, 08h)..........................................................87
Register 10-4 SOC.CFGAIO3 (AIO3 Configuration, 09h)..........................................................88
Register 10-5 SOC.CFGAIO4 (AIO4 Configuration, 0Ah)..........................................................89
Register 10-6 SOC.CFGAIO5 (AIO5 Configuration, 0Bh)..........................................................90
Register 10-7 SOC.CFGAIO6 (AIO6 Configuration, 0Ch) .........................................................91
Register 10-8 SOC.CFGAIO7 (AIO7 Configuration, 0Dh) .........................................................92
Register 10-9 SOC.CFGAIO8 (AIO8 Configuration, 0Eh)..........................................................93
Register 10-10 SOC.CFGAIO9 (AIO9 Configuration, 0Fh)........................................................94
Register 10-11 SOC.SIGSET (Signal Manager Configuration, 10h)..........................................95
Register 10-12 SOC.HPDACH (HPDAC High Setting, 11h)......................................................96
Register 10-13 SOC.HPDACL (HPDAC Low Setting, 12h) .......................................................96
Register 10-14 SOC.LPDACH (LPDAC High Setting, 13h) .......................................................96
Register 10-15 SOC.LPDAC1 (LPDAC Low Setting, 14h).........................................................96
Register 10-16 SOC.SHCFG1 (Sample and Hold Configuration, 15h)......................................97
Register 10-17 SOC.SHCFG2 (Sample and Hold Configuration 2, 16h)...................................98
Register 10-18 SOC.PROTINTEN (Protection Interrupt Enable, 17h) .......................................99
Register 10-19 SOC.PROTSTAT (Protection Interrupt Status, 18h)........................................100
Register 10-20 SOC.DOUTSIG0 (Digital Output 0, 19h).........................................................101
Register 10-21 SOC.DOUTSIG1 (Digital Output 1,1Ah)..........................................................101
Register 10-22 SOC.DINSIG0 (Digital Input 0, 1Bh) ...............................................................102
Register 10-23 SOC.DINSIG1 (Digital Input 1, 1Ch)...............................................................102
Register 10-24 SOC.CFGIO1 (AIO10-AIO13 Configuration 1, 1Dh)........................................103
Register 10-25 SOC.SIGINTEN (AIO Interrupt Enable Configuration, 1Fh).............................104
Register 10-26 SOC.SIGINTF (AIO Interrupt Flag, 20h)..........................................................105
Register 10-27 SOC.BLANKING (Comparator Blanking Configuration, 21h)...........................106
Register 10-28 SOC.SPECCFG0 (AIO7 Comparator Hysteresis Configuration, 22h)..............107
Register 10-29 SOC.SPECCFG1 (AIO8/9 Comparator Hysteresis Configuration, 23h)...........108
Register 10-30 SOC.SPECCFG2 (AIO7/8 Comparator MUX Input Configuration, 24h) ..........109
Register 10-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25h) .............110
Register 11-1 SOC.CFGDRV1 (Driver Configuration 1, 27h) ..................................................120
Register 11-2 SOC.CFGDRV2 (Driver Configuration 2, 28h) ..................................................121
Register 11-3 SOC.CFGDRV3 (Driver Configuration 3, 29h) ..................................................122

Power Application Controller®
-10- Copyright ©2020 Qorvo, Inc.
Rev 2.2 –Nov 25, 2020
Register 11-4 SOC.STATDRV (Driver Status, 2Ah) ................................................................123
Register 11-5 SOC.CFGDRV4 (Driver Configuration 4, 7Bh)..................................................124
Register 11-6 SOC.DRV_FLT (Driver Fault Flag, 7Ch)...........................................................124
Register 11-7 SOC.ENDRV (Driver Manager Enable, 7Dh) ....................................................124
Register 11-8 SOC.WDTPASS (WDT Password, 7Eh)...........................................................125