Qorvo ACT88326 User manual


ACT88326
Advanced PMU with B
yp
ass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 1 of 45 www.qorvo.com
BENEFITS and FEATURES
 Wide input voltage range
 Vin = 2.7V to 5.5V
 Complete integrated power solution
 One 4A DC/DC Step-Down with Bypass Mode
 Two 3A DC/DC Step-Down Regulators
 Two 300mA LDOs
 High Power Load Switch Gate Driver with Slew
Rate Control
 Space Savings
 Fully integrated
 High Fsw = 2.25MHz or 1.125MHz
 Integrated sequencing
 Standard PTH PCB Compatible Footprint
 Easy system level design
 Configurable sequencing
 Seamless sequencing with external supplies
 Programmable Reset and Power Good GPIO’s
 Buck 1 Bypass Mode for 3.3V system level
compliance
 Highly configurable
 µP interface for status reporting and controllability
 Flexible Sequencing Options
 I2C Interface – 1MHz
 Multiple Sleep Modes
 See ACT88325 for non-Pushbutton Startup
APPLICATIONS
 Solid-State Drives
 Microcontroller Applications
 FPGA
 Personal Navigation Devices
GENERAL DESCRIPTION
The ACT88326 PMIC is an integrated ActivePMU™
power management unit. It is highly flexible and can be
reconfigured via I2C for multiple applications without the
need for PCB changes. The low external component
count and high configurability significantly speeds time
to market. Examples of configurable options include
output voltage, startup time, slew rate, system level
sequencing, switching frequency, sleep modes,
operating modes etc. The core of the device includes 3
DC/DC step down converters using integrated power
FETs, and 2 low-dropout regulators (LDOs). Each
regulator can be configured for a wide range of output
voltages through the I2C interface.
ACT88326 is programmed at the factory with a default
configuration. The default settings can be optimized for
a specific design through the I2C interface. Contact the
factory for specific default configurations.
The ACT88326 includes features that allow flexibility for
all system level configurations. The buck converter can
be reconfigured as a bypass switch. It also contains a
high power load switch controller. It’s external power
supply enable and power good interface allows
seamless sequencing with external power supplies.
The ACT88326 PMIC is available in a 2.7 x 3 mm 36 pin
WLCSP package. The IC pinout is optimized to allow
standard, low-cost PTH PCB layouts.
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 2 of 45 www.qorvo.com
TYPICAL APPLICATION DIAGRAM
LDO1 300mA
BUCK1 4A
BUCK2 3A
BUCK3 3A
LDO2 300mA
SCL
SDA
nRESET
IRQ
PG
External
DC/DC
ENABLE
2.7V ~ 5.5V Input
PWREN
SOCACT88326
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 3 of 45 www.qorvo.com
FUNCTIONAL BLOCK DIAGRAM
VIN_IO
SCL
Digital
Controller
External
SMPS
IOSupply
ACT88326
Digital
Core
LSG
Load
Buck1
Controller
Vref 2x22µF
1µH
FB_B1
PGND
SW_B1
VIN
FB_B1
10µF
Buck2/
Bypass
Controller
Vref
22µF
1µH
FB_B2
SW_B2
VIN
FB_B2
10µF
Buck3
Controller
Vref
22µF
1µH
FB_B3
SW_B3
VIN
FB_B3
10µF
nPB
SDA
GPIO1
GPIO2
EN
PG GPIO4
GPIO3
Vref
LDO1
Vref
AVIN
LDO2
Load Switch Gate
Drives
AGND
PGND
PGND
1µF
1µF
1µF
FB
FB
Input Rail
1µF
Input Rail
Input Rail
Supply
Push Button1/
On/Off
50kΩ
PushButton2/
ManualReset
1kΩ
Push Button
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 4 of 45 www.qorvo.com
ORDERING INFORMATION
PART NUMBER VIN VBUCK1 VBUCK2 VBUCK3 VLDO1 VLDO2 VLSG
ACT88326VA102-T 5V 0.85V 1.35V 3.0V 1.8V 3.0V ON
ACT88326VA105-T 2.9V-5.5V 0.9V 1.2V 0.9V 1.1V 1.8V ON
ACT88326VAxxx-T
OptionCode
PinCount
PackageCode
ProductNumber
TapeandReel
Note 1: Standard product options are identified in this table. Contact factory for custom options, minimum order quantity required.
Note 2: All Active-Semi components are RoHS Compliant and with Pb-free plating unless specified differently. The term Pb-free means semiconductor
products that are in compliance with current RoHS (Restriction of Hazardous Substances) standards.
Note 3: Package Code designator “V” represents CSP
Note 4: Pin Count designator “A” represents 36 pins
Note 5: “xxx” represents the CMI (Code Matrix Index) option. The CMI identifies the IC’s default register settings
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 5 of 45 www.qorvo.com
PIN CONFIGURATION
A B C D E F
1 FB_B3 LDO1 AVIN LDO2 nPB FB_B2
2 VIN_B3 VIN_B3 LSG VIN_B2 VIN_B2 VIN_B2
3 SW_B3 SW_B2 SW_B2 SW_B2
4 SW_B3 PGND12 PGND12 PGND12
5 PGND3 SW_B1 SW_B1 SW_B1
6 AGND GPIO3 GPIO2 VIN_B1 VIN_B1 VIN_B1
7 SDA SCL GPIO1 GPIO4 VIN_IO FB_B1
Figure 1: Pin Configuration – Top View (bumps down) CSP 36 Balls 2.7mm x 3mm
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 6 of 45 www.qorvo.com
PIN DESCRIPTIONS
PIN NAME DESCRIPTION
A1 FB_B3 Feedback for Buck3 Regulator. Connect directly to the Buck3 output capacitor.
B1 LDO1 Output for LDO1 Regulator
C1 AVIN Dedicated VIN Power Input for LDO1 & LDO2 Regulators and Analog VIN Input
D1 LDO2 Output for LDO2 Regulator
E1 nPB Multi-purpose push-button input used to start the IC. This is the PWREN pin on the ACT88325.
F1 FB_B2 Feedback for Buck2 Regulator. Connect directly to the Buck2 output capacitor.
A2, B2 VIN_B3 Dedicated Buck3 VIN Power Input. Connect the Buck3 input caps directly to these pins
C2 LSG Load Switch Gate Driver Output
D2, E2, F2 VIN_B2 Dedicated Buck2 VIN Power Input. Connect the Buck2 input caps directly to these pins.
A3, A4 SW_B3 Switch Pin for Buck3 Regulator
D3, E3, F3 SW_B2 Switch Pin for Buck2 Regulator
D4, E4, F4 PGND12 Power Ground for Buck1 and Buck2. Connect the Buck1 and Buck2 input caps directly to
these pins.
A5 PGND3 Power Ground for Buck3. Connect the Buck3 input caps directly to these pins.
D5, E5, F5 SW_B1 Switch Pin for Buck1 Regulator
A6 AGND Analog Ground
B6 GPIO3 / nIRQ General Purpose I/O Port 3. Typically configured as an interrupt (IRQ) open drain output.
C6 GPIO2 General Purpose I/O Port 2. Can be configured for several different functions.
D6, E6, F6 VIN_B1 Dedicated Buck1 VIN Power Input. Connect the Buck1 input caps directly to these pins.
A7 SDA I2C Data Input and Output
B7 SCL I2C Clock Input
C7 GPIO1 / DVS General Purpose I/O Port 1. Typically configured as a dynamic voltage scaling input or voltage
select input.
D7 GPIO4 / nRESET General Purpose I/O Port 4. Typically configured as an nRESET open drain output
E7 VIN_IO Digital Input Reference Voltage Input
F7 FB_B1 Feedback for Buck1 Regulator. Connect directly to the Buck1 output capacitor.
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 7 of 45 www.qorvo.com
ABSOLUTE MAXIMUM RATINGS
PARAMETER VALUE UNIT
All Pins to PGND12 unless stated otherwise below -0.3 to 6 V
VIN_xx to PGND12 -0.3 to 6 V
SW_Bx to PGND12 -0.3 to VIN_xx + 1 V
nPB to AGND -0.3 to AVIN + 0.3 V
GPIOx to AGND -0.3 to VIN_IO + 0.3 V
FB_Bx to PGND -0.3 to VIN_xx + 0.3 V
LDOx to PGND -0.3 to VIN_xx + 0.3 V
AGND to PGND12 -0.3 to + 0.3 V
Junction to Ambient Thermal Resistance (Note 2) 39 °C/W
Junction to Case Thermal Resistance (Note 2) 6.5 °C/W
Operating Junction Temperature -40 to 150 °C
Storage Temperature -55 to 150 °C
Note1: Do not exceed these limits to prevent damage to the device. Exposure to absolute maximum rating conditions for long periods may affect
device reliability.
Note2: Measured on Active-Semi Evaluation Kit.
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 8 of 45 www.qorvo.com
DIGITAL I/O ELECTRICAL CHARACTERISTICS
(VIN_IO = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GPIO1, GPIO2, GPIO4 Input Low VIN_IO = 1.8V 0.40
GPIO3 Input Low VIN_IO = 1.8V 0.25 V
GPIO1, GPIO2, GPIO3, GPIO4 Input High VIN_IO = 1.8V 1.25 V
GPIO1, GPIO2, GPIO4 Input Low VIN_IO = 3.3V 1.0 V
GPIO3 Input Low VIN_IO = 3.3V 0.40 V
GPIO1, GPIO2, GPIO3, GPIO4 Input High VIN_IO = 3.3V 2.3 V
GPIO1, GPIO2, GPIO3, GPIO4 Leakage Current Output = 5V 1 µA
GPIO1, GPIO2, GPIO4 Output Low IOL = 10mA 0.35 V
GPIO3 Output Low IOL = 1mA 0.35 V
GPIO1, GPIO2 Output High IOH = 1mA VIN_IO
- 0.35 V
GPIO4 Deglitch Time (falling) 15 µs
GPIO4 Deglitch Time (rising) 10 µs
VIN_IO Operating Range 1.5 VIN V
nPB external resistor for Push-button function AVIN = 3.3V 50 kΩ
nPB external resistor for Manual Reset function AVIN = 3.3V 1 kΩ
nPB internal pullup resistor AVIN = 3.3V 0.6 2 MΩ
nPB Manual Reset (MR) rising threshold 0.75 V
nPB De-bounce Time Push button presses shorter than this
time are ignored 32 ms
nPB Activation Time
(duration for successful turn-on)
PB WAIT TIME SET[1:0] = 00
PB WAIT TIME SET[1:0] = 01
PB WAIT TIME SET[1:0] = 10
PB WAIT TIME SET[1:0] = 11
0.032
0.5
1.0
2.0
s
nPB Power Cycle with Push Button Pull down through 50kΩ, press and
release for power cycle 4 s
nPB Power Off with Push Button
Pull down through 50kΩ, press and hold
until power off occurs (CMI configurable
option)
6 s
nPB Soft Reset Time Pull down through 1kΩ, starts soft reset 0.032 4 s
nPB Power Cycle or Manual Reset Time Pull down through 1kΩ, starts power
cycle or Manual reset 4 s
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 9 of 45 www.qorvo.com
SYSTEM CONTROL ELECTRICAL CHARACTERISTICS
(VIN_IO = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Supply Voltage Range: AVIN
referenced to AGND 2.7 5.5 V
UVLO Threshold Falling 2.5 2.6 2.7 V
UVLO Hysteresis 100 mV
System Monitor (SYSMON) Programmable
Range 2.7 4.2 V
OV Threshold Rising 5.4 5.75 6.0 V
OV Hysteresis 80 200 320 mV
Operating Supply Current All Regulators Disabled 10 µA
Operating Supply Current All Regulators Enabled but no load 250 µA
Thermal Shutdown Temperature rising 140 160 180 °C
Thermal Shutdown Hysteresis 30 °C
Power Up Delay after initial VIN Time from VIN > UVLO threshold to
Internal Power-On Clear (POR) 120 200 µs
Startup Delay after initial VIN Time from VIN > UVLO threshold to start of
first regulator turning On. (zero delay) 1500 2000 µs
Oscillator Frequency 2.13 2.25 2.37 MHz
VIN UV Interrupt Threshold Falling Referenced to rising threshold 200 mV
VIN UV Threshold Rising Programming
Range
Rising edge threshold can power up
device. Configurable in 100mV steps. 2.7 3.6 4.2 V
VIN UV Shutdown Threshold Falling 2.6 V
VIN OV Shutdown Threshold Rising 5.75 V
VIN OV Shutdown Threshold Falling 5.5 V
VIN Deglitch Time UV 100 µs
VIN Deglitch Time OV 200 µs
Transition time from Deep Sleep (DPSLP)
State to Active State
Time from GPIOx pin transition to time
when the first regulator turns ON with
minimum turn on delay configuration.
1 ms
Transition time from Sleep State (SLEEP)
to Active State
Time from I2C command to clear sleep
mode to time when the first regulator
turns ON with minimum turn on delay
configuration.
100 µs
Time to first power rail turn off
Time from turn Off event to when the first
power rail turns off with minimum turn off
delay configuration
120 µs
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 10 of 45 www.qorvo.com
Startup Delay Programmable Range
ONDLY=00
ONDLY=01
ONDLY=10
ONDLY=11
0
0.25
0.5
1.0
ms
Turn Off Delay Programmable Range Configurable in 0.25ms steps 0 7.75 ms
nRESET Programmable Range Configurable to 20, 40, 60 or 100ms. 20 100 ms
Note 1: All Under-voltage Lockout, Overvoltage measurements are referenced to the AVIN Input and AGND Pins.
Note 2: All POK Under-voltage and Overvoltage measurements are referenced to the VIN Input and PGNDx Pins.
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
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ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 11 of 45 www.qorvo.com
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK1)
(VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER CONDITIONS MIN TYP MAX UNIT
Input Operating Voltage Range 2.7 5.5 V
Output Voltage Programming Range 1 See CMI section for programming details 0.6 3.0 V
Output Voltage Programming Range 2 See CMI section for programming details 0.8 4.0 V
Standby Supply Current, Low Power
Mode Enabled
VOUT_B1 = 103% setpoint, Enabled, VOUT_B1
setpoint = 1.0V, No Load 40 60 µA
Shutdown Current Regulator Disabled 1 µA
Output Voltage Accuracy VOUT_B1 = default CMI voltage, continuous
PWM mode -1 VNOM 1 %
Output Voltage Accuracy VOUT_B1 = default CMI voltage, PFM mode -2 VNOM 2 %
Line Regulation VOUT_B1 = default CMI voltage, PWM
Regulation 0.1 %/V
Load Regulation VOUT_B1 = at default CM, PWM Regulation 0.1 %/A
Power Good Threshold VOUT_B1 Rising 90 92.5 95 %VNOM
Power Good Hysteresis VOUT_B1 Falling 3 %VNOM
Overvoltage Fault Threshold VOUT_B1 Rising 107.5 110 112.5 %VNOM
Overvoltage Fault Hysteresis VOUT_B1 Falling 3 %VNOM
Switching Frequency VOUT_B1 ≥ 20% of VNOM, Configurable -5% 1.125 /
2.25 +5% MHz
Soft-Start Period Tset 10% to 90% VNOM 480 750 µs
Current Limit, Cycle-by-Cycle
(accuracy is only valid for the specific
CMI’s default setting)
ILIM[1:0] = 00
ILIM[1:0] = 01
ILIM[1:0] = 10
ILIM[1:0] = 11
4.2
3.6
3.0
2.4
5.4
4.7
3.8
3.1
6.6
5.7
4.6
3.7
A
Current Limit, Shutdown % compared to Current Limit, cycle-by-cycle 112.5 122.5 132.5 %
Current Limit, Warning % compared to Current Limit, cycle-by-cycle 67.5 75 82.5 %
PMOS On-Resistance ISW = -1A, VIN = 5.0V 40 50 mΩ
NMOS On-Resistance ISW = 1A, VIN = 5.0V 16 25 mΩ
SW Leakage Current
VIN = 5.5V, VSW = 0V 1 µA
VIN = 5.5V, VSW = 5.5V 1 µA
Dynamic Voltage Scaling Rate 3.50 mV/µs
Output Pull Down Resistance Enabled when regulator disabled 4.4 8.75 Ohms
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
Tél. [phone] - Fax. [phone] - e-mail: [email protected] - Site Web: www.es-france.com

ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 12 of 45 www.qorvo.com
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK1) –
BYPASS MODE
(VIN = 3.3V, TA = 25°C, unless otherwise specified.)
PARAMETER CONDITIONS MIN TYP MAX UNIT
Input Voltage for By-Pass Mode 2.7 3.3 5.5 V
PMOS On-Resistance ISW = -1A, VIN = 3.3V, Max=125°C at TJunction 0.04 0.06 Ω
Internal PMOS Current Detection Triggers Interrupt on IRQ Pin 2.8 4.2 5.4 A
Internal PMOS Current Detection Deglitch Time 10 µs
Internal PMOS Current Shutdown Shuts down after deglitch time and stays off
for Off-Time 4.7 6.5 8.7 A
Internal PMOS Current Shutdown Deglitch Time 5 µs
Internal PMOS Current Shutdown Off-Time
(Retry time) 14 ms
Internal PMOS Soft start VIN = 3.3V Input, Cout = 47uF, Default setting
ISS[1:0] = 00 500 µs
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
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ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 13 of 45 www.qorvo.com
INTERNAL STEP-DOWN DC/DC ELECTRICAL CHARACTERISTICS REGULATOR: (BUCK2/3)
(AVIN = VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER CONDITIONS MIN TYP MAX UNIT
Input Operating Voltage Range 2.7 5.5 V
Buck2 Output Voltage Programming
Range 1 See CMI section for programming details 0.6 3.0 V
Buck2 Output Voltage Programming
Range 2 See CMI section for programming details 0.8 4.0 V
Buck3 Output Voltage Programming
Range See CMI section for programming details 0.8 4.0 V
Standby Supply Current, Low Power
Mode Enabled
VOUTx = 103%, Regulator Enabled, No load,
VOUTx = default CMI voltage 40 µA
Shutdown Current VIN = 5.0V, Regulator Disabled 0.1 1 µA
Output Voltage Accuracy VOUTx = default CMI voltage, IOUTx = 1A
(continuous PWM mode) -1% VNOM 1% V
Line Regulation VOUTx = default CMI voltage, PWM Regulation 0.1 %
Load Regulation VOUTx = default CMI voltage, PWM Regulation 0.1 %
Power Good Threshold VOUTx Rising 90 92.5 95 %VNOM
Power Good Hysteresis VOUTx Falling 3 %VNOM
Overvoltage Fault Threshold VOUTx Rising 107.5 110 112.5 %VNOM
Overvoltage Fault Hysteresis VOUTx Falling 3 %VNOM
Switching Frequency VOUTx ≥ 20% of VNOM -5% 1.125 /
2.25 +5% MHz
Soft-Start Period Tset 10% to 90% VNOM 480 750 µs
Startup Time Time from Enable to PG 700 µs
Current Limit, Cycle-by-Cycle
(accuracy is only valid for the spe-
cific CMI’s default setting)
ILIM[1:0] = 00
ILIM[1:0] = 01
ILIM[1:0] = 10
ILIM[1:0] = 11
3.7
3.1
2.6
2.2
4.6
3.9
3.2
2.6
5.4
4.5
3.8
3.1
A
Current Limit, Shutdown % compared to Current Limit, cycle-by-cycle 112.5 122.5 132.5 %
Current Limit, Warning % compared to Current Limit, cycle-by-cycle 67.5 75 82.5 %
PMOS On-Resistance ISW_Bx = -500mA, VIN = 5V 80 mΩ
NMOS On-Resistance ISW_Bx = 500mA, VIN = 5V 50 mΩ
SW Leakage Current
VIN = 5.5V, VSW_Bx = 0 or 0V 1 µA
VIN = 5.5V, VSW_Bx = 0 or 5.5V 1 µA
Dynamic Voltage Scaling Rate 3.50 mV/us
Output Pull Down Resistance Enabled when regulator disabled 9.4 20 Ω
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
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ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 14 of 45 www.qorvo.com
LDO1-2 ELECTRICAL CHARACTERISTICS
(AVIN = VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Operating Voltage Range LDO1 AVIN (Input Voltage) to the LDO1 2.7 5.5 V
Output Voltage Range
Option 1 Configurable in 9.375mV steps 0.6 2.991 V
Option 2 Configurable in 12.5mV steps 0.8 3.9875 V
Output Current 270 300 mA
Output Voltage Accuracy AVIN - VLDOx_OUT > 0.4V -1 VNOM 1 %
Line Regulation AVIN - VLDOx_OUT > 0.4V
ILDOx_OUT = 1mA 0.03 0.2 %
Load Regulation ILDOx_OUT = 1mA to 100mA,
VLDOx_OUT = default CMI 0.5 %
Power Supply Rejection Ratio
f = 1kHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1 40.8 dB
f = 10kHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1 31.2 dB
f = 2.25MHz, ILDOx_OUT = 20mA,
VLDOx_OUT = 1.8V, Note 1 53.6 dB
Supply Current per Output Regulator Disabled 1 µA
Supply Current Regulator Enabled, No load 15 20 µA
Soft-Start Period Time from soft start “ON” to PGOOD. VLDOx = 1.8V 140 225 350 µs
Time from soft start “ON” to PGOOD. VLDOx = 3.3V 140 300 430 µs
Power Good Threshold VLDOx_OUT Rising 90 92.5 95 % VNOM
Power Good Hysteresis VLDOx_OUT Falling 3 % VNOM
Overvoltage Fault Threshold VLDOx_OUT Rising 105 110 115 % VNOM
Overvoltage Fault Hysteresis VLDOx_OUT Falling 3 % VNOM
Discharge Resistance 50 125 Ω
Dropout Voltage ILDOx_OUT = 220mA, VLDOx_OUT = 2.7V 150 mV
Output Current Limit
ILIM [1:0] = 00
ILIM [1:0] = 01
ILIM [1:0] = 10
ILIM [1:0] = 11
-35%
190
250
330
465
+35% mA
Startup Time Time from Enable to PG 300 400 µs
Note 1: AVIN - VLDOx_OUT > 0.4V
(ES) Equipements Scientifiques SA - Département Composants & Modules - 127 rue de Buzenval BP 26 - 92380 Garches
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ACT88326
Advanced PMU with Bypass Switch,
& Pushbutton Function
Data Sheet Rev. 3.0, Nov. 11, 2019 | Subject to change without notice 15 of 45 www.qorvo.com
LDO2 LOAD SWITCH MODE ELECTRICAL CHARACTERISTICS – BYPASS MODE
(AVIN = VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Operating Voltage Range LDO2 AVIN (Input Voltage) to the LDO2 2.7 5.5 V
PMOS On-Resistance 0.3 0.5 mΩ
Internal PMOS Current Detection Triggers Interrupt on IRQ Pin 330 500 mA
Internal PMOS Current Detection Deglitch Time 10 µs
Supply Current Load Switch Enabled, No load 25 55 µA
Internal PMOS Current Shutdown Shuts down after deglitch time and
stays off for Off-Time 330 500 mA
Internal PMOS Current Shutdown Deglitch Time 5 µs
Internal PMOS Current Shutdown Off time
(Retry time) 14 ms
Internal PMOS Soft start Only used with 3.3V Input, Cout = 1uF,
Default Setting ISS [1:0] = 00. 10 mV/µs
LOAD SWITCH GATE DRIVER ELECTRICAL CHARACTERISTICS
(VIN = 5V, TA = 25°C, unless otherwise specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Operating Voltage Range 2.7 5.5 V
Maximum Output - Gate Voltage Gate fully on 2*VIN V
Soft-Start Slew Rate Gate Node rising from 0 to 2V with 1nF output
capacitor. (Configurable)
800
400
260
200
us
Gate Pull-up Current
GATE1 SLEW = 00
GATE1 SLEW = 01
GATE1 SLEW = 10
GATE1 SLEW = 11
2.5
5
7.5
10
µA
Fault Deglitch Time 10 µs
Gate Discharge Resistance 75 Ω
Startup Delay 75 µs
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Advanced PMU with Bypass Switch,
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I2C INTERFACE ELECTRICAL CHARACTERISTICS
(VIN_IO = 1.8V, TA = 25°C, unless otherwise specified.)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SCL, SDA Input Low VIN_IO = 1.8V 0.4 V
SCL, SDA Input High VIN_IO = 1.8V 1.25 V
SCL, SDA Input Low VIN_IO = 3.3V 1.0 V
SCL, SDA Input High VIN_IO = 3.3V 2.3 V
SDA Leakage Current SDA = 5V 1 µA
SDA Output Low IOL = 5mA 0.35 V
SCL Clock Frequency, fSCL 0 1000 kHz
SCL Low Period, tLOW 0.5 µs
SCL High Period, tHIGH 0.26 µs
SDA Data Setup Time, tSU 50 ns
SDA Data Hold Time, tHD (Note1) 0 ns
Start Setup Time, tST For Start Condition 260 ns
Stop Setup Time, tSP For Stop Condition 260 ns
Capacitance on SCL or SDA Pin 10 pF
SDA Fall Time SDA, Tof Device requirement 120 ns
Pulse Width of spikes must be suppressed on SCL and SDA 0 50 ns
Note1: Comply with I2C timings for 1MHz operation - “Fast Mode Plus”.
Note2: No internal timeout for I2C operations, however, I2C communication state machine will be reset when entering Deep Sleep, Sleep,
OVUVFLT, and THERMAL states to clear any transactions that may have been occurring when entering the above states.
Note3: This is an I2C system specification only. Rise and fall time of SCL & SDA not controlled by the device.
Note4: Device Address is factory configurable to 7’h25, 7’h27, 7’h67, 7’h6B.
Figure 2: I2C Data Transfer
SDA
SCL
tST tSU
tHD tSP
tSCL
Start
condition
Stop
condition
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Advanced PMU with Bypass Switch,
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SYSTEM CONTROL INFORMATION
General
The ACT88326 is a single-chip integrated power
management solution designed to power many
processors such as the Silicon Motion
SM2258/59/62/63/63XT solid state drive controllers and
the Atmel SAMA5D processors. It integrates three
highly efficient buck regulators, two LDOs, and an
integrated load bypass switch. Its high integration and
high switching frequency result in an extremely small
footprint and low cost power solution. It contains a
master controller that manages startup sequencing,
timing, voltages, slew rates, sleep states, and fault
conditions. I2C configurability allows system level
changes without the need for costly PCB changes. The
built-in load bypass switch enables full sequencing
configurability in 3.3V systems.
The ACT88326 master controller monitors all outputs
and reports faults via I2C and hardwired status signals.
Faults can be masked and fault levels and responses
are configurable via I2C.
Many of the ACT88326 pins and functions are
configurable. The IC’s default functionality is defined by
the default CMI (Code Matrix Index), but much of this
functionality can be changed via I2C. Several GPIOs
can be configured as enable inputs, reset outputs,
dynamic voltage (DVS) inputs, LED drivers, etc. The
GPIO configuration is specifically defined for each
ACT88326 orderable part number. The first part of the
datasheet describes basic IC functionality and default
pin functions. The end of the datasheet provides the
configuration and functionality specific to each CMI
version. Contact sale[email protected] for additional
information about other configurations.
I2C Serial Interface
To ensure compatibility with a wide range of systems,
the ACT88326 uses standard I2C commands. The
ACT88326 operates as a slave device, and can be
factory configured to one of four 7-bit slave addresses.
The 7-bit slave address is followed by an eighth bit,
which indicates whether the transaction is a read-
operation or a write-operation. Refer to each specific
CMI for the IC’s slave address
7-Bit Slave Address 8-Bit Write
Address
8-Bit Read
Address
0x25h 010 0101b 0x4Ah 0x4Bh
0x27h 010 0111b 0x4Eh 0x4Fh
0x67h 110 0111b 0xCEh 0xCFh
0x6Bh 110 1011b 0xD6h 0xD7h
There is no timeout function in the I2C packet
processing state machine, however, any time the I2C
state machine receives a start bit command, it
immediately resets the packet processing, even if it is in
the middle of a valid packet. The I2C functionality is
operational in all states except RESET.
I2C commands are communicated using the SCL and
SDA pins. SCL is the I2C serial clock input. SDA is the
data input and output. SDA is open drain and must have
a pull-up resistor. Signals on these pins must meet
timing requirements in the Electrical Characteristics
Tab l e.
I2C Registers
The ACT88326 contains an array of internal registers
that contain the IC’s basic instructions for setting up the
IC configuration, output voltages, sequencing, fault
thresholds, fault masks, etc. These registers are what
give the IC its operating flexibility. The two types of
registers are described below.
Basic Volatile – These are R/W (Read and Write) and
RO (Read only). After the IC is powered, the user can
modify the R/W register values to change IC
functionality. Changes in functionality include things like
masking certain faults. The RO registers communicate
IC status such as fault conditions. Any changes to these
registers are lost when power is recycled. The default
values are fixed and cannot be changed by the factory
or the end user.
Basic Non-Volatile – These are R/W and RO. After the
IC is powered, the user can modify the R/W register
values to change IC functionality. Changes in
functionality include things like output voltage settings,
startup delay time, and current limit thresholds. Any
changes to these registers are lost when power is
recycled. The default values can be modified at the
factory to optimize IC functionality for specific
applications. Please consult [e-mail] for
custom options and minimum order quantities.
When modifying only certain bits within a register, take
care to not inadvertently change other bits.
Inadvertently changing register contents can lead to
unexpected device behavior.
State Machine
Figure 1 shows the ACT88326 internal state machine.
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POWER OFF State
The POWER OFF state is a PMIC “safe state” or
“shutdown” state. In this state, all the regulator outputs
are turned off. LDO1 has the option to be configured as
an “always-on” regulator so it stays on in the POWER
OFF state.
The ACT88326 enters POWER OFF at initial power on
when input power is applied to the IC and VIN is within
a valid range defined by the VIN_UV and VIN_OV
thresholds. nRESET is asserted low and all volatile and
non-volatile registers are reset to defaults. If the input
voltage drops below the VIN_UV threshold voltage, the
IC transitions from any other state to the POWER OFF
state. It is important to note a transition to POWER OFF
due to VIN_UV returns all volatile and non-volatile
registers to their default states.
The ACT88326 can also enter POWER OFF from any
other state due to an nPB press that initiates the power
off sequence.
The ACT88326 momentarily enters POWER OFF
during a power cycle sequence.
The ACT88326 exits the POWER OFF state when the
I2C bit POWER OFF is cleared to 0, or the nPB pin is
pulled low for > 32ms.
POWER SEQUENCE START State
The POWER SEQUENCE START state is a transitional
state to power on the regulators. The IC is not intended
to operate in this state. When entering POWER
SEQUENCE START from the SLEEP, DPSLP, and
THERMAL states the IC transitions to the ACTIVE state
when all regulators are in regulation.
When entering POWER SEQUENCE START from the
POWER OFF state due to an nPB press, the IC remains
in POWER SEQUENCE START until nPB is released
AND the regulators are in regulation. If nPB is released
before the regulators are in regulation, the IC transitions
back to the POWER OFF state. If nPB is still pressed
and the regulators enter regulation and one of them has
a fault before nPB is released, the IC transitions back to
the POWER OFF state.
When entering POWER SEQUENCE START from the
POWER OFF state due to a power cycle sequence, the
IC stays in POWER SEQUENCE START for 0.5s before
exiting to the ACTIVE state.
ACTIVE State
The ACTIVE state is the normal operating state when
the input voltage is within the allowable range, all
outputs are turned on, and no faults are present.
The ACT88326 enters the ACTIVE state from POWER
SEQUENCE START with a normal nPB startup, an I2C
startup, or a power cycle sequence.
It transitions from the THERMAL state directly to the
ACTIVE state when the die temperature drops back to
allowable limits. Note that when the outputs turn back
on during this transition, any outputs sequencing
dependent on VIN will turn on immediately. Any outputs
dependent on another output turn on with proper
programmed delays.
SLEEP State
The SLEEP state is a low power mode for the operating
system. Each output can be programmed to be on or off
in the SLEEP state. The outputs follow their
programmed sequencing delay times when turning on
or off as they enter or exit the SLEEP state. Buck1/2/3
can be programmed to regulate to their VSET0 voltage,
VSET1 voltage, or be turned off in the SLEEP state.
LDO1/2 can be programmed to regulate to their VSET0
voltage or can be programmed to be turned off. Note
that LDO1/2 do not have a VSET1 voltage.
The IC enters SLEEP state via I2C register bit SLEEP,
I2C register bit SLEEP MODE, and a GPIO input
pin. The IC’s specific CMI determines the specific
combination of these three inputs to enter SLEEP state.
The I2C bit SLEEP MODE is set at factory and cannot
be changed by the user. It controls the logical
combination of the GPIO input and the SLEEP register
bit to enter SLEEP state.
When SLEEP MODE is factory configured to 1, the
logical combination is an “OR” function and when
SLEEP MODE is factory configured to a 0, the logical
combination is an “AND” function.
If no GPIOs are configured as a control input to enter
and exit SLEEP state then only the SLEEP register bit
controls the entry and exit of the SLEEP state.
Tables 1a and 1b shows the conditions to enter SLEEP
state. ACT88326’s I2C stays enabled in SLEEP state.
The IC exits the SLEEP state when the conditions to
enter SLEEP state are no longer present. Asserting nPB
low for > 32ms clears the SLEEP bit to 0 and the PMIC
exits SLEEP state.
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Advanced PMU with Bypass Switch,
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Table 1a. SLEEP Mode Truth Table (SLEEP MODE bit
is configured to 0)
Table 1b. SLEEP Mode Truth Table (SLEEP MODE bit
is configured to 1)
DPSLP State
The DPSLP state is another low power operating mode
for the operating system. It is intended to be used in a
lower power configuration than the SLEEP mode. It is
similar to the SLEEP state, but DPSLP uses slightly
different configurations to enter and exit this mode.
Each output can be programmed to be on or off in the
DPSLP state. This programming can be different and
independent from the SLEEP state. The outputs follow
their programmed sequencing delay times when turning
on or off as they enter or exit the DPSLP state.
The IC can enter DPSLP state via I2C register bit
DPSLP, I2C register bit DPSLP MODE, and a GPIO
input pin. The IC’s specific CMI determines the specific
combination of these three inputs to enter DPSLP state.
The I2C bit DPSLP MODE is set at factory and cannot
be changed by the user. It controls the logical
combination of the GPIO input and the DPSLP register
bit to enter DPSLP state.
When DPSLP MODE is factory configured to 1, the
logical combination is an “OR” function and when
DPSLP is factory configured to a 0, the logical
combination is an “AND” function.
If no GPIOs are configured as a control input to enter
and exit DPSLP state then only the DPSLP register bit
controls the entry and exit of the DPSLP state.
Table 2a and 2b show the conditions to enter DPSLP
state. ACT88326’s I2C stays enabled in DPSLP state.
The IC exits the DPSLP state when the conditions to
enter DPSLP state are no longer present. Asserting
nPB low for > 32ms clears the DPSLP bit to 0 and the
PMIC exits DPSLP state.
Table 2a. DPSLP Mode Truth Table (DPSLP MODE
factory bit is configured to 0)
Table 2b. DPSLP Mode Truth Table (DPSLP MODE
factory bit is configured to 1)
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POWERSEQUENCE
START
SLEEP
Power Cycle (Red dashed line) automatically transitions
from ACTIVE to POWER OFF to POWER SEQENCE
START and back to ACTIVE state.
THERMAL
ACTIVE POWEROFF
DPSLP
(DeepSleep)
Figure 3: Pushbutton State Machine
THERMAL State
In the THERMAL state the chip has exceeded the
thermal shutdown temperature. To protect the device,
all the regulators are shut down and the reset pins are
asserted low. This state can be disabled by setting
register 0x01h bit5 (TMSK) = 1. TMSK prevents the
interrupt from going active, but does not prevent the IC
from entering the THERMAL State. The IC transitions
directly back to the ACTIVE state when the die
temperature cools down.
Startup/Shutdown
When power is applied, the IC enters the POWER OFF
state and stays there indefinitely. This results in a very
low power state. The IC starts up and sequences on the
regulators when the user actively initiates a power on by
either asserting nPB or by writing a 0 into the I2C
POWER OFF bit. When powering on with the nPB pin,
any fault that occurs before nPB is released transitions
the IC back to the POWER OFF state. Any faults that
occur after nPB is released and the IC is in the ACTIVE
state are handled per the proper fault detection proce-
dure as programmed by the IC’s specific CMI. Once in
the ACTIVE state, the IC can stay in that state or auto-
matically transition to either the SLEEP or DPSLP state
depending on the status of the inputs in Tables 1 and 2.
Shutdown is typically accomplished by forcing the sys-
tem to transition to the DPSLP state. Shutdown can also
be accomplished with the nPB pin or by setting the I2C
POWER OFF bit to a 1.
Sequencing
The ACT88326 provides the end user with extremely
versatile sequencing capability that can be optimized for
many different applications. Each of the five outputs has
four basic sequencing parameters: input trigger, turn-on
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