RCA 70/46 User manual

5iPEL:IRA~'u
70/46
Processor
Reference Manual
OOm3LlD
Information
Systems
70-46-601
March 1968

The information contained herein is subject
to change without notice. Revisions may be
issued to advise
of such changes and/or
additions.
First Printing: April 1967
Reissued: March 1968

INTRODUCTION
SYSTEM STRUCTURE
INSTRUCTION
FORMATS
ADDRESSING
PROGRAM INTERRUPT
INPUT/OUTPUT
OPERATION
CONTENTS
RCA Model 70/46 Processor ................................. .
Organization of Data ....................................... .
Data Formats .............................................. ~
Page
1
3
3
Numbering System. .. . . .. . . . . .. .. . . .. . . . . .. . . . . . . . . . . . . . . . . . 3
Main Memory .............................................. .
Non-Addressable
Main Memory ............................... .
Scratch-Pad Memory ........................................ .
Translation Memory ........................................ .
Read-Only Memory ......................................... .
Program Control and Arithmetic Unit ......................... .
Input/Output Control ....................................... .
Interval Timer ............................................. .
RR Format
RX Format
RS Format
SI Format
SS Format
Memory Address Translation ................................. .
Introduction ............................................... .
4
4
4
5
6
6
8
8
9
9
9
10
10
12
16
Processor States. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Processing State PI ...................................... 16
Interrupt Response State P2 •••••••••••••••••••••••••••••• 16
Interrupt Control State P3 ••••••••••••••••••••••••••••••• 16
Machine Condition
State P4 ••• • • • • • • • • • • • • • • • • • • • • • • • • • • • • 16
Processor State Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
General
Registers ....................................... 18
Floating-Point Registers ................................. 18
Interrupt Status Registers ............................... 18
Interrupt Mask Registers ................................ 20
Program Mask Registers ................................. 20
Register Addressing ..................................... 21
Interrupt Flag Register .................................. 21
Interrupt Conditions ......................................... 23
Interrupt Mechanization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Automatic Interrupt ..................................... 23
Program Controlled Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Introduction ............................................... .
Input/Output Channels ...................................... .
Selector
Channels ............................ .......... .
36
36
36
MUltiplexor Channel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
iii

INPUT /OUTPUT
OPERATION
(Cont'd)
MULTI-PROCESSOR
INSTALLA TlON
PRIVILEGED
INSTRUCTIONS
CONTENTS (Cont'd)
Page
Input/Output Operational Control ............................. 38
Programming Considerations Prior to Input/Output Initiation. . 38
Input/Output Initiation .................................. 38
Channel Servicing ....................................... 38
Channel Address Word (CAW) .......................... 40
Channel Block Address (CBA)
........................... 40
Channel Command Word (CCW)
......................... 40
Input/Output Channel Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Channel Address Register (CAR) ........................ 45
Channel Command Register-II (CCR-II) .................. 45
Channel Command Register-I (CCR-I) .................... 46
Assembly/Status Register ..... 0 0 • 0 0 • 0 0 • 0 • 0 • 0 ••• 0 ••••• 0 • • • 47
CBA Register .............................. 0 •• 0 • • • • • • • • • 47
Input/Output Instructions .............. 0 • • • • • • • • • • • • • • • • • • • • • 47
Start Device Instruction . 0 ••••••••• 0 0 • 0 •• 0 • • • • • • • • • • • • • • • • 47
Halt Device Instruction .......... 0 •• 0 • • • • • • • • • • • • • • • • • • • • 52
Test Device
Instruction ................. 0 • 0 0 • • • • • • • • • • • • • • 56
Check Channel Instruction ..... 0 ••••••• 0 ••• 0 • • • • • • • • • • • • • • 60
Input/Output Status Indicators ... 0 0 • 0 •• 0 0 •••• 0 • • • • • • • • • • • • • • • • 60
Condition Code ... 0 ••••••••• 0 0 0 •• 0 0 0 0 • 0 0 0 • 0 • • • • • • • • • • • • • • 61
Channel Status Byte 0 ••••••• 0.0 •• 00 • 0 0 0 • 0 0.00 ••••••••••• 0 63
Standard Device Byte 00 ••• 0 •• 0. 0 ••• 0 •• 0 •••••••• 0......... 65
Sense Bytes ..... o. 0.0 ••••• 0 • 0 ••• '0' • 0 0 • 0 .000 • • • • • • • • • • • • 66
Channel Servicing ........ 0 •••••• 0 •••••••••••• 0 • 0 • • • • • • • • • • • • 66
Servicing a
Data Transfer ...... 0 • • • • • • • • • • • • • • • • • • • • • • • • • 67
End and Chaining Servicing ........... 0 • • • • • • • • • • • • • • • • • • 72
Interrupt Servicing .............. 0 •••• 0 •• 0 •• 0 • • • • • • • • • • • • 77
Introduction
....................... 0 0 •••• 0 • • • • • • • • • • • • • • • • • • 81
Operational Characteristics .............. 0 • 0 •••• 0 • • • • • • • • • • • • • 81
Direct Control Interface .......... 0 ••• 0 o •• 0 0 •• 0 0 • • • • • • • • • • • • • • 82
Static Out Lines ....... 0 0 • 0 •• 0 • 0 ••• 0 0 • 0 • • • • • • • • • • • • • • • • • • 82
Static In Lines ......... 0 ••• 0 0 0 •••• 0 0 • 0 0 • • • • • • • • • • • • • • • • • 82
Signal Out Line
...... 0 ••• 0.00. o •• 0 00 00 •• o. 0 ••••• 0 • • • • • • • 82
External Signal In Line .. 0 ••••••••••••••• 0 • 0 • • • • • • • • • • • • • 82
Power Failure Line (PFND) .. 0 • • • • • • • • • • • • • • • • • • • • • • • • • • 82
Power Failure Inhibit In Line (PFIR) ................... 82
Dual Processor Complex
... 0 ••••••• 0 ••••••• 0 • • • • • • • • • • • • • • • • • • 83
Master/Satellite Complex '" .......... 0 •• 0 • • • • • • • • • • • • • • • • • • • • 84
Maximum Multi-Processor Complex
... 0 • • • • • • • • • • • • • • • • • • • • • • • • 85
Operational Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Transmission
Procedure .. 0 ••• 0 ••••• 0 •••••••••••• 0 • • • • • • • • 86
Response Procedure
... 0 •••••••• 0 •• 0 ••••••••• 0 •••••• 0 •• 00 86
Introduction
................ 0 • 0 ••••••• 0 •••••••• 0 • • • • • • • • • • • • 88
Instruction Formats ........... 0 0 ••••• 0 0 ••••••••••••• 0 • • • • • • • 88
Interrupt Action ..... 00 •• o •• 0 •••••• 0 •••••• 0 •••• 0 ••••••••••• 0 88
Function Call (FC) ..................... 0 • 0 •• 0 ••••••••••••• 0 90
Special Function # 1 Load Translation Memory (LTM) ........ 92
Special
Function #2 Scan Translation Memory and Store (STMS) 94
Special
Function # 3 Store Translation Memory (STM) '" 0 ••• 0 96
Special Function # 4 Load
Interval Timer (LIT) . 0 ••• 0 0 • 0 •• 0 • • 97
iv

PRIVILEGED
INSTRUCTIONS
(Cont'd)
PROCESSOR STATE
CONTROL
INSTRUCTIONS
FIXED-POINT
INSTRUCTIONS
CONTENTS (Cont'd)
Page
Special Function # 5 Store Interval Timer (SIT) 0 00 00 00 00 00 00 0 98
Special
Function # 6 Paging Queue and Paging Error Interrupt
Service 0000000000000000000000000000000000000000000000000 99
Load
Scratch-Pad (LSP) 0000000000000000000000000000000000000 102
Store Scratch-Pad (SSP) 0000000000000000000000000000000000000 103
Program Control (PC) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 104
Idle (IDL) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 106
Diagnose (DIG) 0000000 0 0 0 0 0 0 0 0000000000 0000 000 000 00 00 0000 00 0 107
Start Device (SDV) 0 00 00 00 000000 0 00000 0000 00 0000 0 0 000 0 0 00 0 0 0 108
Halt Device (HDV) 0 0 0 00 00 00 000000 000 00000 0000 0000 00 00 0 0 00 00 0 111
Test Device (TDV) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 113
Check Channel (CKC) 0000000000000000000000000000000000000000 115
Insert Storage Key (ISK) 0 00 0000 00 00 0000000000 0000000 00 00 00 00 0 116
Set Storage Key (SSK) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 117
Write Direct (WRD) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 118
Read Direct (RDD) 0000000000.000000000000000000000000000000 119
Introduction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120
Instruction Format 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120
Condition Code Utilization 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120
Interrupt Action 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 120
Supervisor Call (SVC) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 121
Set Program Mask (SPM) 000000000000000000000000000000000000 122
Introduction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123
Data Format 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 123
Representation of Numbers 0 00 00 00 00 0000 0 0 0 0 0 0 00 00 0 0 0 00 0 0 00 00 0 123
Instruction Formats 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 124
Condition Code
Utilization 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125
Interrupt Action 0 00 0 0 00 00 00 0000 0 0 0 0 000.00 00 0000000 0 0 00 00 00 0 0 0 126
Load
Word (LR) (L) 00000000000000000000 ••••••• 000000000000 127
Load Halfword (LH) 0 0 0 0 0 0 0 0 • 0 0 0 0 0 • 0 • 0 ••••• 0 0 0 •• 0 0 0 0 0 0 0 0 0 0 0 0 128
Load
and Test (LTR) 0 0 0 •• 0 0 ••• 0 ••• 0 0 • 0 • 0 0 •• 0 ••• 0 0 0 0 0 0 0 0 0 0 0 0 129
Load Complement
(LCR) .. 0 0 0 0 0 0 0 •• 0 • 0 • 0 0 0 0 •••• 0 0 0 0 0 0 0 0 0 0 0 0 0 130
Load Positive (LPR) 0 0 0 0 0 •••• 0 • 0 • 0 •• 0 • 0 0 •• '0 •• 0 • 0 0 0 0 0 0 0 0 0 0 0 0 131
Load
Negative (LNR) 0000. 000. 00. 000.00 ••• 00 •••• 0 0 0 00' • o. 000 132
Load Multiple
(LM) 0 0 0 0 0 0 0 0 0 0 0 • 0 0 0 0 0 0 0 ••••••• 0 0 • 0 0 0 0 0 0 0 0 0 0 0 0 133
Add
Word (AR) (A) 0000000000000000.0. o ••• 00.00.00.0000000 134
Add Halfword (AH) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 • 0 0 0 • 0 0 0 • 0 0 0 0 0 0 0 0 0 0 0 0 0 0 135
Add Logical (ALR) (AL) 0 0 0 0 •• 0 0 • 0 0 0 • 0 ••••••••• 0 0 0 0 0 0 0 0 0 0 0 0 136
Subtract Word (SR) (S) 000 00 o •• 0 00 o •••••• 0 0 •••• 0 00 0000 00 00 0 137
Subtract Halfword (SH) o. 0 0 • 0 0 0 • 0 0 0 • 0 0 • 0 0 ••••••• 0 0 0 0 0 0 0 0 0 0 o. 138
Subtract Logical (SLR) (SL) 0 0 0 • 0 0 0 0 0 0 0 •• 0 0 ••• 0 0 0 0 0 0 0 0 0 0 0 0 0 0 139
Compare Word (CR) (C) 0.0 •• 000 •• 00. 00. 0 •• 0 0 •• 0000. 000. 000 140
Compare Halfword (CH) 0 0 0 0 0 0 0 0 0 0 • 0 0 •• 0 0 • 0 • 0 •• 0 0 0 0 0 • 0 0 0 • 0 0 0 141
Multiply \Vord
(MR) (M) 00.000. 0000000. o •• 0 0 • 0 0 00000000000. 142
Multiply
Halfword (MH) 0 0 0 0 0 0 0 0 0 0 0 ••• 0 0 o •• 0 0 • 0 0 0 0 0 0 0 0 0 0 0 0 o. 143
Divide
(DR) (D) 0" 0 0 0 • 0 0 0 • 0 • 0 • 0 0 0 0 0 • 0 0 •••• 0 ••• 0 0 0 0 0 0 0 0 0 0 0 0 144
Convert to Binary (CVB) 00000000. 0 0 0 ••• 0 ••••• 0 • 0 0 0 000000000 145
Convert to Decimal (CVD) .......................... 0 • • • • • •• 146
Store Word (ST) .. 000 •• 0000 •• 0 ••••••••••••••••••• 00 •••• 0... 147
v

FIXED-POINT
INSTRUCTIONS
(Cont'd)
DECIMAL
ARITHMETIC
INSTRUCTIONS
CONTENTS (Cont'd)
Page
Store Halfword (STH) ...................................... 148
Store Multiple (STM) ....................................... 149
Shift Left Single (SLA) ..................................... 150
Shift Right Single (SRA) ................................... 151
Shift Left Double (SLDA) .................................. 152
Shift Right Double (SRDA) ................................. 153
Introduction ................................................ 154
Data Formats .................................... . . . . . . . . . .. 154
Representation of Numbers .................................. 155
Instruction Format .......................................... 155
Condiiion Code Utilization ............................... . . . .. 156
Interrupt Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 156
Add Decimal (AP) .......................................... 158
Subtract Decimal (SP) ....................................... 159
Zero and Add (ZAP) ........................................ 160
Compare Decimal (CP) ...................................... 161
Multiply Decimal (MP) ...................................... 162
Divide Decimal (DP) ........................................ 163
Pack (PACK) ............................................... 164
Unpack (UNPK) ............................................ 165
Move with Offset (MVO) ..................................... 166
LOGICAL Introduction ............................................... , 167
INSTRUCTIONS Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 167
Instruction Formats ......................................... 168
Condition Code Utilization ................................... 169
Interrupt Action . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 169
Move (MVI) (MVC) ........................................ 170
Move Numerics (MVN) ..................................... 171
Move Zones (MVZ) ......................................... 172
Test and Set (TS) ......................................... 173
Compare Logical (CLR) (CL) (CLI) (CLC) .................. 174
AND (NR) (N) (NI) (NC) ................................. 175
OR (OR) (0) (01) (OC) ................................... 176
Exclusive OR (XR) (X) (XI) (XC) .......................... 177
Test Under Mask (TM) ...................................... 178
Insert Character (IC) ....................................... 179
Store Character (STC) ....................................... 180
Load Address (LA) .......................................... 181
Translate (TR) ............................................. 182
Translate and Test (TRT) .................................... 183
Edit (ED) .................................................. 184
Edit and Mark (EDMK) ..................................... 187
Shift Left Single Logical (SLL) .............................. 189
Shift Right Single Logical (SRL) ............................ 190
Shift Left Double Logical (SLDL) ........................... 191
Shift Right Double Logical (SRDL) .......................... 192
vi

BRANCHING
INSTRUCTIONS
FLOA TING-POINT
INSTRUCTIONS
OPTIONAL
FEATURES
APPENDICES
CONTENTS (Cont/d)
Page
Introduction ................................................ 193
Sequential Execution ....................................... " 193
Instruction Formats ......................................... 193
Interrupt Action. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 194
Branch on Condition (BCR) (Be) ........................... 195
Branch and Link (BALR) (BAL) ............................ 196
Branch on Count (BCTR) (BCT) ............................ 197
Branch on Index High (BXH) ............................... 198
Branch on Index Low or Equal (BXLE) ..................... 199
Execute (EX) .............................................. 200
Introduction ................................................ 201
Data Formats ............................................. " 201
Representation of Numbers ................................. " 202
Normalization ............................................... 202
Instruction Formats ......................................... 202
Condition Code
Utilization .................................. " 203
Interrupt Action ............................................ 204
Load (LER) (LE) (LDR) (LD) .............................. 205
Load
and Test (LTER) (LTDR) ............................. 206
Load Complement (LCER) (LCDR) .......................... 207
Load Positive (LPER) (LPDR) .............................. 208
Load Negative (LNER) (LNDR) ............................ 209
Add Normalized (AER) (AE) (ADR) (AD) ................. 210
Add Unnormalized (AUR) (AU) (AWR) (AW) .............. 212
Subtract Normalized (SER) (SE) (SDR) (SD) ............... 213
Subtract Unnormalized (SUR) (SU) (SWR) (SW) ............ 214
Compare (CER) (CE) (CDR) (CD) .......................... 215
Halve (HER) (HDR) ........................................ 216
Store (STE) (STD) ......................................... 217
Multiply (MER) (ME) (MDR) (MD) ......................... 218
Divide
(DER) (DE) (DDR) (DD) ............................ 219
Feature 5001-46 - Memory Protect ........................... 220
Feature 5002-46 - Elapsed Time Clock. . . . . . . . . . . .. . . . . . . . . . .. 220
Feature 5019-46 - Elapsed Time Clock. . . . . . . . . . . . . . . . . . . . . . .. 221
Feature 5003-46 - Direct Control ............................. 221
Feature 5040 -Selector Channel ............................. 221
Feature 5041- Selector Channel ............................. 221
Feature 5042 -Selector Channel ............................. 221
A -
Summary of Instructions ................................ 224
B -
Program Interrupts ................................... " 237
C - Input/Output Service Request ............................ 239
D -
Extended Binary-Coded-Decimal Interchange Code .......... 240
E - USA Standard Code for Information Interchange.. . . . . . . . .. 241
F -
Character Codes ........................................ 242
G -
Powers of Two Table ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 247
H- Hexadecimal-Decimal Number Conversion. .. .. . . . . . . .. .. . .. 248
I - Scratch-Pad Memory Layout and Register Assignments 253
vii

LIST OF TABLES
LIST OF
ILLUSTRA liONS
CONTENTS (Cont'd)
Page
Table 1. Basic Hexadecimal Marking System .................. 3
Table
2. Use of General Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 2A. Analysis of Model 70/46 Move Instruction Results ... 15
Table 2B. Analysis
of Overlapped and Non-Overlapped Fields of
Model 70/46 Move Instruction. . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Processor
State Registers ........................... 17
Table
4. Instruction Length Codes ........................... 17
Table
5. Interrupt State Identifier Codes . . . . . . . . . . . . . . . . . . . . . . 18
Table
6. Program Indicator Codes ........................... 19
Table
7. Register Addressing in Processor States . . . . . . . . . . . . . . . 21
Table 8. Interrupt Conditions and Priority ................... 22
Table
9. Interrupt Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Command Code Operations
......................... . 41
Table 11. Input/Output Channel Registers ..................... 45
Figure 1. Data Formats ................................... .
Figure 2. 70/46 Translation Flow ........................... .
Figure 3. Functional Logic of Automatic Interrupt ........... .
Figure 4. Functional Logic of Program Control Instruction ... .
Figure 5. Functional Logic of Start Device Instruction ........ .
Figure 6. Functional Logic of Halt Device Instruction ........ .
Figure 7. Functional Logic of Test Device Instruction ........ .
Figure 8. Functional Logic of Check Channel Instruction ...... .
Figure 9. Functional Logic of Servicing a Data Transfer ...... .
Figure 10. Functional Logic of End and Chaining Servicing .... .
Figure 11. Functional Logic of Interrupt Servicing ........... .
Figure 12. Dual-Processor Complex ........................... .
Figure 13. Master/Satellite Complex .......................... .
Figure 14. Maximum Multi-Processor Complex ................ .
viii
2
7
30
34
48
54
57
59
68
74
78
83
84
85

INSTRUCTION INDEX
The index marks at the right edge of this
page line up with similar index marks in the
text. By merely examining the page edges,
the reader can quickly locate a category of
instructions.
Appendix A summarizes the instruction
set for the 70/46 Processor, including timing,
formats and condition codes.
ix
Instruction Index
Privileged Instructions _
Processor State Control Instructions _
Fixed-Point Instructions _
Decimal Arithmetic Instructions _
Logical Instructions _
Branching Instructions _
Floating-Point Instructions _

INTRODUCTION
RCA MODEL 70/46
PROCESSOR
Compatibility
• The 70/46 Processor incorporates features which increase the efficiency
of the system for time-sharing use and for conventional batch processing.
This is accomplished by using main and subsidiary memory to create a
virtual memory of two million bytes. The virtual memory consists of
blocks of either 4,096 or 2,048 bytes which are called pages. An address
translation feature translates the addresses of the virtual memory pages
into actual addresses as assigned in
working memory by the operating
system. The translated actual addresses are then stored in a translation
memory which is used to implement the virtual memory.
The
70/46 Processor is a halfword-organized, variable-format processor
consisting
of main memory, nonaddressable main memory, scratch-pad
memory,
translation memory, read-only memory, program control and
arithmetic unit, input/output control, and a program interval timer.
The 70/46 provides multiprogramming with multiaccess time-sharing
capabilities.
User programs may run interactively at remote terminals or sequen-
tially under the automatic control of a job stream monitor where the
presence of the user is not required. The 70/46 also features an efficient
technique
for the handling of I/O data transfer through the reduction in
processing interference during I/O selector channel operations, and an
increase in the I/O transfer rate capability.
The Time Sharing Operating System, which is used with the 70/46
Processor, consists of a set of control routines, language processors, and
service routines which enable the complete system to provide efficient
batch processing concurrently with time-sharing operations from remote
terminals.
• All instructions, character codes, interrupt facilities, formats, and pro-
gramming features are functionally the same as corresponding features
on the 70/35, 70/45, and 70/55 Processors. Programs can be interchanged
between processors provided that:
1. Systems features are equivalent (Emulator features are not pro-
vided).
2. Programs are written to be independent of strict timing considera-
tions.
3.
Programs are restricted to specified functions and do not use unspeci-
fied characteristics peculiar to the hardware of either processor.
4. Program interrupts does not occur where an instruction is terminated
with unpredictable results.
5. Programs are written subject to all specified compatibility restric-
tions.
1

I:
32 Bits
Word
64 Bits
Double Word
Word
t=
~~I~~:~d I Halfword Halfword ,I
Byte -Byte ~ Byte - Byte -I-- Byte --r:- Byte ~
o 718 15116 23124 31 32 39140 47148
I Halfword Fixed-Point No. I I
151 I I I
Integer
Fullword Fixed-Point No. I I I
1
S
Inteqer
Sho" FloaHL.paint Na. I
1 7
S Character Fraction
I
ILOng Floatin~.Point Na. I I
1 7
S
Character
Ipacked Deci~al Numbe, I
31
I I
I I
24
I I
I I
Fraction
L-D_i..::,9_i:_IL-D_i..::,9_it4 .......... D--=i9'-i: ..... 1 ~ ] ~ J Di9i: Di9it
4
1 Di9it
4
Di9i:Lign
4
I Zoned Decimal Number
I Fixed-Length Logical Information
I
32
Logical Data
Introduction
Halfword -----t
Byte __ Byte _
55156 63
56
4
it
I
variable Length Logical Information
I Cha,acte,
8I
Cha,acte, 8
- - - - -....-.-----:8,....,
N-OTE: Numbers in upper right corners of blocks
indicate number of bits used.
Figure 1. Data Formats
2
Character

ORGANIZATION
OF DATA
Bit
Byte
Halfword
Word
Doubleword
Item/Field
Record
DATA FORMATS
NUMBERING
SYSTEM
Introduction
• The following definitions describe the various levels of data organiza-
tion
for the 70/46 Processor:
• A bit is a single binary digit having the value of either zero or one.
• A byte consists of eight information bits. It represents two decimal
digits, one alphabetic
character, or one special symbol.
• A halfword consists of two consecutive bytes beginning on a main
memory location that is a multiple of two.
• A word consists of four consecutive bytes beginning on a main
memory location that is a mUltiple of four.
• A doubleword consists of eight consecutive bytes beginning on a main
memory location that is a multiple of eight.
• An item/field consists of any number of bytes that specify a particular
unit of information (numeric field, alphabetic name, street address, stock
number,
etc.).
• A record consists of one or more related items.
• The basic unit of information in the 70/46 Processor is a byte, which
is
the smallest addressable unit. A byte consists of eight information bits.
The
parity bit ensures the accuracy of all bytes accessed by the processor.
Odd parity is used in the 70/46 Processor.
The internal code representation in the 70/46 is either the Extended
Binary-Coded-Decimal Interchange Code (EBCDIC) or the USA Standard
Code for Information Interchange (USASCII) as specified by program.
(See Appendices D and E.)
There are eight distinct formats for data in main memory (see figure
1). Further explanation of each format appears in the instruction sections
of this manual.
• Since binary addresses are cumbersome to work with, the hexadecimal
numbering system has been adopted to represent characters and addresses
in the 70/46 Processor. The hexadecimal system has a base of 16. The
first
ten marks are represented by decimal numbers zero (0) through
nine (9); the last six marks are represented by the letters A through F.
The basic hexadecimal marking system and its binary and decimal
equivalent
are specified in table 1. (See Appendix H.)
Table 1. Basic Hexadecimal Marking System
Hexadecimal
Binary
Decimal Hexadecimal
Binary Decimal
(Base 16)
(Base 21
(Base 10) (Base 16) (Base 2) (Base 10)
0 0000 0 8
1000
8
1 0001 1 9 1001 9
2 0010 2 A 1010 10
3
0011
3 B
1011 11
4 0100
4 C
1100 12
5 0101 5 D
1101
13
6
0110
6 E
1110
14
7
0111
7 F
1111 15
3

SYSTEM
STRUCTURE
MAIN MEMO'RY
NON-ADDRESSABLE
MAIN MEMORY
SCRATCH-PAD
MEMORY
• The main memory of the RCA 70/46 Processor is the central storage
for both data to be processed and the controlling instructions. Main memory
consists of planes of magnetic cores, with each core representing one
binary digit. The smallest addressable unit of information in main memory
is one byte (eight bits). The first 128 locations of main memory are
reserved for processor use and must not be used by the program.
The basic cycle time of the 70/46 Processor is the time required to
access
and transfer a halfword from main memory to the memory register
and regenerate the information in main memory. The memory cycle time
is 1.44 microseconds, and memory is available in a 262 KB module.
• A non-addressable main memory, is in addition to main memory and
cannot be addressed by programming. It contains the subchannel registers
that control the operation of input/output devices on the mUltiplexor
channel. A
set of three 32-bit registers services each device on the multi-
plexor channel; 256 subchannel
register sets and devices can be connected
to
the multiplexor channel.
• The scratch-pad memory is a micromagnetic storage device consisting
of 128 four-byte words, the cycle time of which is 300 nanoseconds. Each
word is scratch-pad memory is uniquely addressed.
The following
registers are contained in scratch-pad memory. (See
also Appendix 1.) :
1. Processor Utility Registers -All locations designated as processor
utility registers are used by the processor for program control and
cannot be used by the program.
2. General Registers -These locations are the general registers for
each processor state. These registers are used by the program for
base addressing, for indexing, or for storing operands.
Note: The 70/46 Processor has four processor states that pertain
to system and program interrupts.
3. Interrupt Mask Registers - An Interrupt Mask register for each
processor
state permits or inhibits 32 interrupt conditions.
4. Interrupt Status Registers - An Interrupt Status register for
each processor state stores interrupt identification information and
operational control information. This register contains indications
of the last state interrupted, the protection key, the decimal mode
(USASCII or EBCDIC), the privileged mode hit, and the supervisor
call identification.
4

SCRATCH-PAD
MEMORY
(Cont'd)
TRANSLATION
MEMORY
System Structure
5. Program Counter -A Program Counter for each processor state
contains the main memory address of the next instruction to be
executed,
the condition code, the instruction length code, and the
program mask.
6. Input/Output Channel Registers -A set of four registers for each
selector channel controls
input/output operation. A set of four
registers for the multiplexor channel controls initiation and ter-
mination of input/output operations on the multiplexor channel.
7. Floating-Point Registers - Four floating-point registers (each is
two words long)
are used in floating-point arithmetic.
8. Interrupt Flag Register -One Interrupt Flag register is provided.
When
an interrupt condition occurs, a bit associated with this con-
dition is
set in the Interrupt Flag register.
• The Translation Memory is a magnetic storage device consisting of
512
halfwords (1,024 bytes), the cycle time of which is 300 nanoseconds.
Each halfword (two bytes) in the translation memory is uniquely addressed
and contains a translation table element which is used in translating
virtual addresses to actual addresses (see figure 2).
The translation table which is maintained in the translation memory
is loaded
and stored from and to main memory by special EO (Elementary
Operation) routines. It is addressed during each main memory address-
ing cycle when translation is required. Address translation does not require
additional instruction time from that required by the basic 70/45 timing;
however, staticizing time for the SS-Format Load Multiple and Execute
instructions is increased when operating in 70/46 Mode.
Each element of the table consists of 17 bits (16 data bits plus 1
parity bit).
Bits
xxx REAL PAGE
o 2 3 4 5 6 8 9 14 15
P = Parity bit.
W = Written Into Bit: indicates, when set, that the page addressed in
memory by
this translation word has been written into. This bit
indicates, when reset, that the page has not been written into.
This \bit is
set and reset by the processor.
G = Accessed Bit: indicates, when set,
that the page addressed in
memory by
this translation word has been accessed (read, or
written into). This bit indicates, when reset, that the page has
not been accessed. This bit is set and reset by the processor.
Attempted but unsuccessful access to a page does not set this bit.
U = Utilization Bit: indicates, when set, that the addressed transla-
tion word can be utilized. This bit indicates, when reset, that the
addressed translation word cannot'be utilized and a Paging Queue
Program Interrupt condition occurs. This bit is set and reset by
the program.
5

TRANSLATION
MEMORY
(Cont'd)
Notes
READ-ONLY
MEMORY
PROGRAM
CONTROL AND
ARITHMETIC UNIT
Syste'Jn Structure
S = State Bit: indicates, when set, that the addressed page is non-
privileged. When
this bit is reset, it indicates that the addressed
page is privileged. When this bit is reset and the nonprivileged
bit in the ISR is set, a Paging Error Program Interrupt condition
occurs.
This bit is set and reset by the program.
E = Executable Bit: indicates, when set, that the page addressed in
memory by this translation word can be read as an operand or
instruction, but cannot be written into. If a program attempts to
write into a page with this bit set in the translation word, a
Paging Error Program Interrupt condition occurs. This bit
indicates, when reset, that the page addressed in memory can
be executed,
read or written into. This bit is set and reset by
the program.
M = Page Control Bit: indicates, when set, that a 2,048-byte page is
referenced. This
bit indicates, when reset, that a 4,096-byte page
is referenced.
If the high-order bit of the displacement field is
set and M is set, a Paging Error Program Interrupt condition
occurs. This
bit is set and reset by the program.
H = Page Address Bit: indicates, when set, and M is set, the high-order
address (2,048 bytes of a 4,096 byte page). This bit indicates,
when
reset and M is set, the low-order address (2,048 bytes of a
4,096 byte page). This bit is ignored if M is reset. This bit is set
and reset by the program.
XXX bits are for future expansion and must be zeros (program
restriction) .
• 1. The G condition is provided as a program flag to indicate written
into and/or accessed, respectively. A first time Read or Write to a
page would cause
the G bit to be set.
2. This translation memory is provided in addition to the 128-word
memory used
in scratch pad.
3. Addresses used in
I/O servicing and I/O data transfer are direct
and do not go through translation.
• Three banks of Read-Only Memory (ROM) are standard on the Model
70/46 Processor. Each ROM bank consists of 2,048 56-bit words (each
containing one micro-instruction of 53-bit [plus 3 parity bits] length).
In addition each ROM contains a 12-bit address register and a 54-bit
memory register.
The wired-in microprogranl logic contained in the first read-only
memory
bank controls the elementary operations when in the 70/45 or
70/46 Mode. The effective cycle time of the ROM banks is 480 nanoseconds
with a 56-bit access.
Although
the Read-Only Memory is a standard feature in the 70/46,
it is not accessible by programming and the programmer need not be
familiar with the detailed method of operation of the ROM.
• The
program control and arithmetic unit in the Model 70/46 Processor
interprets and executes the instructions stored in main memory. Registers
and indicators monitor the sequence of operations, perform automatic
accuracy checks, and communicate with the RCA standard interface in
the control of input/output devices.
6

-1
o
WRITTEN
INTO
BIT
ACCESSED
BIT
2
UTILIZ-
ATION
BIT
3
STATE
BIT
TRANSLATION MEMORY
512 BYTE LOCATIONS
16 BITS + PARITY
4
EXECUTE.
ABLE
BIT
5
PAGE
CONTROL
BIT
-----------------~----------------
CONTROL
6
BBB
24-BIT EFF ECTIVE ADDRESS, OR 24-BIT
VIRTUAL ADDRESS DURING
FETCH OR EXECUTE
Q D
BIT
SEGMENT
5 BITS
PAGE IDISPLACEMENT.
6 BITS 12 BITS
INTERRUPT
IF NOT
B B
8 9 14
PAGE
~
1
DECODER
I
PAGE
ADDRESS
BIT
L
15
o 17
Figure 2. 70/46 Translation Flow
18 -BIT ACTUAL ADDRESS
OF INSTRUCTION OR
OPERAND
t/:l
~.
~
<:-t-
(1:)
~
t/:l
<:-t-
~
(')
<:-t-
~
(1:)

INPUT /OUTPUT
CONTROL
INTERVAL TIMER
System Structure
• The RCA 70/46 Processor communicates with all input/output devices
through the RCA standard interface.
The
70/46 Processor can have up to four selector channels (optional).
Each selector channel contains two standard interface trunks. Each stand-
ard interface trunk controls one device subsystem (from 1 to 16 devices).
All selector channels can operate simultaneously.
In addition to the selector channels, a multiplexor channel is standard
equipment on the 70/46 Processor.
The multiplexor channel on
the 70/46 contains eight standard interface
trunks. Each trunk controls one device subsystem. All trunks on the multi-
plexor channel can
operate simultaneously. Also, the multiplexor channel
and all selector channels can operate simultaneously.
• The 70/46 has a variable 16-bit Interval Timer which can be set and
read by the program. Upon being set to a nonzero value, the least significant
bit position of the timer is decremented by one every 100 microseconds
until
its count becomes zero. Further decrementing is suppressed and the
Interval Timer (Flag Position 12) interrupt is effected, subject to the
corresponding mask. The Interval Timer runs when set to a nonzero
value; otherwise
it does not run. 'The decrement of the count occurs such
that the total elapsed time is never less than the count set in the Interval
Timer. The maximum possible time interval is not greater than 100 micro-
seconds more
than the loaded count. This timer is not available to 70/35,
70/45,
and 70/55 programs.
The
Interval Timer is an independent unit capable of being read and
loaded by Special Functions. Decrementation occurs simultaneously with
processing and causes no interference to either processing (except for
program interrupt upon lapse of count) or I/O servicing. When the proces-
sor is halted, the Interval Timer decrementing is stopped. General reset
causes the Interval Timer to be reset to zero.
Note: Use of the Interval Timer and Diagnostic Snapshot by programs
may not occur together because the Counter register is common
to both. If the Diagnose function is initiated while the Interval
Timer is running, the shared counter is cleared to zero without
occurrence of the Interval Timer interrupt and the Diagnose func-
tion assumes control
of the counter. If the function being diagnosed
is
the Load Interval Timer, the actual loading of the counter is
inhibited
but the E/O Flow is diagnosed.
8

INSTRUCTION
FORMATS
RR FORMAT
RX FORMAT
RS FORMAT
• The five basic instruction formats express, in general terms, the opera-
tion
to be performed as follows:
RR =
register-to-register
RX = register-to-indexed main memory
RS = register-to-main memory
SI = main memory and immediate operand operation
SS = main memory to main memory
The
instruction subfields are defined as follows:
Rl1 R2 , Ra -four-bit general register designation used for an operand
X2 - four-bit general register designation used for indexing
Bl,
B2 - four-bit general register designation used for base
addressing
DI, D2 -12-bit displacement
12 -eight-bit immediate operand
Lh L2 - four-bit operand length specification
L - eight-bit operand length specification
M - eight-bit
mask
Before executing the Load Multiple, Store Multiple, and the SS format
instructions, an address look-up is performed to insure that all pages
referenced can be utilized.
The time required for this address look-up is
in addition to regular staticizing time. If T = 1 (70/46 Mode), the addi-
tional
time is required. If T = 0 (70/45 Mode), no additional time
is required.
• The contents of the general register specified by Rl is the first operand.
The contents of the general register specified by R2 is the second operand.
In floating-point operations, Rl designates the address of the floating-point
register that contains the first operand. R2 designates the floating-point
register that contains the second operand. The first and second operands
can be the same and are designated by identical Rl and R2 addresses.
Op Code
o 7 8 11 12 15
• The contents of the general register specified by Rl is the first operand.
To obtain
the address of the second operand, the contents of the general
registers specified by X2 and B2 are added to the D2 field. In floating-point
operations, Rl designates
the floating-point register that contains the
first operand.
Op Code
o 7 8 11 12 15 16 19 20
31
• The RS format is used by shift instructions, branching instructions,
and load/store multiple instructions.
Op Code
o 7 8 11 12
15 16 19 20 31
9

Shift Instructions
Branching Instructions
Load/Store Multiple
Instructions
SI FORMAT
SS FORMAT
Instruction Formats
• The contents of the general register specified by Rl is the first operand.
The contents
of the general register specified by B2 are added to the D2
field. The sum specifies the number of bits of shifting to be done by the
shift operation. The R3 field is ignored.
• The contents of the general register specified by Rl is the first operand.
The contents of the general register specified by B2 are added to the D2
field to obtain the branch address. 'The contents of the general register
specified by R3 is the third operand.
• The Rl and R3 fields specify the general register boundaries. The con-
tents of the general register specified by B2 are added to the D2 field to
obtain the main memory address of the second operand.
• The contents of the general register specified by Bl are added to the
contents of the Dl field to obtain the address of the first operand. The
second operand is the immediate eight-bit
byte in the 12 field of instruction.
Op Code
o 7 8
15 16 19
20 31
• The contents of the general register specified by Bl are added to the
contents of the Dl field to obtain the address of the leftmost byte of the
first operand. The Ll field specifies the number of additional bytes in
the operand that are to the right of the first operand address. To obtain
the second operand address, the contents of the general register specified by
B2 are added to the contents of the D2 field. The L2 field specifies the
number of additional bytes in the operand that are to the right of the
second operand address. The L field specifies the number of additional
bytes
that are to the right of the first and the second operand address.
I Op Coo. I L, L L, I B, I
o 7 8 11 12 15 16 19 20 31 32 35 36
47
Notes • 1. A zero appearing in the X2, Bl or B2 fields indicates an absence of
the corresponding address or shift-amount component. An instruc-
tion can specify the same general register both for address modi-
fication
and for operand location.
2. Address modification is completed before the execution of an
operation.
3. The results replace the first operand (except in Store Character
instruction, where the result replaces the second operand).
4. A variable-length result is never stored outside the field specified
by the address and length.
5. The contents of all registers and main memory locations not speci-
fied by
an instruction remain unchanged except for the Edit and
Mark instruction and the Translate and Test instructions. These
instructions automatically use
certain general registers as given
in table 2.
10

SS FORMAT
(Cont'd)
Table 2. Use of General Registers
Processor State.
Edit and Mark
P1.
GR 1
P2 GR 1
Pa GR 13
P4 GR 9
* Processor States are discussed on page 16.
11
Instruction Formats
Translate and Test
GR 1 and 2
GR 1 and 2
GR 13 and 14
GR 9 and 10