Rca Cosmac User manual

Microprocessor

Products

User Manual

for

the

COSMAC

Microprocessor

User Manual

for the

COS

MAC

Microprocessor

RCAISolid State DivisionISomerville, NJ 08876

by

RCA

Corporation

(All

rights reserved under Pan-American Copyright Convention)

Printed

in

USA/5-75

2

Information furnished

by

RCA

is

believed

to

be

accurate

and

reliable.

However,

no

responsibility

is

assumed

by

RCA

for

its

use;

nor

for

any

infringements

of

patents

or

other

rights

of

third

parties

which

may

result

from

its

use.

No

license

is

granted

by

implication

or

otherwise

under

any

patent

or

patent

rights

of

RCA.

Trademark(s) Registered ®

M,arca(s) Registrada(s)

Table of Contents

Page

No.

Introduction

General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Specific Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

System Organization

......................................................

8

COSMAC

Architecture

and

Notation.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Instructions and Timing.

..

. . . . . . .

..

. . . . . . . . .

..

. . . . . . . . . • . . . . . . . . . . . . . . . . . . . . 12

Instruction

Repertoire

Register Operations

......................................................

.

Memory Reference

.......................................................

.

ALU

Operations Using

M(R(X))

ALU

Operations Using M(R(P))

15

17

18

22

I

nput/Output

Byte Transfer

................................................

24

Branching.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Control

................................................................

27

Interrupt

Handling.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

Instruction

Utilization

...

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Memory

and Control Interface

Memory

Interface and

Timing

......................................

. . . . . . . . . 33

Control Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

I/O

Interface

Programmed

I/O

DMA

Operation

Interrupt

Control

Machine Code Programming

39

42

44

Sample System and Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Useful Instructions

with

X = P

...............

,..............................

51

Interru

pt

Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

51

Branching Between

Pages

..................................................

53

Subroutine Techniques 53

Common Program

Bugs.

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Appendixes:

A -

Instruction

Summary

..................................................

58

B - State Sequencing

.....................................................

60

C - COSMAC Interface and

................................................

61

Chip Connections

D - COSMAC

Timing

Summary

.............................................

62

Index

..................................................

'.

. . . . . . . . . . . . . . . . . . . 63

3

4

Foreword

The

RCA

Microprocessor

(COSMAC)

is

an

LSI

CMOS

8-bit

register-oriented

central

processing

unit.

It

is

suitable

for

use in a

wide

range

of

stored-program

computer

systems

and

products.

These

systems

may

be

either

special

or

general-purpose

in

nature.

This User Manual provides a

detailed

guide

to

the

COSMAC Microprocessor. It

is

written

for

electrical

engineers,

and

assumes

no

familiarity

with

computers.

It describes

the

microprocessor

architecture

and

its

set

of

simple, easy-to-use

instructions.

Examples are given

to

illustrate

the

operation

of

each

instruction.

For

systems

designers,

this

manual illustrates practical

methods

of

adding

external

memory

and

control

circuits. Because

the

processor

is

capable

of

supporting

input/output

(I/O) devices

in

polled,

interrupt-

driven,

and

direct-memory-access

modes,

detailed

examples

are provided

for

the

use

of

the

I/O

instructions

and

the

use

of

the

I/O

interface

lines.

The

latter

include

direct-memory-access

and

interrupt

inputs,

external

flag

inputs,

command

lines, processor

state

indicators,

and

external

timing

pulses.

This manual also describes

machine-code

programming

methods

and

gives

detailed

examples.

Potential

programming

errors

are discussed,

and

various

programming

techniques

are

described,

including

interrupt

response,

long

branch,

and

subroutine

linkage

and

nesting.

This basic

manual

is

intended

to

help design engineers

understand

the

COSMAC

Microprocessor

and

aid

them

in

developing

simpler

and

more

powerful

products

based on

microprocessors.

Users requiring infor-

mation

on

the

operation

of

the

RCA COSMAC

Microprocessor

software

support

system

should

refer

to

the

MPM-102

"Program

Development

Guide

for

the

COSMAC

Microprocessor".

6

7

Introd

uction

General

The COSMAC Microprocessor has been developed

and

tested

within RCA in a wide variety

of

appli-

cations. COSMAC

is

suitable for use

in

business,

education,

entertainment,

instrumentation,

control,

communications,

and

other

applications where

stored

program

control

is

desired.

The

RCA COSMAC Microprocessor

is

a CMOS

byte-oriented

central processing

unit

(CPU). It

is

suitable

for use

in

a wide range

of

stored-program

computer

systems

or

products.

These systems can be

either

special

or

general-purpose in

nature.

They

are

byte-oriented,

a

byte

being eight bits.

COSMAC

operations

are specified by sequences

of

one-byte

operation

codes

stored

in a

memory.

These

operation

codes are called instructions. Sequences

of

instructions,

called programs,

determine

the

specific

behavior

or

function

of

a COSMAC-based system. System

functions

are easily changed

by

modifying

the

program(s)

stored

in

memory.

This ability

to

change

function

without

extensive

hardware

modification

is

the

basic advantage

of

a

stored-program

computer.

Reduced

cost

results

from

using identical

hardware

components

(memory

and

microprocessor)

in

a variety

of

different

systems

or

products.

The COSMAC microprocessor includes all

of

the

circuits required

for

fetching,

interpreting,

and

exe-

cuting

instructions

which have been

stored

in

standard

types

of

memories. Extensive input/output

(I/O)

control

features are also provided

to

facilitate

system

design.

Microprocessor

cost

is

only

a small

part

of

total

system

or

product

cost.

Memory,

input,

output,

power-

supply,

system-control,

and

programming costs are also major considerations. A

unique

set

of

COSMAC

features

combine

to

minimize

the

total system cost.

COSMAC's low-power, single-voltage CMOS

circuitry

minimizes power-supply

and

packaging costs.

High noise

immunity

and

wide

temperature

tolerance

facilitate use

in

hostile

environments.

COSMAC

compatibility

with

standard,

high-volume memories assures

minimum

memory

cost

and

maximum

system

flexibility

for

both

current

and

future

applications. Program storage

requirements

are

reduced by means

of

an efficient

one-byte

instruction

format.

The 40-pin COSMAC system interface

is

designed

to

minimize external I/O and

memory

control

circuitry. A single-phase clock, internal direct-memory-access (DMA)

mode,

flexible I/O

instructions,

program

interrupt,

program load

mode,

and

static

circuitry

are

other

COSMAC

features

explicitly

aimed

at

total

system

cost

reduction.

COSMAC does

not

require an external

bootstrap

ROM.

Microprocessor programming

is

facilitated

by

a variety

of

support

programs

or

software.

Extensive

support

software

and

support

hardware are available

for

use

in

developing COSMAC systems. Machine-

language programming

is

sometimes

indicated

when

only

a

few

short

programs need

to

be developed.

COSMAC provides a

set

of

efficient, easy-to-Iearn

instructions

which

are simple

to

use.

The COSMAC microprocessor comprises

two

conservatively designed LSI chips (one 40-pin

and

one

28-pin dual-in-line package).

Appendix

C shows

the

required

interconnections

for

these

two

LSI

chips

and

summarizes

the

COSMAC

system

interface signals.

8

User

Manual for the

Specific Features

The advanced features and

operating

characteristics

of

the

RCA

COSMAC

Microprocessor

include:

• static

COS/MOS

circuitry,

no

minimum

clock

frequency

•

full

military

temperature

range

• high noise

immun

ity,

wide

operating-voltage range

•

TTL

compatibility

•

8-bit

parallel

organization

with

bidirectional

data bus

•

built-in

program-load

facility

•

any

combination

of

standard

RAM/ROM

via

common

interface

•

direct

memory

addressing

up

to

65,536

bytes

•

flexible

programmed

I/O

mode

•

program

interrupt

mode

•

on-chip

DMA

facility

•

four

I/O

flag

inputs

directly

testable

by

branch

instruction

•

one-byte

instruction

format

with

two

machine cycles

for

each

instruction

•

59

easy-to-use

instructions

• 16 x

16

matrix

of

registers

for

use

as

multiple

program counters, data

pointers,

or

data registers

System Organization

Fig. 1

illustrates

a

typical

computer

system

incorporating

the

COSMAC

microprocessor.

Operations

that

can

be

performed

by

COSMAC

include:

a)

control

of

input/output

(I/O)

devices,

b)

transfer

of

binary

data between

I/O

and

memory

(M),

c)

movement

of

data bytes between

different

memory

locations,

d)

interpretation

or

modification

of

bytes stored in

memory.

N

(41

I/O

____

jr

CPU

______

J

TIMING

B MSC.

STATE

CODE

(21

DEPENDING

ON

RAMIROM

SYSTEM

65536

TIMING

(21

BYTES

COS

MAC CONTROL

MAX.

MWRITE

DMA/INT.

(31 CKTS

FLAGS

(41

1/0

DEVICES

DATABUS(BI

92C5-

26554

Fig. 1 -

Block

diagram

of

typical

computer

system using

the

COSMAC

microprocessor.

COSMAC Microprocessor

_____________________________

_ 9

For example, COSMAC can control

the

entry

of

binary-coded decimal numbers

from

an

input

keyboard

and

store

them

in

predetermined

memory

locations. COSMAC can

then

perform

specified

arithmetic

operations

using

the

stored

numbers

and

transfer

the

results

to

an

output

display

or

printing device.

System

input

devices may include switches,

paper-tape/card

readers, magnetic-tape/disc devices, relays,

modems, analog-to-digital converters,

photodetectors,

and

other

computers.

Output

devices may include

lights,

CRT

/lED/liquid-crystal

devices, digital-to-analog converters, modems, printers,

and

other

computers.

Memory can comprise

any

combination

of

RAM

and

ROM

up

to

a

maximum

of

65,536

bytes. ROM

(Read-Only Memory)

is

used

for

permanent

storage

of

programs, tables,

and

other

types

of

fixed

data.

RAM

(Random-Access Memory)

is

required for general-purpose

computer

systems which require

frequent

program

changes.

RAM

is

also required

for

temporary

storage

of

variable

data.

The

type

of

memory

and

required

storage

capacity

is

determined

by

the

specific application

of

the

system.

Bytes are

transferred

between ·1/0 devices,

memory,

and

COSMAC by means

of

a

common,

bidirectional

eight-bit

data

bus.

Fifteen COSMAC I/O

control

signal lines are provided. Systems can use

some

or

all

of

these signals

depending

on

required I/O sophistication. A

four-bit

N

code

is

generated by

the

COSMAC

input/output

instruction.

It

can be used

to

specify an I/O device

to

be involved in an I/O-memory

byte

transfer

by means

of

the

data

bus,

or,

alternatively,

to

specify

whether

an I/O

byte

represents

data,

an I/O device selection

code, an I/O

status

code,

or

an I/O

control

code.

Use

of

the

N

code

to

directly

specify an I/O device

permits simple, inexpensive

control

of

a small

number

of

I/O devices

or

modes. Use

of

the

N

code

to

specify

the

meaning

of

the

word

on

the

data

bus facilitates systems incroporating a large

number

of

I/O devices

or

modes.

Four

I/O flag

inputs

are provided. I/O devices can activate these

inputs

at

any

time

to

signal COSMAC

that

a

byte

transfer

is

required,

that

an

error

condition

has

occurred,

etc.

These flags can also be used

as

binary

input

lines if desired.

They

can be

tested

by COSMAC instructions

to

determine

whether

or

not

they

are active. Use

of

the

flag inputs

must

be

coordinated

with

programs

that

test

them.

A program

interrupt

line can be activated

at

any

time

by I/O circuits

to

obtain

an

immediate

COSMAC

response.

The

interrupt

causes COSMAC

to

suspend its

current

program sequence

and

execute

a prede-

termined

sequence

of

operations

designed

to

respond

to

the

interrupt

condtion.

After servicing

the

inter-

rupt,

COSMAC resumes

execution

of

the

interrupted

program. COSMAC

can

be made

to

ignore

the

inter-

rupt

line by resetting its

interrupt-enable

flip-flop (IE).

Two additional I/O lines are provided

for

special

types

of

byte

transfer

between

memory

and

I/O devices.

These lines are called direct-memory-access (DMA) lines. Activating

the

DMA-in line causes an

input

byte

to

be immediately

stored

in a

memory

location

without

affecting

the

COSMAC program being

executed.

The

DMA-out line causes a

byte

to

be immediately

transferred

from

memory

to

the

requesting

output

circuits. A

built-in

memory

pointer

register

is

used

to

indicate

the

memory

location

for

the

DMA cycles.

The

program

sets this

pointer

to

an initial

memory

location. Each DMA

byte

transfer

automatically

increments

the

pointer

to

the

memory

location.

Repeated

activation

of

a DMA line can cause

the

transfer

of

any

number

of

consecutive

bytes

to

and

from

memory

independent

of

concurrent

program

execution.

I/O device circuits can cause

data

transfer

by

activating a flag line,

the

interrupt

line,

or

a DMA line. A

program

must

sample a flag line

to

determine

when

it

becomes

active. Activating

the

interrupt

line causes an

immediate COSMAC response regardless

of

the

program

currently

in

progress, suspending

operation

of

that

program. Use

of

DMA provides

the

quickest

response

with

least

disturbance

of

the

program.

A

two-bit

COSMAC

state

code

and

two

timing

lines are provided

for

use

by

I/O device circuits. These

four

signals

permit

synchronization

of

I/O circuits

with

internal COSMAC

operating

cycles.

The

state

code

indicates

whether

COSMAC

is

responding

to

a

DMA

request,

responding

to

an

interrupt

request,

executing

10

__________________________________

User Manual

for

the

an

input/output

instruction,

or

none

of

thp.se. The

timing

signals are used

by

the

memory

and

I/O systems

to

signal a new processor

state

code,

to

latch

memory

address bits,

to

take

memory

data

from

the

bus,

and

to

set

and

reset

I/O

controller

flip-flops.

Bytes are

transmitted

to

and

from

memory

by

means

of

the

common

data

bus. COSMAC provides

two

lines

to

control

memory

read/write

cycles. During a

memory

write

cycle,

the

byte

to

be

written

appears

on

the

data

bus

and

a

memory

write pulse

is

generated

by

COSMAC

at

the

appropriate

time.

A

memory

read

level

is

generated

which

is

used by

the

system

to

gate

the

memory

output

byte

onto

the

common

data

bus.

COSMAC provides eight

memory

address

lines. These eight lines

supply

16-bit

memory

addresses in

the

form

of

two

successive 8-bit bytes. The more significant (high-order) address

byte

appears

on

the

eight

address lines first, followed by

the

less significant (low-order) address

byte.

The

number

of

high-order bits

required

to

select a

unique

memory

byte

location

depends

on

the

size

of

the

memory.

For

example,

a

4096-byte

memory

would

require a 12-bit address. This 12-bit address

is

obtained

by

combining

4 bits

from

the

high-order address

byte

with

the

8 bits

from

the

low-order address

byte.

One

of

the

two

COSMAC

timing

pulses

strobes

the

required high-order bits

into

an address latch (register)

when

they

appear

on

the

eight

address lines. An internal COSMAC register holds

the

eight

low-order address bits

on

the

address lines

for

the

remainder

of

the

memory

cycle. No

external

latch circuits are required

for

the

low -order address

byte.

Three

additional

lines

complete

the

COSMAC microprocessor

system

interface. A single-phase

clock

input

determines

operating

speed.

The

external clock may be

stopped

and

started

to

synchronize

COSMAC

operation

with

system

circuits if desired. A single clear

input

initializes internal COSMAC

circuitry

in

one

step.

The

load signal line holds

the

COSMAC microprocessor in

the

program load

mode.

The

use

of

this

mode

is

discussed

in

the

section

on

Memory

and

Control

Interface.

COSMAC

Architecture

and

Notation

Fig. 2 illustrates

the

internal

structure

of

the

COSMAC microprocessor. This simple,

unique

architecture

results in a

number

of

system

advantages. The COSMAC

architecture

is

based on a register array

comprising

sixteen general-purpose 16-bit

scratchpad

registers. Each

scratchpad

register, R,

is

designated by a

4-bit

binary

code.

Hexadecimal (hex)

notation

will be used here

to

refer

to

4-bit

binary

codes.

The

16

hexa-

decimal digits (0,1,2,...E,F)

and

their

binary equivalents

(0000,0001,0010,

...

,1110,1111)

are listed in

Appendix

A.

Using hex

notation,

R(3) refers

to

the

16-bit

scratch

pad register

designated

or

selected by

the

binary

code

0011.

R(3).0 refers

to

the

low-order (less significant) eight bits

or

byte

of

R(3). R(3).1 refers

to

the

high-

order

(more significant)

byte

of

R(3).

Three

4-bit

registers labeled N, P,

and

X hold 4-bit binary

codes

(hex digits)

that

are used

to

select

individual 16-bit

scratch

pad registers.

The

16

bits

contained

in

a selected

scratch

pad can be

copied

into

the

16-bit A register.

The

two

A-register

bytes

are sequentially placed

on

the

eight

external

memory

address

lines

for

memory

read/write

operations.

Either

of

the

two

A-register

bytes

(A.O/A.1) can also be gated

to

the

8-bit

data

bus

for

subsequent

transfer

to

the

D register.

The

16-bit

val

ue in

the

A register can also be

incremented

or

decremented

by

1

and

returned

to

the

selected

scratch

pad register

to

permit

a

scratch

pad

register

to

be used as a

counter.

The

notation

R(X), R(N),

or

R(P)

is

used

to

refer

to

a

scratchpad

register selected

by

the

4-bit

code

in

X,

N,

or

P, respectively. Fig. 3 illustrates

the

transfer

of

a scratchpad register

byte,

designated by

N,

to

D.

The

left half

of

Fig. 3 illustrates

the

initial

contents

of

various registers (hex

notation).

The

operation

performed

can be

written

as

R(N)_O

-7

D

This expression indicated

that

the

low-order 8 bits

contained

in

the

scratch

pad register designated

by

the

hex digit in N are

to

be placed

into

the

8-bit

D register. The designated

scratch

pad register

is

left

unchanged.

COSMAC Microprocessor

_____________________________

11

MEMORY

ADDRESS

(4)

R SELECT

SCRATCH

PAD

'"":&-.....,,"""~:-i

-REG

ISTE

RS

R(9).1

R(9).0

R

R(

AU

R(A).O

R(E).I

R(F).I

(8)

I/O

BI-DIRECTIONAL

COMMAND

DATA

BUS

(8)

8

-BIT

BUS

92CM-26420

Fig. 2 - Internalstructure

of

the COSMAC microprocessor.

The right half

of

Fig. 3 illustrates

the

contents

of

the

COSMAC registers

after

this

operation

is

completed.

The following sequence

of

steps

is

required

to

perform this

operation:

1)

N

is

used

to

select

R.

(left half

of

Fig. 3)

2) R(N)

is

copied into A. \

3)

A.O

is

gated

to

the

bus.

4) The bus

is

gated

to

D.

(right half

of

Fig. 3)

~

A - - -N 2 A

01

25

f---

N 2

p 0 p 0

A.O

X 3 X 3

I -

RIOI

--

Rill

--

IALU

I-

I I -

RIO)

- -

R(ll

--IALU I- I

•

RI2J

01

25

~

DF=

R(2)

01

25

I--

DF=

R(3) --ID I- I

R(31

- - D 25

I-

25

Fig. 3 -

Use

of

N designator

to

transfer data

from

scratchpadregister R(2) to the D register.

12

__________________________________________________

__

User Manual

for

the

Memory or I/O data used

in

various COSMAC operations are transferred by means

of

the

common

data

bus. Memory cycles involve

both

an address and

the

data

byte itself. Memory addresses are provided

by

the

contents

of

scratchpad registers. An example

of

a memory operation

is

M(R(X))

-+

D

This expression indicates

that

the

memory byte addressed by R(X)

is

copied into

the

D register. Fig. 4

illustrates this operation. The following steps are required:

1)

X

is

used

to

select

R.

~

(I.ft

,;d.

of

F;

•.

41

2)

R(X)

is

copied into A.

3)

A addresses a memory byte.

4) The addressed memory

byte

JI,;.h.

,;d.

of

F;

•.

41

is

gated

to

the

bus.

5)

The bus

is

gated

to

D.

Reading a byte from memory does

not

change

the

contents

of

memory.

A 00 02 N 3

6 p 0

l-

x 1

ADDRESS M I -

00

01

FF

R(O)

--

00 02

C5

R(l)

00 02

~

IALUI-

I

00

03

AA

R(2) --

DF=-

00

04

23

R(3)

--ID

I-

I

Fig. 4 - Transfer

of

data

from

memory

to

the D register.

The 8-bit arithmetic-logic

unit

(ALU

in

Fig. 2) performs arithmetic and logical operations. The

byte

stored

in

the

D register

is

one operand and

the

byte on

the

bus (obtained from memory)

is

the

second

operand. The resultant byte replaces

the

operand

in

D.

A single-bit register

data

flag (DF)

is

set

to

"0"

if no

carry results from an add, subtract, or shift operation. DF

is

set

to

"1"

if a carry does occur. The 8-bit D

register

is

similar

to

the

accumulator

found

in

many computers.

Instructions and

Timing

COSMAC operations are specified by a sequence

of

operation codes stored

in

external memory. These

code are called instructions. Each instruction consists

of

one 8-bit byte. Two 4-bit hex digits contained in

each instruction byte are designated

as

I and N, as shown

in

Fig. 5.

5A

(HEX)

I \

I N

10

1 0 1 I 1 0 1 0 I

,7654,

~

I

----.-

High Order Low-Order

Digit Digit

Fig. 5 -

Eight-bit

instruction format.

COSMAC Microprocessor

_____________________________

13

The

execution

of

each instruction requires

two

machine cycles. The first cycle fetches

or

reads

the

ap-

propriate instruction

byte

from memory and stores

the

two

hex instruction digits

in

registers I and

N.

The

values in I and N specify

the

operation

to

be performed during

the

second machine cycle. I specifies

the

in-

struction

type.

Depending upon

the

instruction, N

either

designates a scratchpad register, as illustrated

in

Fig. 3,

or

acts as a special code, as described

in

more detail below.

Instructions are normally executed

in

sequence. A program

counter

is

used

to

address successively

the

memory bytes representing instructions.

In

the

COSMAC microprocessor,

anyone

of

the

16-bit scratchpad

registers can be used as a program

counter.

The value

of

the

hex digit

contained

in

register P determines

which scratchpad register

is

currently being used, as

the

program

counter.

The

operations performed by

the

instruction fetch cycle are

M{R{P))

-+ I,N;R{P)+l

Fig. 6 illustrates a typical instruction

fetch

cycle. Register P has been previously

set

to

1, designating

R(1) as

the

current

program

counter.

During

the

instruction fetch cycle,

the

"0298"

contained

in

R(P)

is

placed

in

A and used

to

address

the

memory. The F4 instruction

byte

at

M (0298)

is

read

onto

the

bus and

then

gated into I and

N.

The value in A

is

incremented by 1 and replaces

the

original value

in

R{P).

The

next machine cycle will perform

the

operation

specified by

the

values

in

I and

N.

Following

the

execute

cycle,

another

instruction fetch cycle will occur.

R{P)

designates

the

byte

in sequence (56).

Alternately repeating instruction fetch

execute

cycles

in

this manner causes sequences

of

instructions

that

are stored

in

memory

to

be executed.

• A

02

98

I N 4

--

cb

I-

p 1

X 7

ADDRESS M

~

I F

02 97

46

R(O)

--

02

98

F4

r--

R(l)

02

99

-

~

02

99

56

R(2)

--DF

=-

02

9A 17

R(3)

--D -

A

02

98 N 6

cfu

-P 1

X 7

ADDRESS M I 4

02 97

46

R(O) --

02

98

F4

R(l)

02 98 -

IALul-

I

02 99

56

R(2)

--

DF=-

02

9A 17

R(3)

--ID I- I

~

F4

Fig. 6 - Typical instruction fetch cycle.

The COSMAC machine cycle during which an instruction

byte

is

fetched

from

memory

is

called

state

0

(SO).

The

cycle during which

the

fetched instruction

is

executed

is

called

state

1 (S1). During execution

of

a program, COSMAC alternates between SO and S1,

as

shown below:

...

ISO I

S1

ISO I

Sl

ISO I

S1

I

...

Each machine cycle

is

internally divided into eight equal time intervals, as illustrated

in

Appendix D

under general timing. Each

time

interval

is

equivalent

to

one

external

clock

cycle (T). The rate

at

which

machine cycles occur is,

therefore,

one-eight

of

the

clock frequency. The instruction

time

is

16T

or

two

machine cycles.

All

instructions require

the

same

fetch/execute

time.

14

Instruction

Repertoire

15

Each COSMAC instruction

is

fetched during SO

and

executed

during S1. The

operations

performed

during

the

execute

cycle

S1

are

determined

by

the

two

hex digits

contained

in I and

N.

These

operations

are divided

into

six general classes:

Register Operations -This group includes six instructions used

to

count

and

to

move

data

between

internal COSMAC registers.

Memory Reference -Two instructions are provided

to

load

or

store a

memory

byte.

ALU

Operations

-This

group

contains

fifteen instructions

for

performing

arithmetic

and logical

operations.

I/O

Byte Transfer -Eight instructions are provided

to

load

memory

from

I/O

control

circuits,

and

eight instructions

to

transfer

data

from

memory

to

I/O control circuits.

Branching -

Fourteen

different

conditional and unconditional branch instruction are provided.

Control -Six control instructions facilitate program

interrupt,

operand

selection,

or

branch

and

link

operations.

Each instruction

is

designated

by

its two-digit hex

code

and by a name. A description

of

the

operation

is

provided using a symbolic

notation.

A two- or three-letter abbreviated

name

is

also given. Examples are

shown

in

this section for most instructions. A

summary

of

the

instruction repertoire

is

given

in

Appendix

A.

It should be

noted

that

any unused machine codes, such as

"CN"

"31

",

"72",

"01

",

etc.,

are considered

illegal codes and should

not

be

used by users.

They

are reserved for

future

use by RCA.

Register Operations

11

N INCREMENT R(N)+1

INC

When 1=1,

the

scratchpad register specified by

the

hex digit

in

N

is

incremented

by

1.

Note

that

FFFF+1=0000.

A 02 FF

I--

N 3 A 02 FF

l-

N 3

p 0 p 0

+1

X 2

+f

x 2

I 1

RIOI

03

7A

Rill

01

32

IALU

I-

I • I 1

RIOI

03

7A

Rill

01

32

IALU

I-

I

RI21

- - DF

~-

RI21

--DF

~-

RI31

02

FF

f4-

ID I

AB

I

r-

R(31

03

00

l-

ID I

AB

I

Fig.

7 - Example

of

instruction

TN

-INCREMENT.

16

User Manual

for

the

2N DECREMENT

R(N)-l

DEC

When

1=2,

the

register specified by N

is

decremented by 1. Note

that

0000-1=FFFF.

A

01

32

~

N 1 A

01

32 -N 1

p 0 P 0

-T X 2

-1

X 2

•

2I

RWI

03 7B

Rill

01

32

4-

IALU

I-

I I 2

RWI

03 7B

-

Rill

01

31

~

IALul

-I

RI21

- -

DF

=-

RI21

- - DF

=-

RI31

03

00 I D IAB I

RI31

03 00 ID IAB I

Fig.

8 - Example

of

instruction

2N

-DECREMENT.

8N GET

LOW

R(N).O-+ D

When

1=8,

the

low-order

byte

of

the

register specified by N replaces

the

byte

in

the

D register.

A

01

31

-N 1 { A

01

31

-N 1

p 0 P 0

A.O X 2 X 2

I B

RIOI

03

7C

Rill

01

31

..

IALU

I-

I • I 8

RWI

03 7(:

Rill

01

31

f4-

IALU

I-

I

RI21

--

DF=

-

RI21

--

DF=-

RI31

03 00 I D IAB I

RI31

03 00 D

31

31 31

Fig. 9 - Example

of

instruction

8N

-

GET

LOW.

GET HIGH

R(N).l

-+

D GHI

When

1=9,

the

high-order byte of

the

register specified by N replaces

the

byte

in

the

D register.

A

72

00

~

N 3

~

A 72 00 . -N 3

p 0 p 0

A.l

X 2 X 2

I 9

RIOI

03 7D

Rill

01

31

IALU

I-

I • I 9

RIOI

03 7D

Rill

01

31

IALU

I- I

RI21

- -

DF

=-

RI21

--

DF=

-

RI31

72 00

f4-

I D I

31

I

RI31

72 00

.;-

D

72

72 72

Fig.

10

-Example

of

instruction

9N

-

GET

HIGH.

COSMAC Microprocessor

_____________________________

_ 17

PUT LOW

D--*

R(N).O PLO

When I=A,

the

byte

contained

in

the

D register replaces

the

low-order

byte

of

the

register specified

by

N.

~

A --

t--

N 2 A --

l-

N 2

p 0 p 0

X 2 X 2

A

I

RIOI

03 7E

R(1)

01

31

IALU

I-

I • I A

RIOI

03 7E

Rill

01

31

IALU

I-

I

RI21

00

I-

DF

~-

RI21

00

72

I-

DF

~-

RI31

72

00 D

72

RI31

72

00

D

72J--

72 1

72

Fig.

11

-Example

of

instruction

AN

-

PUT

LOW.

PUT HIGH

D--*

R(N).l

PHI

When I=B,

the

byte

contained

in

the

D register replaces

the

high-order

byte

of

the

register specified by

N.

-1

A - -

l-

N 2 A - -

l-

N 2

p 0 p 0

X 2 X 2

I B

RIOI

03

7F

Rill

01

31

IALU

I-

I • I B

RIOI

03

7F

Rill

01

31

IALU

I-

I

RI21

00 72

I+-

DF~

-

RI21

66 72

I+-

DF

~-

R131·

72 00 D 66

R(31

72 00 D 66 r-

66 t 66

Fig. 12 -Example

of

instruction

BN

-

PUT

HIGH.

Memory

Reference

LOAD

ADVANCE

M(R(N))

--*

D;

R(N)+1

When 1=4,

the

external

memory

byte

addressed

by

the

contents

of

the

register specified by N replaces

by

byte

in

the

D register.

The

original

memory

address

contained

in

R(N)

is

incremented

by 1.

The

contents

of

memory

are

not

changed.

A 00 19 -N 1

~

p 0

X 2

ADDKIoSS M I 4

00 17 12 R(oI

01

00

18

34

Rill

00 19 -

IALul-

I

A 00 19 -N 1

dJ

p 0

X 2

ADDRESS M I 4

00

17

12

RIOI

01 00

00 18 34

r-

RI11

01

lA

I--

IALU

I-I

•

00 19 56

RI21

00

17

DF

~-

00 19 56

RI21

00 17 DF

~-

00

lA

78

RI31

- - I D I F7 I 00

1A

78

R(31

--D

56..1-

t 56

Fig. 13 -Example

of

instruction

4N

-

LOAD

ADVANCE.

18

________________________________________________________________

User Manual

for

the

5N

STORE

D -i> M(R(N))

STR

When 1=5,

the

byte

in

D replaces

the

memory

byte

addressed

by

the

contents

of

the

register specified

by

N.

A 00

171

f-

N 2

cb

p 0

X 2

ADDHt:SS M

A 00

17

l-

N 2

6 p 0

X 2

ADDRESS M

I 5

00

17

12

RIOI

01 01

I 5

00

17

56

RIOI

01

00 18 34

Rill

00

lA

IALUI-

I 00 18

34

Rill

00

1A

IALul

-I

00 19 56

RI21

00

17

I-

DF

=-

00

19

56

RI21

00 17

r-

DF

=-

00

1A

78

RI31

--D

56

00 1A 78

RI31

--D

56]-

56 f

56

Fig. 14 -Example

of

instruction

5N

-STORE.

ALU

Operations Using

M(R(X))

In

this

group

of

instructions,

the

N

digit

of

the

instruction

is

a

code

specifying.a

specific

ALU

operation.

The

high-order bit

of

N

is

O.

The

X register

must

previously

have

been

loaded

(by an

instruction,

SET

X,

described

among

the

control

instructions).

In

general,

R(X)

points

at

one

operand,

D

is

the

other,

and

the

result

replaces

the

latter

in

the

D register.

FO

I LOAD

BY

X

M(R(X))

-i> D I LDX ]

When I=F

and

N=O,

the

memory

byte

addressed

by

the

contents

of

the

register

specified

by

X replaces

the

byte

in

the

D register. (This

instruction does

not

increment

the

address

as LOAD

ADVANCE

does.)

A

00

32

N

cb

0

p 0

l-

x 2

ADDHcSS M I F

00

30

01

RIOI

00

70

00

31

00

Rill

00

33

IALUI

-I

A 00 32 N 0

P 0

l-

x 2

F

I

RIOI

00 70

Rill

00 33

IALU

I-

I

•

ADDRESS M

00 30

01

00

31

00

00 32 92

RI21

00

32

-

DF

=-

00

32

72

RI21

00 32

I-

DF=

-

00 33

57

RI31

--I D 1

00

I 00

33

57

RI31

--D

92

Fig. 15 -Example

of

instruction

FO -

LOAD

BY

X.

F1

OR

M(R(X)) v D

-i>

D

OR

When I=F

and

N=1,

the

individual

bits

of

the

two

8-bit

operands

are

combined

according

to

the

rules

for

logical

OR

as

follows:

M(R(X))

a

D

a

OR(v)

a

COSMAC Microprocessor

19

The

byte

in D

is

one operand. The

memory

byte

addressed

by

R(X)

is

the second operand. The result

byte

replaces the D operand. This

instruction

can

be

used

to

set individual bits.

A 00 33 N 1

6 p 0

f-

1

X

ADDRESS M I F

00 30

01

RiOl 00

71

00

31

00

Rill

00

33 -ALU

(V)

r-

N

0

•

ADDRESS M

00 30

01

RIOI

00

71

00

31

00

Rll)

00 33

oo

32 92

RI21

00 32

OF

=-

t

00

32

92

R(2)

00

32

00 33

57

RI31

--D 92 00 33 57

R(3)

57

Fig. 16 -Example

of

instruction

F1

-OR.

F2

AND

M(R(X)).

D

-?-

D

AND

When

I=F

and N=2, the individual bits

of

the

two

8-bit

operands are combined according

to

the

rules

for

logical

AND

as

follows:

M(R(X))

D

AND(·)

o 0 o

o 0

The

byte

in D

is

one operand. The

memory

byte

addressed

by

R(X)

is

the

second operand. The result

byte

replaces the D operand. This

instructi~n

_~a~be

used

to

test

or

mask

individual

bits.

A 00 33 N 2

cb

P 0

f-

x 1

ADDH~SS

M I F

00

30

01

RIO)

00

71

00

31

00

Rill

00 33

I-

ALU I·)

00

32

92

R(2)

00

32

OF=-

f

00

33 57 R(3) --D 92

A N 2

cb

00

33

p 0

~

X 1

ADDRESS M I F

00 30

01

RIOI

00

71

00

31

00

Rll)

00 33

I-

~

00

32 92 R(2)

00

32

OF

=-

00 33

57

R13)

--D 12

• + 57

Fig.

17

-Example

of

instruction

F2

-

AND.

F3

EXCLUSIVE-OR

I

M(R(X))

Ell

D

-?-

D

XOR

When

I=F

and N=2,

the

individual bits

of

the

two

8-bit

operands are

combined

according

to

the

rules

for

logical

EXCLUSIVE-OR

as

follows:

M(R(X))

D

o 0

o 1

o

XOR(Ell)

o

RCA COSMAC User manual

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