RDC R8810LV User manual

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.2
Subject to change without notice 1
R8810LV
16-Bit RISC Microcontroller User’s Manual
RDC RISC DSP Controller
RDC Semiconductor Co., Ltd
http:\\www.rdc.com.tw
Tel. [phone]
Fax [phone]

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.2
Subject to change without notice 2
Contents
-----------------------------------------------------------------------page
- Features -------------------------------------------------------------------4
- Block Diagram ------------------------------------------------------------4
- Pin Configuration ---------------------------------------------------------5
- PQFP and LQFP Pin-Out Table --------------------------------------------------------------7
- Pin Description------------------------------------------------------------8
- Basic Application System Block-----------------------------------------13
- Oscillator Characteristics------------------------------------------------14
- Read/Write timing Diagram---------------------------------------------15
- Execution Unit------------------------------------------------------------17
= General Register ------------------------------------------------------17
= Segment Register------------------------------------------------------17
= Instruction Pointer and Status Flags Register ------------------------18
= Address Generation---------------------------------------------------19
- Peripheral Control Block Register -------------------------------------20
- System Clock Block ------------------------------------------------------22
- Reset-----------------------------------------------------------------------23
- Bus Interface Unit--------------------------------------------------------25
= Memory and I/O Interface --------------------------------------------25
= Data Bus --------------------------------------------------------------25
= Wait States ------------------------------------------------------------26
= Bus Hold --------------------------------------------------------------27
- Chip Select Unit ----------------------------------------------------------29
= UCS ------------------------------------------------------------------29
= LCS ------------------------------------------------------------------30
= MCSx ----------------------------------------------------------------31
= PCSx ----------------------------------------------------------------32
- Interrupt Controller Unit------------------------------------------------34
= Master Mode and Slave Mode -----------------------------------------34
= Interrupt Vector, Type and Priority -----------------------------------35
= Interrupt Request -----------------------------------------------------36
= Interrupt Acknowledge -----------------------------------------------36
= Programming Register------------------------------------------------37

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.2
Subject to change without notice 3
- DMA Unit-----------------------------------------------------------------50
= DMA Operation------------------------------------------------------50
= External Request-----------------------------------------------------55
- Timer Control Unit-------------------------------------------------------57
= Watchdog Timer----------------------------------------------------61
= Timer/Counter Unit Output Mode -----------------------------------62
- Asynchronous Serial Port -----------------------------------------------63
- Synchronous Serial Port -------------------------------------------------67
= Synchronous Serial Port Operation-------------------------------69
- PIO Unit-------------------------------------------------------------------71
= PIO Multi-Function Pin list Table -----------------------------------71
- PSRAM Control Unit----------------------------------------------------74
- Instruction Set Opcodes and Clock Cycle -----------------------------75
= R8810LV Execution Timings ---------------------------------------79
- DC Characteristics -------------------------------------------------------80
- AC Characteristics -------------------------------------------------------82
- Package Information-----------------------------------------------------91
- Revision History----------------------------------------------------------93

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.2
Subject to change without notice 4
16-Bit Microcontroller with 8-bit external data bus
Features
lFive-stages pipeline
lRISC architecture
lStatic Design &Synthesizable design
lBus interface
- Multiplexed address and Data bus which
compatible with 80C188 microprocessor
- Supports nonmultiplexed address bus [A19 : A0]
- 1M byte memory address space
- 64K byte I/O space
lSoftware compatible with the 80C186
lSupport one Asynchronous serial channel & one
Synchronous serial channel
lSupports 32 PIO pins
lPSRAM (Pseudo static RAM) interface with
auto-refresh control
lThree independent 16-bit timers and Timer 1 can
be programed as a watchdog timer
lThe Interrupt controller with five maskable
external interrupts and one
nonmaskable external interrupt
lTwo independent DMA channels
lProgramble chip-select logic for Memory
or I/O bus cycle decoder
lProgrammable wait-state generator
Block Diagram
DMA
Unit
PSRAM
Control
Unit
Chip
Select
Unit
Refresh
Control
Unit
Bus
Interface
Unit
PIO
Unit
Synchronous
Serial Interface
Timer Control
Unit
Interrupt
Control Unit
Clock and
Power
Management
Asynchro-
nous Serial
Port
Instruction
Queue (64bits)
Instruction
Decoder
Register
File
General,
Segment,
Eflag Register
ALU
(Special,
Logic,
Adder,
BSF)
Micro
ROM
EA / LA
Address
Control Signal
Execution
Unit
X1 X2
CLKOUTA
CLKOUTB INT4 INT0 TMRIN0
TMROUT0
TMRIN1
TMROUT1 DRQ0 DRQ1
TXD
RXD
SCLK
SDEN0SDEN1
SDATA
A19~A0
AD7~AD0
AO15~AO8ALE
RD
VCC
GND
LCS/ONCE0
MCS3/RFSH
UCS/ONCE1
PCS5/A1
PCS6/A2
ARDY
SRDY
S2~S0
DT/R
DEN
HOLD
HLDA
S6/CLKDIV2
UZI
RFSH/ADEN
WR WB
RST
INT3/INTA1/IRQ
INT2/INTA0
INT1/SELECT
NMI
MCS2-MCS0
PCS3-PCS0

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 5
Pin Configuration
(PQFP)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
100
R8810LV
Microcontroller
SDEN1/PIO23
SDEN0/PIO22
SCLK/PIO20
ALE
ARDY
GND
X1
X2
VCC
CLKOUTA
CLKOUTB
GND
A19/PIO9
A18/PIO8
VCC
A17/PIO7
A16
A15
A14
A13
A12
A11
A10
A9
A8 A7 A6 A5 A4 A3 A2 A1
VCC
A0
GND GND
HLDA
HOLD
SRDY/PIO6
NMI
INT4/PIO30
INT0
VCC
CND
VCC
GND
TMRIN1/PIO0
TMROUT1/PIO1
TMROUT0/PIO10
TMRIN0/PIO11
DRQ1/PIO13
DRQ0/PIO12
AD0
AO8
AD1
AO9 AD2 AO10 AD3 AO11 AD4 AO12 AD5 GND AO13 AD6 VCC AO14 AD7 AO15
TXD/PIO27 RXD/PIO28 SDATA/PIO21
INT3/INTA1/IRQ
UCS/ONCE1
LCS/ONCE0
PCS2/PIO18
S6/CLKDIV2/PIO29
DT/R/PIO4
DEN/PIO5
MCS0/PIO14
MCS1/PIO15
INT2/INTA0/PIO31
PCS6/A2/PIO2
PCS5/A1/PIO3
PCS3/PIO19
PCS1/PIO17
PCS0/PIO16
MCS2/PIO24
MCS3/RFSH/PIO25
RST
UZI/PIO26
RFSH2/ADEN
WB
WR
RD
S2
S1
S0
INT1/SELECT

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 6
(LQFP)
R8810LV
AD0
AO8
AD1
AO9
AD2
AO10
AD3
AO11
AD4
AO12
AD5
GND
AO13
AD6
VCC
AO14
AD7
AO15
S6/CLKDIV2/PIO29
UZI/PIO26
TXD/PIO27
RXD/PIO28
SDATA/PIO21
SDEN1/PIO23
SDEN0/PIO22
SCLK/PIO20
BHE/ADEN
WR RD
ALE
ARDY
S2 S1 S0
GND
X1 X2
VCC
CLKOUTA CLKOUTB
GND
A19/PIO9 A18/PIO8
VCC
A17/PIO7
A16 A15 A14 A13 A12
A11
A9
A10
A8
A7
A6
A4
A5
A3
A2
VCC
A0
A1
GND
HOLD
HLDA
SRDY/PIO6
NMI
INT4/PIO30
INT0
VCC GND VCC GND
TMRIN1/PIO0 TMROUT0/PIO10 TMRIN0/PIO11 TMROUT1/PIO1 DRQ1/PIO13 DRQ0/PIO12
GND
DT/R/PIO4
INT3/INTA1/IRQ INT2/INTA0/PIO31 INT1/SELECT UCS/ONCE1
LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 PCS3/PIO19 PCS2/PIO18 PCS1/PIO17 PCS0/PIO16
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
55
54
53
52
51
60
59
58
57
56
65
64
63
62
61
70
69
68
67
66
75
74
73
72
71
76 77 78 80 79 81 82 83 85 84 86 87 88 90 89 91 92 93 95 94 96 97 98
100
99
DEN/PIO5
MCS3/RFSH/PIO25
WB
MCS0/PIO14
MCS1/PIO15
MCS2/PIO24

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 7
R8810LV Pin Number Comparison Table
Pin name LQFP Pin No. PQFP Pin No. Pin name
LQFP Pin No.
PQFP Pin No.
AD0 1 78 A11 51 28
AO8 2 79 A10 52 29
AD1 3 80 A9 53 30
AO9 4 81 A8 54 31
AD2 5 82 A7 55 32
AO10 6 83 A6 56 33
AD3 7 84 A5 57 34
AO11 8 85 A4 58 35
AD4 9 86 A3 59 36
AO12 10 87 A2 60 37
AD5 11 88 VCC 61 38
GND 12 89 A1 62 39
AO13 13 90 A0 63 40
AD6 14 91 GND 64 41
VCC 15 92 GND 65 42
AO14 16 93 WB 66 43
AD7 17 94 HLDA 67 44
AO15 18 95 HOLD 68 45
S6/ UZI /PI O29 19 96 SRDY/PI O6 69 46
UZI/PI O26 20 97 NMI 70 47
TXD/PIO27 21 98 DT/
R
/PI O4 70 48
RXD/PI O28 22 99 DEN /PI O5 72 49
SDATA/PIO21 23 100 0MCS /PI O14 73 50
SDEN1/PI O23 24 1 1MCS /PI O15 74 51
SDEN0/PI O22 25 2 I NT4/ PI O30 75 52
SCLK/PI O20 26 3 I NT3/ 1INTA /I RQ 76 53
2RFSH /ADEN 27 4 I NT2/ 0INTA /PI O31 77 54
WR 28 5 I NT1/SELECT 78 55
RD
29 6 I NT0 79 56
ALE 30 7 UCS/1CNCE 80 57
ARDY 31 8 LCS/0CNCE 81 58
2S32 9 6PCS /A2/PI O2 82 59
1S33 10 5PCS /A1/PI O3 83 60
0S34 11 VCC 84 31
GND 35 12 3PCS /PI O19 85 62
X1 36 13 2PCS /PI O18 86 63
X2 37 14 GND 87 64
VCC 38 15 1PCS /PI O17 88 65
CLKOUTA 39 16 0PCS /PI O16 89 66
CLKOUTB 40 17 VCC 90 67
GND 41 18 2MCS /PI O24 91 68
A19/PI O9 42 19 3MCS /RFSH/PI O25 92 69
A18/PI O8 43 20 GND 93 70
VCC 44 21 RST 94 71
A17/PI O7 45 22 TMRI N1/PI O0 95 72
A16 46 23 TMROUT1/PIO1 96 73
A15 47 24 TMROUT0/PIO10 97 74
A14 48 25 TMRI N0/PI O11 98 75
A13 49 26 DRQ1/PI O13 99 76
A12 50 27 DRQ0/PI O12 100 77

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 8
Pin Description
Pin No.(PQFP) Symbol Type Description
15, 21, 38, 61, 67, 92 VCC Input System power: +3.3 volt power supply.
12, 18, 41, 42, 64, 70,
89 GND Input System ground.
71 RST Input* Reset input. When RST is asserted, the CPU immediately
terminate all operation, clears the internal registers & logic,
and the address transfers to the reset address FFFF0h.
13 X1 Input Input to the oscillator amplifier.
14 X2 Output Output from the inverting oscillator amplifier.
16 CLKOUTA Output Clock output A. The CLKOUTA operation is the same as crystal input frequency (X1). CLKOUTA remains active during
reset and bus hold conditions.
17 CLKOUTB Output Clock output B. The CLKOUTB operation is the same as crystal input frequency (X1). CLKOUTB remains active
during reset andbus hold conditions.
Synchronous Serial Port Interface
1
2SDEN1/PIO23 SDEN0/PIO22 Output/Input Serial data enables. Active-high. These pins enable data
transfers of the synchronous serial interface. SDEN1 for port1,
SDEN0 for port0.
3SCLK/PIO20 Output/Input
Synchronous serial data clock. This pin provides the shift clock
to an external device. SCLK=X1/2, 4, 8 or 16 depending on
register setting. This pin held high during the UART inactive.
100 SDATA/PIO21 Input/Output
Synchronous serial data. This pin provides the shift data to or
receives a serial data from an external device.
Asynchronous Serial Port Interface
98 TXD/PIO27 Output/Input Transmit data. This pin transmits asynchronous serial data
from the UART of the microcontroller.
99 RXD Input Receive data. This pin receives asynchronous serial data.
Bus Interface
42RFSH /ADEN Output/Input
For 2RFSH feature, this pin actice low to indicate a DRAM
refresh bus cycle.
For ADEN feature, when this pin is held high on power-on
reset the address portion of the AD bus can be disabled or
enabled by DA bit in the LMCS and UMCS register during
LCS or UCS bus cycle access. The 2RFSH /ADEN with a
internal weak pull-up resister, so no external pull-up resister is
reqired. The AD bus always drives both address and data
during LCS or UCS bus cycle access, if the
2RFSH /ADEN pin with external pull-Low resister during
reset.
5WR Output
Write strobe. This pin indicates that the data on the bus is to be
written into a memory or an I/O device. WR is active during
T2, T3 and
Tw of any write cycle, floats during a bus hold or
reset.
6RD Output Read Strobe. Active low signal which indicates that the
microcontroller is performing a memory or I/O read cycle.
RD floats during bus hold or reset.
7ALE Output Address latch enable. Active high. This pin indicates that an address output on the AD bus. Address is guaranteed to be
valid on the trailing edge of ALE. This pin is tri-stated during

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 9
ONCE mode and is never floating during a bus hold or reset.
8ARDY Input
Asynchronous ready. This pin performs the microcontroller
that the address memory space or I/O device will complete a
data transfer. The ARDY pin accepts a rising edge that is
asynchronous to CLKOUTA and is active high. The falling
edge of ARDY must be synchronized to CLKOUTA. Tie
ARDY high, the microcontroller is always asserted in the ready
condition. If the ARDY is not used, tie this pin low to yield
control to SRDY.
Both SRDY and ARDY should be tied to high if the system
need not assert wait state by externality.
Bus cycle status. These pins are encoded to indicate the bus
status. 2Scan be used as memory or I/O indicator. 1Scan be
used as DT/ Rindicator. These pins are floating during hold
and reset. Bus Cycle Encoding Description
2S1S0SBus Cycle
9
10
11
2S
1S
0S
Output 0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Interrupt acknowledge
Read data from I/O
Write data to I/O
Halt
Instruction fetch
Read data from memory
Write data to memory
Passive
19
20
22
23-37
39, 40
A19/PIO9
A18/PIO8
A17/PIO7
A16-A2
A1 , A0
Output/Input
Address bus. Non-multiplex memory or I/O address.
The A bus
is one-half of a CLKOUTA period earlier than the AD bus.
These pins are high-impedance during bus hold or reset.
78,80,82,84,86,88
91,94 AD0-AD7 Input/Output
The multiplexed address and data bus for memory or I/O
accessing. The address is present during the t1 clock phase, and
the data bus phase is in t2-t4 cycle.
The address phase of the AD bus can be disabled when the
BHE /ADEN pin with external pull-Low resister during reset.
The AD bus is in high-impedance state during bus hold or
reset condition and this bus also be used to load system
configuration information (with pull-up or pull-Low resister)
into the RESCON(F6h) register when the reset input from low
go high.
79,81,83,85,87,90
93,95 AO8-AO15 Output Address Only Bus, In the multiplexed address bus, the AO15 –
AO8 combine with the AD7 –AD0 to form a 16 bit address
bus. These pins are floating during a bus hold or reset.
43 WB Output Write Byte. This pin active low to indicate a write cycle on the
bus. It is floating during reset.
44 HLDA Output
Bus hold acknowledge. Active high. The
microcontroller will
issue a HLDA in response to a HOLD request by external bus
master at the end of T4 or Ti. When the microcontroller is in
hold status (HLDA is high), the AD15-D0, A19-A0, WR ,
RD ,DEN ,0S-1S,6S,BHE , DT/ R,WHB and WLB are
floating, and the UCS , LCS , 6PCS -5PCS ,3MCS -0MCS
and 3PCS -0PCS will be drive high. After HOLD is detected
as being low, the microcontroller will lower HLDA.

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 10
45 HOLD Input
Bus hold request. Active high. This pin indicates that another
bus master is requesting the local bus.
46 SRDY/PIO6 Input/Output
Synchronous ready. This pin performs the microcontroller that
the address memory space or I/O device will complete a data
transfer. The SRDY pin accepts a falling edge that is
asynchronous to CLKOUTA and is active high. SRDY is
accomplished by elimination of the one-half clock period
required to internally synchronize ARDY. Tie SRDY high the
microcontroller is always assert in the ready condition. If the
SRDY is not used, tie this pin low to yield control to ARDY.
Both SRDY and ARDY should be tied to high if the
system need not assert wait state by externality.
48 DT/ R/PIO4 Output/Input
Data transmit or receive. This pin indicates the direction of
data flow through an external data-bus transceiver. DT/ Rlow,
the
microcontroller receives data. When DT/R is asserted high,
the microcontroller writes data to the data bus.
49 DEN /PIO5 Output/Input
Data enable. This pin is provided as a data bus transceiver
output enable.DEN
is asserted during memory and I/O access.
DEN is drived high when DT/ Rchanges state. It is floating
during bus hold or reset condition.
96 S6/ 2CLKDIV /PIO29 Output/Input
Bus cycle status bit6/clock divided by 2. For S6 feature, this
pin is low to indicate a
microcontroller-initiated bus cycle or
high to indicate a DMA-initiated bus cycle during T2, T3, Tw
and T4. For 2CLKDIV
feature. The internal clock of
microcontroller is the external clock
be divided by 2.
(CLKOUTA, CLKOUTB=X1/2), if this pin held low during
power-on reset. The pin is sampled on the rising edge of
RST .
97 UZI /PIO26 Output/Input Upper zero indicate. This pin is the logical OR of the inverted
A19-A16. It asserts in the T1 and is held throughout the cycle.
Chip Select Unit Interface
50
51
68
69
0MCS /PIO14
1MCS /PIO15
2MCS /PIO24
3MCS /RFSH /PIO25
Output/Input
Midrange memory chip selects. For MCS feature, these pins
are active low when enable the MMCS(A6h) register to access
a memory. The address ranges are programmable.
3MCS -0MCS are held high during bus hold. When
programming LMCS(A2h) register, pin69 is as aRFSH pin to
auto refresh the PSRAM.
57 UCS /1ONCE Output/Input
Upper memory chip select/ONCE mode request 1. For UCS
feature, this pin acts low when system accesses the defined
portion memory block of the upper 512K bytes (80000h-
FFFFFh) memory region. UCS default acted address region is
from F0000h to FFFFFh after power-on reset. The address
range acting UCS is programmed by software. For 1ONCE
feature. If 0ONCE and 1ONCE are sampled low on the
rising edge of RST . The microcontroller enters ONCE mode.
In ONCE mode, all pins are high-impedance. This pin
incorporates weakly pull-up resistor.
58 LCS /0ONCE Output/Input
Lower memory chip select/ONCE mode request 0. For LCS
feature, this pin acts low when the microcontroller accesses the
defined portion memory block of the lower 512K (00000h-
7FFFFh) memory region. The address range acting LCS is

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 11
programmed by software.
For 0ONCE feature, see UCS /1ONCE description. This pin
incorporates weakly pull-up register.
59
60 6PCS /A2/PIO2
5PCS /A1/PIO3 Output/Input
Peripheral chip selects/latched address bit. For PCS feature,
these pins act low when the microcontroller accesses the fifth
or sixth region of the peripheral memory (I/O or memory
space). The base address of PCS is programmable. These pins
assert with the AD address bus and are not float during bus
hold.
For latched address bit feature. These pins output the latched
address A2, A1 when cleared the EX bit in theMCS and PCS
auxiliary register. The A2, A1 retains previous latched data
during bus hold.
62
63
65
66
3PCS /PIO19
2PCS /PIO18
1PCS /PIO17
0PCS /PIO16
Output/Input
Peripheral chip selects. These pins act low when the
microcontroller accesses the defined memory area of the
peripheral memory block (I/O or memory address). For I/O
accessed, the base address can be programmed in the region
00000h to 0FFFFh.
For memory address access, the base address can be located in
the 1M byte memory address region. These pins assert with the
multiplexed AD address bus and are not float during bus hold.
Interrupt Control Unit Interface
47 NMI Input
Nonmaskable Interrupt. The NMI is the highest priority
hardware interrupt and is nonmaskable. When this pin is
asserted (NMI transition from low to high), the
microcontroller
always transfers the address bus to the location specified by the
nonmaskable interrupt vector in the microcontroller interrupt
vector table. The NMI pin must be asserted for at least one
CLKOUTA period to guarantee that the interrupt is recognized.
52 INT4/PIO30 Input/Output
Maskable interrupt request 4. Act high. This pin indicates that
an interrupt request has occurred. The
microcontroller will
jump to the INT4 address vector to execute the service routine
if the INT4 is enable. The interrupt input can be configured to
be either edge- or level-triggered. The requesting device must
holt the INT4 until the request is acknowledged to guarantee
interrupt recognition.
53 INT3/ 1INTA /IRQ Input/Output
Maskable interrupt request 3/interrupt acknowledge 1/slave
interrupt request. For INT3 feature, except the difference
interrupt line and interrupt address vector, the function of INT3
is the same as INT4.
For 1INTA feature, in cascade mode or special fully-nested
mode, this pin corresponds the INT1.
For IRQ feature, when the microcontroller is as a slave device,
this pin issues an interrupt request to the master interrupt
controller.
54 INT2/ 0INTA /PIO31 Input/Output
Maskable interrupt
request 2/interrupt acknowledge 0. For
INT2 feature, except the difference interrupt line and interrupt
address vector, the function of INT2 is the same as INT4.
For 0INTA feature, in cascade mode or special fully-nested
mode, this pin corresponds the INT0.
55 INT1/ SELECT Input/Output Maskable interrupt request 1/slave select. For INT1 feature, except the difference interrupt line and interrupt address vector,
the function of INT1 is the same as INT4.

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 12
For SELECT feature, when the microcontroller is as a slave
device, this pin is
drived from the master interrupt controller
decoding. This pin acts to indicate that an interrupt appears on
the address and data bus.
The INT0 must act before SELECT acts when the interrupt
type appears on the bus.
56 INT0 Input Maskable interrupt request 0. Except the interrupt line and interrupt address vector, the function of INT0 is the same as
INT4.
Timer Control Unit Interface
72
75 TMRIN1/PIO0 TMRIN0/PIO11 Input/Output
Timer input. These pins can be as clock or control signal input,
which depend upon the programmed timer mode. After
internally synchronizing low to high transitions on TMRIN, the
timer controller increments. These pins must be pull-up if not
being used.
73
74 TMROUT1/PIO1 TMROUT0/PIO10 Output/Input
Timer output. Depending on timer mode select these pins
provide single pulse or continuous waveform. The duty cycle
of the waveform can be programmable. These pins are floated
during a bus hold or reset.
DMA Unit Interface
76
77 DRQ1/PIO13 DRQ0/PIO12 Input/Output
DMA request. These pins are asserted high by an external
device when the device is ready for DMA channel 1 or channel
0 to perform a transfer. These pins are level-triggered and
internally synchronized. The DRQ signals must remain act
until finish serviced and are not latched.
Notes:
1.When enable the PIO Data register, there are 32 MUX definition pins can be as a PIO pin. For example, the DRD1/PIO13
(pin76) can be as a PIO13 when enable the PIO Data register.
2.The PIO status during Power-On reset : PIO1, PIO10, PIO22, PIO23 are input with pull-down, PIO4 to PIO9 are
normal operation and the others are input with pull-up.

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 13
Basic Application System Block
X1
X2
RS232
Level
Converter
Serial port0
Timer0-1
INTx
DMA
PIO
D7-D0
A19-A0
WR
Data(8)
Address
UCS
RD
WE
OE
CE
Flash ROM
Data(8)
Address
SRAM
Data
Address
WE
OE
Peripheral
CSPCSx
R8810LV
WE
OE
CELCS
BASIC APPLICATION SYSTEM BLOCK (B)
RST
VCC
100K
1uF
DIR
Transciver
G
Latch
DEN
DT/R
AD7-AD0
AD7-AD0
ALE
AO15-AO8
A19-A16
X1
X2
RS232
Level
Converter
Serial port0
Timer0-1
INTx
DMA
PIO
AD7-AD0
A19-A0
WR
Data(8)
Address
UCS
RD
WE
OE
CE
Flash ROM
Data(8)
Address
SRAM
Data
Address
WE
OE
Peripheral
CSPCSx
R8810LV WE
OE
CELCS
BASIC APPLICATION SYSTEM BLOCK (A)
RST
VCC
100K
1uF

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 14
Oscillator Characteristics
For fundamental -mode crystal:
C1 --- 20pF ±20% ; C2 --- 20pF ±20% ; Rf --- 1 mega-ohm ; C3 , L --- Don’t care
For third-overtone mode crystal:
C1 --- 20pF ±20% ; C2 --- 20pF ±20% ; C3 --- 200pf ; Rf --- 1 mega-ohm
L --- 3.0uH ±20% (40MHz) , 4.7uH ±20% (33MHz)
8.2uH ±20% (25MHz) , 12uH ±20% (20MHZ)
X1
X2
L
C2
C1
200PF
Rf R8810LV
C3

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 15
Read/Write timing Diagram
CLKOUTA
A19:A0
S6
AO15:AO8
ALE
DEN
DT/R
UZI
T1 T2 T3 T4
ADDRESS
UCS,LCS
S2:S0
TW
READ CYCLE
PCSx,MCS X
ADDRESS
RD
AD7:AD0 ADDRESS DATA
7 5 7

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 16
CLKOUTA
A19:A0
S6
AO15:AO8
ALE
WR
DEN
DT/R
UZI
T1 T2 T3 T4
ADDRESS
UCS,LCS
S2:S0
TW
WRITE CYCLE
PCSx,MCS X
ADDRESS
AD7:AD0
WB
ADDRESS DATA
7 6 7

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 17
Execution Unit
General Register
The R8810 has eight 16-bit general registers. And the AX,BX,CX,DX can be subdivided into two 8-bit register (AH,AL,BH,
BL,CH,CL,DH,DL). The functions of these registers are described as follows.
AX : Word Divide , Word Multiply, Word I/O operation.
AH : Byte Divide , Byte Multiply, Byte I/O , Decimal Arithmetic, Translate operation.
AL : Byte Divide , Byte Multiply operation.
BX : Translate operation.
CX : Loops, String operation
CL : Variable Shift and Rotate operation.
DX : Word Divide , Word Multiply, Indirect I/O operation
SP: Stack operations (POP, POPA, POPF, PUSH, PUSHA, PUSHF)
BP : General-purpose register which can be used to determine offset address of operands in Memory.
SI: String operations
DI : String operations
Segment Register
R8810 has four 16-bit segment registers, CS, DS, SS, ES. The segment registers contain the base addresses (starting location)
of these memory segments, and they are immediately addressable for code (CS), data (DS & ES), and stack (SS) memory.
CS (Code Segment) : The CS register points to the current code segment, which contains instruction to be fetched. The
default location memory space for all instruction is 64K. The initial value of CS register is 0FFFFh.
Accumulator
Base Register
Count/Loop/Repeat/Shift
Data
Stack Pointer
Destination Index
Base Pointer
Source Index
AX
BX
CX
DX
Data
Group
Index Group
and
Pointer
GENERAL REGISTERS
AH
BH
CH
DH
AL
BL
CL
DL
SP
BP
SI
DI
07815
High Low

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 18
DS (Data Segment): The DS register points to the current data segment, which generally contains program variables. The
DS register initialize to 0000H.
SS (Stack Segment ) : The SS register points to the current stack segment, which is for all stack operations, such as pushes
and pops. The stack segment is used for temporary space. The SS register initialize to 0000H.
ES (Extra Segment) : The ES register points to the current extra segment which is typically for data storage, such as large
string operations and large data structures. The DS register initialize to 0000H.
Instruction Pointer and Status Flags Register
IP (Instruction Pointer): The IP is a 16-bit register and it contains the offset of the next instruction to be fetched. Software
can not to direct access the IP register and this register is updated by the Bus Interface Unit. It can change, be saved or be
restored as a result of program execution. The IP register initialize to 0000H and the CS:IPstarting execution address is at
0FFFF0H.
These flags reflect the status after the Execution Unit is executed.
Bit 15-12 : Reserved
Bit 11: OF, Overflow Flag. An arithmetic overflow has occurred, this flag will be set.
Bit 10 : DF, Direction Flag. If this flag is set, the string instructions are increment address process. If DF is cleared, the string
instructions are decrement address process. Refer the STD and CLD instructions for how to set and clear the DF flag.
Bit 9 : IF, Interrupt-Enable Flag. Refer the STI and CLI instructions for how to set and clear the IF flag.
Set to 1 : The CPU enables the maskable interrupt request.
CS
DS
SS
ES
07815
Code Segment
Data Segment
Stack Segment
Extra Segment
SEGMENT REGISTERS
Processor Status Flags Registers FLAGS
0
Reset Value : 0000h
123456789101112131415
Res PF Res CFAFResZFSFTFIFDFOFReserved

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 19
Set to 0 : The CPU disables the maskable interrupt request.
Bit 8: TF, Trace Flag. Set to enable single-step mode for debugging; Clear to disable the single-step mode. If an application
program sets the TF flag using POPF or IRET instruction, a debug exception is generated after the instruction (The
CPU automatically generates an interrupt after each instruction) that follows the POPF or IRET instruction.
Bit 7: SF, Sign Flag. If this flag is set, the high-order bit of the result of an operation is 1,indicating it is negative.
Bit 6: ZF, Zero Flag. The result of operation is zero, this flag is set.
Bit 5: Reserved
Bit 4: AF, Auxiliary Flag. If this flag is set, there has been a carry from the low nibble to the high or a borrow from the high
nibble to the low nibble of the AL general-purpose register. Used in BCD operation.
Bit 3: Reserved.
Bit 2: PF, Parity Flag. The result of low-order 8 bits operation has even parity, this flag is set.
Bit 1: Reserved
Bit 0: CF, Carry Flag. If CF is set, there has been a carry out or a borrow into the high-order bit of the instruction result.
Address generation
The Execution Unit generates a 20-bit physical address to Bus Interface Unit by the Address Generation. Memory is organized
in sets of segments. Each segment contains a 16 bits value. Memory is addressed using a two-component address that consists
of a 16-bit segment and 16-bit offset. The Physical Address Generation figure describes how the logical address transfers to the
physical address.
12F90
19 0
0012
15 0
12FA2
19 0
TO Memory
12F9
0012
15 0
15 0
Physical Address
Segment Base
Offset
Logical
Address
Shift left 4 bits
Physical Address Generation

RDC
®RISC DSP Controller R8810LV
RDC Semiconductor Co. Rev:1.1
Subject to change without notice 20
Peripheral Control Block Register
The peripheral control block can be mapped into either memory or I/O space which is to program the FEh register. And it
starts at FF00h in I/O space when reset the microprocessor.
The following table is the definition of all the peripheral Control Block Register , and the detail description will arrange on
the relation Block Unit.
Offset
(HEX) Register Name Page Offset (HEX) Register Name Page
FE Peripheral Control Block Relocation Register 21 66 Timer 2 Mode / Control Register 60
F6 Reset Configuration Register 24 62 Timer 2 Maxcount Compare A Register 61
F4 Processor Release Level Register 21 60 Timer 2 Count Register 61
F0 PDCON Register 22 5E Timer 1 Mode / Control Register 58
E4 Enable RCU Register 74 5C Timer 1 Maxcount Compare B Register 60
E2 Clock Prescaler Register 74 5A Timer 1 Maxcount Compare A Register 60
E0 Memory Partition Register 74 58 Timer 1 Count Register 60
DA DMA 1 Control Register 52 56 Timer 0 Mode / Control Register 57
D8 DMA 1 Transfer Count Register 54 54 Timer 0 Maxcount Compare B Register 58
D6 DMA 1 Destination Address High Register 54 52 Timer 0 Maxcount Compare A Register 58
D4 DMA 1 Destination Address Low Register 54 50 Timer 0 Count Register 57
D2 DMA 1 Source Address High Register 55 44 Serial Port Interrupt Control Register 37
D0 DMA 1 Source Address Low Register 55 42 Watchdog Timer Control Register 61
CA DMA 0 Control Register 51 40 INT4 Control Register 38
C8 DMA 0 Transfer Count Register 51 3E INT3 Control Register 39
C6 DMA 0 Destination Address High Register 51 3C INT2 Control Register 39
C4 DMA 0 Destination Address Low Register 52 3A INT1 Control Register 40
C2 DMA 0 Source Address High Register 52 38 INT0 Control Register 40
C0 DMA 0 Source Address Low Register 52 36 DMA 1 Interrupt Control Register 41
A8 PCS and MCS Auxiliary Register 32 34 DMA 0 Interrupt Control Register 42
A6 Midrange Memory Chip Select Register 31 32 Timer Interrupt Control Register 42
A4 Peripheral Chip Select Register 33 30 Interrupt Status Register 43
A2 Low Memory Chip Select Register 30 2E Interrupt Request Register 44
A0 Upper Memory Chip Select Register 29 2C In-service Register 45
88 Serial Port Baud Rate Divisor Register 66 2A Priority Mask Register 46
86 Serial Port Receive Register 65 28 Interrupt Mask Register 47
84 Serial Port Transmit Register 65 26 Poll Status Register 47
82 Serial Port Status Register 64 24 Poll Register 48
80 Serial Port Control Register 63 22 End-of-Interrupt 48
7A PIO Data 1 Register 72 20 Interrupt Vector Register 49
78 PIO Direction 1 Register 72 18 Synchronous Serial Receive Register 68
76 PIO Mode 1 Register 72 16 Synchronous Serial Transmit 0 Register 68
74 PIO Data 0 Register 73 14 Synchronous Serial Transmit 1 Register 68
72 PIO Direction 0 Register 73 12 Synchronous Serial Enable Register 67
70 PIO Mode 0 Register 73 10 Synchronous Serial Status Register 67