NXP Semiconductors LPC11U3x User manual

UM10462
LPC11U3x/2x/1x User manual
Rev. 5.5 — 21 December 2016 User manual
Document information
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Keywords LPC11U3x/2x/1x, ARM Cortex-M0, microcontroller, LPC11U12,
LPC11U14, LPC11U13, USB, LPC11U22, LPC11U23, LPC11U24,
LPC11U34, LPC11U35, LPC11U36, LPC11U37, LPC11U37H, I/O Handler
Abstract LPC11U3x/2x/1x User manual

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User manual Rev. 5.5 — 21 December 2016 2 of 523
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Revision history
Rev Date Description
5.5 20161221 Modifications:
•Updated Table 200 “USBD_API_INIT_PARAM class structure” with:
Parameters:
a. hUsb = Handle to the USB device stack.
Returns:
The call back should return ErrorCode_t type to indicate success or error condition.
•Updated Table 208 “USBD_HW_API class structure”:
Added GetMemSize to the text: This function is called by application layer before calling
pUsbApi->hw->
Added Parameters:
–hUsb = Handle to the USB device stack.
–EPNum = Endpoint number corresponding to the event as per USB specification. ie.
An EP1_IN isrepresented by 0x81 number. For device events set this param to 0x0.
–event = Type of endpoint event. See USBD_EVENT_T for more details.
–enable = 1 - enable event, 0 - disable event.Returns:Returns ErrorCode_t type to
indicate success or error condition.Return values:1. LPC_OK(0) = - On success2.
ERR_USBD_INVALID_REQ(0x00040001) = - Invalid event type.
•Added on-chip local RAM to Section 20.8.8 “RAM used by ISP command handler”,
Section 20.8.9 “RAM used by IAP command handler”, and Section 20.14 “IAP
commands”
•Deleted: The boot sector can not be prepared by this command from Section 20.14.1
“Prepare sector(s) for write operation”, Table 384 “IAP Copy RAM to flash command”,
and Table 385 “IAP Erase Sector(s) command”.
5.4 20161007 Modifications:
•Added text after Table 227 “Endpoint commands”: For EP0 transfers, the hardware will
do auto handshake as long as the ACTIVE bit is set in EP0_IN/OUT command list.
Unlike other endpoints, the hardware will not clear the ACTIVE bit after transfer is done.
Thus, the software should manually clear the bit whenever it receives new setup packet
and set it only after it has queued the data for control transfer.
5.3 20140611 Modifications:
•I/O Handler interrupt added in Table 59 “Connection of interrupt sources to the Vectored
Interrupt Controller”.
•NVIC register description added. See Section 6.5.

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5.2 20140331 Modifications:
•Part LPC11U22FBD48/301 added.
•Use of IAP mode with power profiles clarified. Use power profiles in default mode when
executing IAP commands. See Section 20.14 “IAP commands” and Section 5.3.
•Section 5.3 added to clarify use of power profiles.
•Watchdog interrupt flag polarity corrected: This flag is cleared by writing a 1 to the
WDINT bit in the MOD register (Section 17.8.1 “Watchdog mode register”).
•Figure 69 “Boot process flowchart” corrected.
•Table 15 “Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit
description” added.
•Remark added to Section 3.9.4.3 “Wake-up from Deep-sleep mode” and
Section 3.9.5.3 “Wake-up from Power-down mode”: After wake-up, reprogram the clock
source for the main clocks.
•Pin description tables for RESET/PIO0_0 updated: In deep power-down mode, this pin
must be pulled HIGH externally. The RESET pin can be left unconnected or be used as
a GPIO pin if an external RESET function is not needed. See Chapter 8
“LPC11U3x/2x/1x Pin configuration”.
•Pin description notes relating to open-drain I2C-bus pins updated for clarity. Chapter 8
“LPC11U3x/2x/1x Pin configuration”.
•Pin description of the WAKEUP pin updated for clarity. Chapter 8 “LPC11U3x/2x/1x Pin
configuration”.
5.1 20131220 Modifications:
•Reset value of the SYSAHBCLKCTRL register corrected. See Table 5.
•Reserved function added to IOCON pin configuration registers PIO0_8 and PIO0_9.
See Table 69 and Table 70.
•Changed title to “LPC11U3x/2x/1x User manual”.
5 20131120 Modifications:
•Table 121 “GPIO pins available” corrected.
•Table 343 “ISP entry pins for different boot loader versions” added.
•Bit description of the SLEEPDEEP bit corrected in Table 53 “Power control register
(PCON, address 0x4003 8000) bit description”.
•Part LPC11U37HFBD64/401 added.
•API pointer structure updated in Figure 73, Figure 10, and Figure 19.
•Power Profiles API pointer definitions corrected. See Section 5.4.
•Chapter 23 “LPC11U3x/2x/1x I/O Handler” added.
Revision history …continued
Rev Date Description

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LPC11U3x/2x/1x User manual
4.1 20130719 Modifications:
•Description of the NMISRC register updated. See Section 3.5.32 “NMI source selection
register”.
•Bootloader description clarified. See Section 20.2.
•Code listings corrected in Chapter 10.
•Table 346 “LPC11U3x flash sectors and pages” corrected for LPC11U35 parts.
•Editorial updates in Section 20.14 “IAP commands”.
•Steps to enter Deep-sleep mode and Power-down mode updated in Section 3.9.4.2
“Programming Deep-sleep mode” and Section 3.9.5.2 “Programming Power-down
mode”: Main clock must be switched to IRC before entering either mode.
•Minimum USB AHB clock changed to 6 MHz. See Section 11.4.7.
•Description of ISP GO command expanded. See Section 20.13.8.
4 20121119 Modifications:
•Removed remark “USB ISP commands are supported for the Windows operating
system only.”. USP ISP commands are supported in Windows, Linux, and Mac OS.
•Remove the following step to execute before entering Deep power-down: Enable the
IRC. This step is not longer required. See Section 3.9.6 “Deep power-down mode”.
•Register offset of the CR1 register corrected in timers CT16B0 and CT32B0. See
Table 293 and Table 314.
•Bit position of the CAP1 interrupt flag corrected in the IR registers of timers CT16B0
and CT32B0. See Table 282 and Table 303.
•Bit positions of the CAP1 edge and interrupt control bits corrected in the CCR registers
of timers CT16B0 and CT32B0. See Table 290 and Table 311.
•Bit values of the CAP1 counter mode and capture input select bits corrected in the
CTCR registers of timers CT16B0 and CT32B0. See Table 297 and Table 319.
•Remove instruction breakpoints from feature list for SWD. See Section 21.2.
•Explained use of interrupts with Power profiles in Section 5.3 “General description”.
•BOD interrupt level 0 removed. See Section 3.5.29 “BOD control register”.
•Polarity of the IOCON glitch filter FILTR bit changed: 0 = glitch filter on, 1 = glitch filter
off. See Table 60.
•Reset value of SYSCON registers updated and reset value after boot added. See
Table 5 “Register overview: system control block (base address 0x4004 8000)”.
3 20120716 Modifications:
•Parts LPC11U3x added.
•Editorial updates to Section 9.4.1 and Section 9.6.4.
•USB on-chip driver support for composite device added in Chapter 10.
Revision history …continued
Rev Date Description

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Chapter :
•Flash page erase command added for LPC11U3x parts in Chapter 20.
•FREQSEL bit values updated in Table 14 “Watchdog oscillator control register
(WDTOSCCTRL, address 0x4004 8024) bit description”.
•SRAM use by bootloader specified in Section 20.2.
•Description of interrupt use with IAP calls updated (see Section 20.8.7).
•Description of ISP Go command updated (only Thumb mode allowed) in Table 357.
•Update EEPROM write command. The top 64 bytes are reserved for the 4 kB EEPROM
only (see Section 20.14.11).
•Description of the BYPASS bit corrected in Table 13 “System oscillator control register
(SYSOSCCTRL, address 0x4004 8020) bit description”.
•Description of USB CDC device class updated in Table 186 “USBD_CDC_API class
structure” and Table 187 “USBD_CDC_INIT_PARAM class structure”.
•IRC suitable for USB clocking in low-speed mode (see Section 11.4.7 and
Section 3.5.12).
•Figure 8 “Start-up timing” updated (RESET changed to internal reset).
•Figure 66 corrected.
2.1 20120113 Modifications:
•Description of PIOPOR1CAP register updated (see Table 34).
•LPM register added (Table 201).
2 20111214 LPC11U3x/2x/1x User manual
Modifications:
•Parts LPC11U2x added.
•Chapter 22 added.
•Part LPC11U14FHI33/201 added.
Modifications:
•Parts LPC11U2x added.
•Chapter 22 added.
•Part LPC11U14FHI33/201 added.
•Bit 10 (TD) changed to reserved for PIO0_4 and PIO0_5 registers (Table 65, Table 66).
1 20110414 Initial version
Revision history …continued
Rev Date Description

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1.1 Introduction
The LPC11U3x/2x/1x are an ARM Cortex-M0 based, low-cost 32-bit MCU family,
designed for 8/16-bit microcontroller applications, offering performance, low power, simple
instruction set and memory5 addressing together with reduced code size compared to
existing 8/16-bit architectures.
The LPC11U3x/2x/1x operate at CPU frequencies of up to 50 MHz. Equipped with a
highly flexible and configurable full-speed USB 2.0 device controller, the LPC11U3x/2x/1x
bring unparalleled design flexibility and seamless integration to today's demanding
connectivity solutions.
The peripheral complement of the LPC11U3x/2x/1x includes up to 32 kB of flash memory,
up to 8 kB of SRAM data memory, one Fast-mode Plus I2C-bus interface, one
RS-485/EIA-485 USART with support for synchronous mode and smart card interface,
two SSP interfaces, four general purpose counter/timers, a 10-bit ADC, and up to 54
general purpose I/O pins.
The I/O Handler is a software library-supported hardware engine that can be used to add
performance, connectivity and flexibility to system designs. It is available on the
LPC11U37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,
I2C, and I2S with no or very low additional CPU load and can off-load the CPU by
performing processing-intensive functions like DMA transfers in hardware. Software
libraries for multiple I/O handler applications are available on http://www.LPCware.com.
See Section 25.2 “References” for additional documentation related to the LPC11Uxx
parts.
1.2 Features
•System:
–ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
–ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
–Non Maskable Interrupt (NMI) input selectable from several input sources.
–System tick timer.
•Memory:
–Up to 32 kB on-chip flash program memory.
–LPC11U3x only: Up to 128 kB on-chip flash program memory with sector (4 kB)
and page erase (256 byte) access.
–In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
bootloader software.
–Total SRAM
LPC11U1x: up to 6 kB (4 kB main SRAM and 2 kB USB SRAM).
LPC11U2x: up to 10 kB (8 kB main SRAM and 2 kB USB SRAM).
UM10462
Chapter 1: LPC11U3x/2x/1x Introductory information
Rev. 5.5 — 21 December 2016 User manual

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Chapter 1: LPC11U3x/2x/1x Introductory information
LPC11U3x: up to 12 kB (8 kB main SRAM0, 2 kB SRAM1, 2 kB USB SRAM).
–16 kB boot ROM.
–LPC11U2x/3x only: Up to 4 kB on-chip EEPROM data memory; byte erasable and
byte programmable; on-chip API support.
•ROM based drivers:
–Power profiles.
–32-bit integer division routines.
–LPC11U2x/3x only: ROM-based USB drivers. Flash updates via USB supported.
Supports Human-Interface Device (HID) class, Mass Storage Device Class (MSC),
and Communication Device Class (CDC).
–LPC11U2x/3x only: IAP EEPROM drivers.
•Debug options:
–Standard JTAG test interface for BSDL.
–Serial Wire Debug.
•Digital peripherals:
–Up to 54 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
–Up to eight GPIO pins can be selected as edge and level sensitive interrupt
sources.
–Two GPIO grouped interrupt modules enables an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
–High-current source output driver (20 mA) on one pin (P0_7).
–High-current sink driver (20 mA) on true open-drain pins (P0_4 and P0_5).
–Four general purpose counter/timers with a total of 8 capture inputs and 13 match
outputs.
–Programmable windowed WatchDog Timer (WDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
•Analog peripherals:
–10-bit ADC with input multiplexing among eight pins.
•I/O Handler for hardware emulation of serial interfaces, DMA, and other functionality;
supported through software libraries. (LPC11U37HFBD64/401 only.)
•Serial interfaces:
–USB 2.0 full-speed device controller.
–USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
–Two SSP interfaces with FIFO and multi-protocol capabilities.
–I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
•Clock generation:
–Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).

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Chapter 1: LPC11U3x/2x/1x Introductory information
–12 MHz Internal high-frequency RC oscillator (IRC) that can optionally be used as
a system clock.
–Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
–PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
–A second, dedicated PLL is provided for USB.
–Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
•Power control:
–Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
–Power profiles residing in boot ROM allow optimized performance and minimized
power consumption for any given application through one simple function call.
–Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, watchdog interrupt, BOD interrupt, or USB port activity.
–Processor wake-up from Deep power-down mode using one special function pin.
–Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
–Power-On Reset (POR).
–Brownout detect with four separate thresholds for interrupt and forced reset.
•Unique device serial number for identification.
•Single 3.3 V power supply (1.8 V to 3.6 V).
•Temperature range 40 C to +85 C.
•Available as LQFP64, LQFP48, TFBGA48 packages, and as HVQFN33 in two
package sizes: 5 x 5 x 0.85 mm and 7 x 7 x 0.85 mm.
•Pin-compatible to the ARM Cortex-M3 based LPC134x series.
1.3 Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC11U12FHN33/201 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U12FBD48/201 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U13FBD48/201 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U14FHN33/201 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U14FHI33/201 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no
leads; 33 terminals; body 5 5 0.85 mm n/a
LPC11U14FBD48/201 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U14FET48/201 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 4.5
0.7 mm SOT1155-2

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Chapter 1: LPC11U3x/2x/1x Introductory information
LPC11U22FBD48/301 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U23FBD48/301 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U24FHI33/301 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5 5 0.85 mm n/a
LPC11U24FBD48/301 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U24FET48/301 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U24FHN33/401 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U24FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U24FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11U34FHN33/311 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U34FBD48/311 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U34FHN33/421 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U34FBD48/421 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U35FHN33/401 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11U35FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U35FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11U35FHI33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 5 5 0.85 mm n/a
LPC11U35FET48/501 TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 4.5
0.7 mm SOT1155-2
LPC11U36FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U36FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11U37FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11U37HFBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11U37FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
Table 1. Ordering information …continued
Type number Package
Name Description Version
Table 2. Part ordering options
Part Number FLASH
(kB) SRAM (kB)
(Main
SRAM)
SRAM1
(kB) USB SRAM
(kB)
Total
genera
purpose
SRAM
EEPROM
(kB) USB I2C/ Fast+ SSP ADC Chan
nels
GPIO
LPC11U12FHN33/201 16 4 - 2 6 N/A 1 1 2 8 26
LPC11U12FBD48/201 16 4 - 2 6 N/A 1 1 2 8 40
LPC11U13FBD48/201 24 4 - 2 6 N/A 1 1 2 8 40
LPC11U14FHI33/201 32 4 - 2 6 N/A 1 1 2 8 26
LPC11U14FHN33/201 32 4 - 2 6 N/A 1 1 2 8 26
LPC11U14FBD48/201 32 4 - 2 6 N/A 1 1 2 8 40
LPC11U14FET48/201 32 4 - 2 6 N/A 1 1 2 8 40
LPC11U22FBD48/301 16 6 - 2 8 1 1 1 2 8 40

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Chapter 1: LPC11U3x/2x/1x Introductory information
[1] 2 kB of SRAM1 available for I/O Handler library only.
LPC11U23FBD48/301 24 6 - 2 8 1 1 1 2 8 40
LPC11U24FHI33/301 32 6 - 2 8 2 1 1 2 8 26
LPC11U24FBD48/301 32 6 - 2 8 2 1 1 2 8 40
LPC11U24FET48/301 32 6 - 2 8 2 1 1 2 8 40
LPC11U24FHN33/401 32 8 - 2 10 4 1 1 2 8 26
LPC11U24FBD48/401 32 8 - 2 10 4 1 1 2 8 40
LPC11U24FBD64/401 32 8 - 2 10 4 1 1 2 8 54
LPC11U34FHN33/311 40 8 - - 8 4 1 1 2 8 26
LPC11U34FBD48/311 40 8 - - 8 4 1 1 2 8 40
LPC11U34FHN33/421 48 8 - 2 10 4 1 1 2 8 26
LPC11U34FBD48/421 48 8 - 2 10 4 1 1 2 8 40
LPC11U35FHN33/401 64 8 - 2 10 4 1 1 2 8 26
LPC11U35FBD48/401 64 8 - 2 10 4 1 1 2 8 40
LPC11U35FBD64/401 64 8 - 2 10 4 1 1 2 8 54
LPC11U35FHI33/501 64 8 2 2 12 4 1 1 2 8 26
LPC11U35FET48/501 64 8 2 2 12 4 1 1 2 8 40
LPC11U36FBD48/401 96 8 - 2 10 4 1 1 2 8 40
LPC11U36FBD64/401 96 8 - 2 10 4 1 1 2 8 54
LPC11U37FBD48/401 128 8 - 2 10 4 1 1 2 8 40
LPC11U37HFBD64/401 128 8 2[1] 210 4 112854
LPC11U37FBD64/501 128 8 2 2 12 4 1 1 2 8 54
Table 2. Part ordering options …continued
Part Number FLASH
(kB) SRAM (kB)
(Main
SRAM)
SRAM1
(kB) USB SRAM
(kB)
Total
genera
purpose
SRAM
EEPROM
(kB) USB I2C/ Fast+ SSP ADC Chan
nels
GPIO