Holtek HT32F52342 User manual

Holtek 32-Bit Microcontroller with Arm®Cortex®-M0+ Core
HT32F52342/HT32F52352
User Manual
Revision: V1.30 Date: September 28, 2018

Rev. 1.30 2 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Table of Contents
1 Introduction........................................................................................................... 26
Overview.............................................................................................................................. 26
Features............................................................................................................................... 27
Device Information............................................................................................................... 32
Block Diagram ..................................................................................................................... 33
2 Document Conventions ....................................................................................... 34
3 System Architecture............................................................................................. 35
Arm®Cortex®-M0+ Processor .............................................................................................. 35
Bus Architecture................................................................................................................... 36
Memory Organization .......................................................................................................... 37
Memory Map................................................................................................................................... 38
Embedded Flash Memory............................................................................................................... 41
Embedded SRAM Memory ............................................................................................................. 41
AHB Peripherals ............................................................................................................................. 41
APB Peripherals ............................................................................................................................. 41
4 Flash Memory Controller (FMC) .......................................................................... 42
Introduction .......................................................................................................................... 42
Features............................................................................................................................... 42
Functional Descriptions ....................................................................................................... 43
Flash Memory Map ......................................................................................................................... 43
Flash Memory Architecture ............................................................................................................. 44
Wait State Setting ........................................................................................................................... 44
Booting Conguration ..................................................................................................................... 45
Page Erase ..................................................................................................................................... 46
Mass Erase..................................................................................................................................... 47
Word Programming......................................................................................................................... 48
Option Byte Description .................................................................................................................. 49
Page Erase/Program Protection ..................................................................................................... 49
Security Protection.......................................................................................................................... 51
Register Map ....................................................................................................................... 52
Register Descriptions........................................................................................................... 53
Flash Target Address Register – TADR .......................................................................................... 53
Flash Write Data Register – WRDR ............................................................................................... 54
Flash Operation Command Register – OCMR ............................................................................... 55
Flash Operation Control Register – OPCR..................................................................................... 56
Flash Operation Interrupt Enable Register – OIER ........................................................................ 57
Flash Operation Interrupt and Status Register – OISR .................................................................. 58
Flash Page Erase/Program Protection Status Register – PPSR.................................................... 60
Flash Security Protection Status Register – CPSR ........................................................................ 61

Rev. 1.30 3 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Flash Vector Mapping Control Register – VMCR ........................................................................... 62
Flash Manufacturer and Device ID Register – MDID...................................................................... 63
Flash Page Number Status Register – PNSR ................................................................................ 64
Flash Page Size Status Register – PSSR ...................................................................................... 65
Flash Cache & Pre-fetch Control Register – CFCR........................................................................ 66
Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 67
5 Power Control Unit (PWRCU) .............................................................................. 68
Introduction .......................................................................................................................... 68
Features............................................................................................................................... 69
Functional Descriptions ....................................................................................................... 69
Backup Domain .............................................................................................................................. 69
VDD Power Domain.......................................................................................................................... 70
1.5 V Power Domain....................................................................................................................... 72
Operation Modes ............................................................................................................................ 72
Register Map ....................................................................................................................... 74
Register Descriptions........................................................................................................... 75
Backup Domain Status Register – BAKSR..................................................................................... 75
Backup Domain Control Register – BAKCR ................................................................................... 76
Backup Domain Test Register – BAKTEST .................................................................................... 78
Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 79
Backup Register n – BAKREGn, n = 0 ~ 9 ..................................................................................... 81
6 Clock Control Unit (CKCU) .................................................................................. 82
Introduction .......................................................................................................................... 82
Features............................................................................................................................... 84
Function Descriptions .......................................................................................................... 84
High Speed External Crystal Oscillator – HSE ............................................................................... 84
High Speed Internal RC Oscillator – HSI........................................................................................ 85
Auto Trimming of High Speed Internal RC Oscillator – HSI............................................................ 85
Phase Locked Loop – PLL.............................................................................................................. 87
Low Speed External Crystal Oscillator – LSE................................................................................. 89
Low Speed Internal RC Oscillator – LSI ......................................................................................... 89
Clock Ready Flag ........................................................................................................................... 89
System Clock (CK_SYS) Selection ................................................................................................ 90
HSE Clock Monitor ......................................................................................................................... 91
Clock Output Capability .................................................................................................................. 91
Register Map ....................................................................................................................... 92
Register Descriptions........................................................................................................... 93
Global Clock Conguration Register – GCFGR.............................................................................. 93
Global Clock Control Register – GCCR.......................................................................................... 95
Global Clock Status Register – GCSR ........................................................................................... 97
Global Clock Interrupt Register – GCIR.......................................................................................... 98
PLL Conguration Register – PLLCFGR ........................................................................................ 99

Rev. 1.30 4 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
PLL Control Register – PLLCR....................................................................................................... 99
AHB Conguration Register – AHBCFGR .................................................................................... 100
AHB Clock Control Register – AHBCCR ...................................................................................... 101
APB Conguration Register – APBCFGR..................................................................................... 103
APB Clock Control Register 0 – APBCCR0.................................................................................. 104
APB Clock Control Register 1 – APBCCR1.................................................................................. 106
Clock Source Status Register – CKST ......................................................................................... 108
APB Peripheral Clock Selection Register 0 – APBPCSR0........................................................... 109
APB Peripheral Clock Selection Register 1 – APBPCSR1............................................................111
HSI Control Register – HSICR.......................................................................................................113
HSI Auto Trimming Counter Register – HSIATCR .........................................................................114
Low Power Control Register – LPCR ............................................................................................115
MCU Debug Control Register – MCUDBGCR...............................................................................116
7 Reset Control Unit (RSTCU) .............................................................................. 119
Introduction ........................................................................................................................ 119
Functional Descriptions ..................................................................................................... 120
Power On Reset ........................................................................................................................... 120
System Reset ............................................................................................................................... 120
AHB and APB Unit Reset.............................................................................................................. 120
Register Map ..................................................................................................................... 121
Register Descriptions......................................................................................................... 121
Global Reset Status Register – GRSR ......................................................................................... 121
AHB Peripheral Reset Register – AHBPRSTR............................................................................. 122
APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 123
APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 125
8 General Purpose I/O (GPIO)............................................................................... 127
Introduction ........................................................................................................................ 127
Features............................................................................................................................. 128
Functional Descriptions ..................................................................................................... 128
Default GPIO Pin Conguration.................................................................................................... 128
General Purpose I/O – GPIO........................................................................................................ 128
GPIO Locking Mechanism ............................................................................................................ 130
Register Map ..................................................................................................................... 130
Register Descriptions......................................................................................................... 131
Port A Data Direction Control Register – PADIRCR ..................................................................... 131
Port A Input Function Enable Control Register – PAINER ............................................................ 132
Port A Pull-Up Selection Register – PAPUR ................................................................................. 133
Port A Pull-Down Selection Register – PAPDR ............................................................................ 134
Port A Open Drain Selection Register – PAODR .......................................................................... 135
Port A Output Current Drive Selection Register – PADRVR ......................................................... 136
Port A Lock Register – PALOCKR ................................................................................................ 137
Port A Data Input Register – PADINR........................................................................................... 138

Rev. 1.30 5 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Port A Output Data Register – PADOUTR .................................................................................... 139
Port A Output Set/Reset Control Register – PASRR .................................................................... 140
Port A Output Reset Register – PARR.......................................................................................... 141
Port B Data Direction Control Register – PBDIRCR..................................................................... 142
Port B Input Function Enable Control Register – PBINER ........................................................... 143
Port B Pull-Up Selection Register – PBPUR ................................................................................ 144
Port B Pull-Down Selection Register – PBPDR............................................................................ 145
Port B Open Drain Selection Register – PBODR ......................................................................... 146
Port B Output Current Drive Selection Register – PBDRVR ........................................................ 147
Port B Lock Register – PBLOCKR................................................................................................ 148
Port B Data Input Register – PBDINR .......................................................................................... 149
Port B Output Data Register – PBDOUTR ................................................................................... 150
Port B Output Set/Reset Control Register – PBSRR.................................................................... 151
Port B Output Reset Register – PBRR ......................................................................................... 152
Port C Data Direction Control Register – PCDIRCR .................................................................... 153
Port C Input Function Enable Control Register – PCINER ........................................................... 154
Port C Pull-Up Selection Register – PCPUR ................................................................................ 155
Port C Pull-Down Selection Register – PCPDR ........................................................................... 156
Port C Open Drain Selection Register – PCODR ......................................................................... 157
Port C Output Current Drive Selection Register – PCDRVR ........................................................ 158
Port C Lock Register – PCLOCKR ............................................................................................... 159
Port C Data Input Register – PCDINR.......................................................................................... 160
Port C Output Data Register – PCDOUTR ................................................................................... 161
Port C Output Set/Reset Control Register – PCSRR ................................................................... 162
Port C Output Reset Register – PCRR......................................................................................... 163
Port D Data Direction Control Register – PDDIRCR .................................................................... 164
Port D Input Function Enable Control Register – PDINER ........................................................... 165
Port D Pull-Up Selection Register – PDPUR ................................................................................ 166
Port D Pull-Down Selection Register – PDPDR ........................................................................... 167
Port D Open Drain Selection Register – PDODR ......................................................................... 168
Port D Output Current Drive Selection Register – PDDRVR ........................................................ 169
Port D Lock Register – PDLOCKR ............................................................................................... 170
Port D Data Input Register – PDDINR.......................................................................................... 171
Port D Output Data Register – PDDOUTR ................................................................................... 172
Port D Output Set/Reset Control Register – PDSRR ................................................................... 173
Port D Output Reset Register – PDRR......................................................................................... 174
9 Alternate Function Input/Output Control Unit (AFIO)...................................... 175
Introduction ........................................................................................................................ 175
Features............................................................................................................................. 176
Functional Descriptions ..................................................................................................... 176
External Interrupt Pin Selection .................................................................................................... 176
Alternate Function......................................................................................................................... 177
Lock Mechanism .......................................................................................................................... 177
Register Map ..................................................................................................................... 177

Rev. 1.30 6 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Register Descriptions......................................................................................................... 178
EXTI Source Selection Register 0 – ESSR0 ................................................................................ 178
EXTI Source Selection Register 1 – ESSR1 ................................................................................ 179
GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C, D............................................... 180
GPIO x Conguration High Register – GPxCFGHR, x = A, B, C, D ............................................. 181
10 Nested Vectored Interrupt Controller (NVIC).................................................. 182
Introduction ........................................................................................................................ 182
Features............................................................................................................................. 183
Function Descriptions ........................................................................................................ 184
SysTick Calibration ....................................................................................................................... 184
Register Map ..................................................................................................................... 184
11 External Interrupt/Event Controller (EXTI)...................................................... 185
Introduction ........................................................................................................................ 185
Features............................................................................................................................. 185
Function Descriptions ........................................................................................................ 186
Wakeup Event Management......................................................................................................... 186
External Interrupt/Event Line Mapping ......................................................................................... 187
Interrupt and Debounce ................................................................................................................ 187
Register Map ..................................................................................................................... 188
Register Descriptions......................................................................................................... 189
EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 189
EXTI Interrupt Control Register – EXTICR ................................................................................... 190
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR................................................................ 191
EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 192
EXTI Interrupt Software Set Command Register – EXTISSCR.................................................... 193
EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 194
EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 195
EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG........................................................... 196
12 Analog to Digital Converter (ADC) .................................................................. 197
Introduction ........................................................................................................................ 197
Features............................................................................................................................. 198
Function Descriptions ........................................................................................................ 199
ADC Clock Setup.......................................................................................................................... 199
Channel Selection......................................................................................................................... 199
Conversion Mode.......................................................................................................................... 199
Start Conversion on External Event.............................................................................................. 202
Sampling Time Setting.................................................................................................................. 203
Data Format.................................................................................................................................. 203
Analog Watchdog.......................................................................................................................... 203
Interrupts....................................................................................................................................... 204
PDMA Request ............................................................................................................................ 204

Rev. 1.30 7 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Register Map ..................................................................................................................... 205
Register Descriptions......................................................................................................... 206
ADC Conversion Control Register – ADCCR ............................................................................... 206
ADC Conversion List Register 0 – ADCLST0............................................................................... 208
ADC Conversion List Register 1 – ADCLST1............................................................................... 209
ADC Input Sampling Time Register – ADCSTR ........................................................................... 210
ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ................................................................211
ADC Trigger Control Register – ADCTCR .................................................................................... 212
ADC Trigger Source Register – ADCTSR..................................................................................... 213
ADC Watchdog Control Register – ADCWCR .............................................................................. 214
ADC Watchdog Threshold Register – ADCTR.............................................................................. 215
ADC Interrupt Enable Register – ADCIER.................................................................................... 216
ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 217
ADC Interrupt Status Register – ADCISR..................................................................................... 218
ADC Interrupt Clear Register – ADCICLR .................................................................................... 219
ADC DMA Request Register – ADCDMAR................................................................................... 220
13 Comparator (CMP) ............................................................................................ 221
Introduction ........................................................................................................................ 221
Features............................................................................................................................. 221
Function Descriptions ........................................................................................................ 222
Comparator Inputs and Output ..................................................................................................... 222
Comparator Voltage Reference .................................................................................................... 222
Interrupts and Wakeup.................................................................................................................. 223
Power Mode and Hysteresis......................................................................................................... 224
Comparator Write-Protected mechanism ..................................................................................... 224
Register Map ..................................................................................................................... 224
Register Descriptions......................................................................................................... 225
Comparator Control Register n – CMPCRn, n = 0 or 1 ................................................................ 225
Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1................................. 227
Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 ................................................. 228
Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 .................................................. 229
14 General-Purpose Timer (GPTM) ...................................................................... 230
Introduction ........................................................................................................................ 230
Features............................................................................................................................. 231
Functional Descriptions ..................................................................................................... 232
Counter Mode ............................................................................................................................... 232
Clock Controller ............................................................................................................................ 235
Trigger Controller.......................................................................................................................... 236
Slave Controller ............................................................................................................................ 237
Master Controller .......................................................................................................................... 240
Channel Controller........................................................................................................................ 241
Input Stage ................................................................................................................................... 244

Rev. 1.30 8 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Quadrature Decoder ..................................................................................................................... 246
Output Stage................................................................................................................................. 248
Update Management .................................................................................................................... 252
Single Pulse Mode........................................................................................................................ 253
Asymmetric PWM Mode ............................................................................................................... 255
Timer Interconnection ................................................................................................................... 256
Trigger ADC Start.......................................................................................................................... 259
PDMA Request ............................................................................................................................. 259
Register Map ..................................................................................................................... 260
Register Descriptions......................................................................................................... 261
Timer Counter Conguration Register – CNTCFR ....................................................................... 261
Timer Mode Conguration Register – MDCFR............................................................................. 263
Timer Trigger Conguration Register – TRCFR............................................................................ 266
Timer Counter Register – CTR ..................................................................................................... 267
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 268
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 270
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 272
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 274
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 276
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 278
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 280
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 282
Channel Control Register – CHCTR............................................................................................. 284
Channel Polarity Conguration Register – CHPOLR.................................................................... 285
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 286
Timer Event Generator Register – EVGR..................................................................................... 288
Timer Interrupt Status Register – INTSR...................................................................................... 290
Timer Counter Register – CNTR................................................................................................... 293
Timer Prescaler Register – PSCR ................................................................................................ 294
Timer Counter Reload Register – CRR ........................................................................................ 295
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 296
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 297
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 298
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 299
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 300
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 301
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 302
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 303
15 Basic Function Timer (BFTM).......................................................................... 304
Introduction ........................................................................................................................ 304
Features............................................................................................................................. 304
Functional Description ....................................................................................................... 305
Repetitive Mode............................................................................................................................ 305
One Shot Mode............................................................................................................................. 306

Rev. 1.30 9 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Register Map ..................................................................................................................... 307
Register Descriptions......................................................................................................... 307
BFTM Control Register – BFTMCR .............................................................................................. 307
BFTM Status Register – BFTMSR................................................................................................ 308
BFTM Counter Register – BFTMCNTR ........................................................................................ 309
BFTM Compare Value Register – BFTMCMPR ........................................................................... 310
16 Motor Control Timer (MCTM) ........................................................................... 311
Introduction ........................................................................................................................ 311
Features............................................................................................................................. 312
Functional Descriptions ..................................................................................................... 313
Counter Mode ............................................................................................................................... 313
Clock Controller ............................................................................................................................ 317
Trigger Controller.......................................................................................................................... 318
Slave Controller ............................................................................................................................ 319
Master Controller .......................................................................................................................... 321
Channel Controller........................................................................................................................ 322
Input Stage ................................................................................................................................... 325
Output Stage................................................................................................................................. 327
Update Management .................................................................................................................... 337
Single Pulse Mode........................................................................................................................ 339
Asymmetric PWM Mode ............................................................................................................... 341
Timer Interconnection ................................................................................................................... 342
Trigger ADC Start.......................................................................................................................... 346
Lock Level Table ........................................................................................................................... 346
PDMA Request ............................................................................................................................. 347
Register Map ..................................................................................................................... 348
Register Descriptions......................................................................................................... 349
Timer Counter Conguration Register – CNTCFR ....................................................................... 349
Timer Mode Conguration Register – MDCFR............................................................................. 351
Timer Trigger Conguration Register – TRCFR............................................................................ 354
Timer Counter Register – CTR ..................................................................................................... 355
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 356
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 358
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 360
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 362
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 364
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 366
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 368
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 370
Channel Control Register – CHCTR............................................................................................. 372
Channel Polarity Conguration Register – CHPOLR.................................................................... 374
Channel Break Conguration Register – CHBRKCFR ................................................................. 376
Channel Break Control Register – CHBRKCTR ........................................................................... 377

Rev. 1.30 10 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 379
Timer Event Generator Register – EVGR..................................................................................... 381
Timer Interrupt Status Register – INTSR...................................................................................... 383
Timer Counter Register – CNTR................................................................................................... 386
Timer Prescaler Register – PSCR ................................................................................................ 387
Timer Counter Reload Register – CRR ........................................................................................ 388
Timer Repetition Register – REPR ............................................................................................... 389
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 390
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 391
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 392
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 393
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 394
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 395
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 396
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 397
17 Single-Channel Timer (SCTM) ......................................................................... 398
Introduction ........................................................................................................................ 398
Features............................................................................................................................. 399
Functional Descriptions ..................................................................................................... 399
Counter Mode ............................................................................................................................... 399
Clock Controller ............................................................................................................................ 400
Trigger Controller.......................................................................................................................... 401
Slave Controller ............................................................................................................................ 402
Channel Controller........................................................................................................................ 404
Input Stage ................................................................................................................................... 406
Output Stage................................................................................................................................. 407
Update Management .................................................................................................................... 409
Register Map ..................................................................................................................... 410
Register Descriptions......................................................................................................... 411
Timer Counter Conguration Register – CNTCFR ........................................................................411
Timer Mode Conguration Register – MDCFR............................................................................. 412
Timer Trigger Conguration Register – TRCFR............................................................................ 413
Timer Counter Register – CTR ..................................................................................................... 414
Channel Input Conguration Register – CHICFR ......................................................................... 415
Channel Output Conguration Register – CHOCFR .................................................................... 417
Channel Control Register – CHCTR............................................................................................. 418
Channel Polarity Conguration Register – CHPOLR.................................................................... 419
Timer Interrupt Control Register – DICTR .................................................................................... 420
Timer Event Generator Register – EVGR..................................................................................... 421
Timer Interrupt Status Register – INTSR...................................................................................... 422
Timer Counter Register – CNTR................................................................................................... 423
Timer Prescaler Register – PSCR ................................................................................................ 424
Timer Counter Reload Register – CRR ........................................................................................ 425
Channel Capture/Compare Register – CHCCR ........................................................................... 426

Rev. 1.30 11 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
18 Real Time Clock (RTC) ..................................................................................... 427
Introduction ........................................................................................................................ 427
Features............................................................................................................................. 427
Functional Descriptions ..................................................................................................... 428
RTC Related Register Reset ........................................................................................................ 428
Reading RTC Register.................................................................................................................. 428
Low Speed Clock Conguration ................................................................................................... 428
RTC Counter Operation................................................................................................................ 429
Interrupt and Wakeup Control....................................................................................................... 429
RTCOUT Output Pin Conguration............................................................................................... 430
Register Map ..................................................................................................................... 431
Register Descriptions......................................................................................................... 431
RTC Counter Register – RTCCNT................................................................................................ 431
RTC Compare Register – RTCCMP............................................................................................. 432
RTC Control Register – RTCCR................................................................................................... 433
RTC Status Register – RTCSR..................................................................................................... 435
RTC Interrupt and Wakeup Enable Register – RTCIWEN............................................................ 436
19 Watchdog Timer (WDT) .................................................................................... 437
Introduction ........................................................................................................................ 437
Features............................................................................................................................. 437
Functional Description ....................................................................................................... 438
Register Map ..................................................................................................................... 440
Register Descriptions......................................................................................................... 440
Watchdog Timer Control Register – WDTCR ............................................................................... 440
Watchdog Timer Mode Register 0 – WDTMR0............................................................................. 441
Watchdog Timer Mode Register 1 – WDTMR1............................................................................. 442
Watchdog Timer Status Register – WDTSR ................................................................................. 443
Watchdog Timer Protection Register – WDTPR ........................................................................... 444
Watchdog Timer Clock Selection Register – WDTCSR................................................................ 445
20 Inter-Integrated Circuit (I2C)............................................................................. 446
Introduction ........................................................................................................................ 446
Features............................................................................................................................. 447
Functional Descriptions ..................................................................................................... 447
Two Wire Serial Interface.............................................................................................................. 447
START and STOP Conditions....................................................................................................... 447
Data Validity.................................................................................................................................. 448
Addressing Format ....................................................................................................................... 449
Data Transfer and Acknowledge................................................................................................... 451
Clock Synchronization .................................................................................................................. 452
Arbitration ..................................................................................................................................... 452
General Call Addressing ............................................................................................................... 453

Rev. 1.30 12 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Bus Error....................................................................................................................................... 453
Address Mask Enable................................................................................................................... 453
Address Snoop ............................................................................................................................. 453
Operation Mode ............................................................................................................................ 453
Conditions of Holding SCL Line.................................................................................................... 459
I2C Timeout Function .................................................................................................................... 460
PDMA Interface............................................................................................................................. 460
Register Map ..................................................................................................................... 461
Register Descriptions......................................................................................................... 462
I2C Control Register – I2CCR ....................................................................................................... 462
I2C Interrupt Enable Register – I2CIER ........................................................................................ 464
I2C Address Register – I2CADDR................................................................................................. 466
I2C Status Register – I2CSR......................................................................................................... 467
I2C SCL High Period Generation Register – I2CSHPGR.............................................................. 470
I2C SCL Low Period Generation Register – I2CSLPGR ............................................................... 471
I2C Data Register – I2CDR ........................................................................................................... 472
I2C Target Register – I2CTAR ....................................................................................................... 473
I2C Address Mask Register – I2CADDMR .................................................................................... 474
I2C Address Snoop Register – I2CADDSR................................................................................... 475
I2C Timeout Register – I2CTOUT.................................................................................................. 476
21 Serial Peripheral Interface (SPI) ...................................................................... 477
Introduction ........................................................................................................................ 477
Features............................................................................................................................. 478
Function Descriptions ........................................................................................................ 478
Master Mode................................................................................................................................. 478
Slave Mode................................................................................................................................... 478
SPI Serial Frame Format .............................................................................................................. 479
Status Flags.................................................................................................................................. 483
Register Map ..................................................................................................................... 486
Register Descriptions......................................................................................................... 486
SPI Control Register 0 – SPICR0 ................................................................................................. 486
SPI Control Register 1 – SPICR1 ................................................................................................. 488
SPI Interrupt Enable Register – SPIIER ....................................................................................... 490
SPI Clock Prescaler Register – SPICPR ...................................................................................... 491
SPI Data Register – SPIDR .......................................................................................................... 492
SPI Status Register – SPISR........................................................................................................ 493
SPI FIFO Control Register – SPIFCR........................................................................................... 495
SPI FIFO Status Register – SPIFSR ............................................................................................ 496
SPI FIFO Time Out Counter Register – SPIFTOCR..................................................................... 497
22 Universal Synchronous Asynchronous Receiver Transmitter (USART) ..... 498
Introduction ........................................................................................................................ 498
Features............................................................................................................................. 499

Rev. 1.30 13 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Function Descriptions ........................................................................................................ 500
Serial Data Format........................................................................................................................ 500
Baud Rate Generation .................................................................................................................. 501
Hardware Flow Control ................................................................................................................. 502
IrDA............................................................................................................................................... 504
RS485 Mode................................................................................................................................. 506
Synchronous Master Mode........................................................................................................... 509
Interrupts and Status .....................................................................................................................511
PDMA Interface..............................................................................................................................511
Register Map ..................................................................................................................... 511
Register Descriptions......................................................................................................... 512
USART Data Register – USRDR.................................................................................................. 512
USART Control Register – USRCR.............................................................................................. 513
USART FIFO Control Register – USRFCR................................................................................... 515
USART Interrupt Enable Register – USRIER ............................................................................... 516
USART Status & Interrupt Flag Register – USRSIFR................................................................... 518
USART Timing Parameter Register – USRTPR ........................................................................... 520
USART IrDA Control Register – IrDACR ...................................................................................... 521
USART RS485 Control Register – RS485CR............................................................................... 522
USART Synchronous Control Register – SYNCR ........................................................................ 523
USART Divider Latch Register – USRDLR................................................................................... 524
USART Test Register – USRTSTR............................................................................................... 525
23 Universal Asynchronous Receiver Transmitter (UART)................................ 526
Introduction ........................................................................................................................ 526
Features............................................................................................................................. 527
Function Descriptions ........................................................................................................ 527
Serial Data Format........................................................................................................................ 527
Baud Rate Generation .................................................................................................................. 528
Interrupts and Status .................................................................................................................... 529
PDMA Interface............................................................................................................................. 529
Register Map ..................................................................................................................... 530
Register Descriptions......................................................................................................... 530
UART Data Register – URDR....................................................................................................... 530
UART Control Register – URCR................................................................................................... 531
UART Interrupt Enable Register – URIER.................................................................................... 533
UART Status & Interrupt Flag Register – URSIFR ....................................................................... 534
UART Divider Latch Register – URDLR ....................................................................................... 536
UART Test Register – URTSTR.................................................................................................... 537
24 Smart Card Interface (SCI) ............................................................................... 538
Introduction ........................................................................................................................ 538
Features............................................................................................................................. 539
Functional Descriptions ..................................................................................................... 539

Rev. 1.30 14 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Elementary Time Unit Counter...................................................................................................... 539
Guard Time Counter ..................................................................................................................... 541
Waiting Time Counter ................................................................................................................... 542
Card Clock and Data Selection..................................................................................................... 543
Card Detection ............................................................................................................................. 543
SCI Data Transfer Mode ............................................................................................................... 544
Interrupt Generator ....................................................................................................................... 546
PDMA Interface............................................................................................................................. 547
Register Map ..................................................................................................................... 547
Register Descriptions......................................................................................................... 548
SCI Control Register – CR............................................................................................................ 548
SCI Status Register – SR ............................................................................................................. 550
SCI Contact Control Register – CCR............................................................................................ 552
SCI Elementary Time Unit Register – ETUR ................................................................................ 553
SCI Guard Time Register – GTR .................................................................................................. 554
SCI Waiting Time Register – WTR................................................................................................ 555
SCI Interrupt Enable Register – IER............................................................................................. 556
SCI Interrupt Pending Register – IPR........................................................................................... 558
SCI Transmit Buffer – TXB............................................................................................................ 560
SCI Receive Buffer – RXB............................................................................................................ 560
SCI Prescaler Register – PSCR ................................................................................................... 561
25 USB Device Controller (USB) .......................................................................... 562
Introduction ........................................................................................................................ 562
Features............................................................................................................................. 562
Functional Descriptions ..................................................................................................... 563
Endpoints...................................................................................................................................... 563
EP-SRAM ..................................................................................................................................... 563
Serial Interface Engine – SIE........................................................................................................ 564
Double-Buffering........................................................................................................................... 564
Suspend Mode and Wake-up ....................................................................................................... 566
Remote Wake-up.......................................................................................................................... 566
Register Map ..................................................................................................................... 566
Register Descriptions......................................................................................................... 568
USB Control and Status Register – USBCSR .............................................................................. 568
USB Interrupt Enable Register – USBIER .................................................................................... 570
USB Interrupt Status Register – USBISR ..................................................................................... 571
USB Frame Count Register – USBFCR ....................................................................................... 573
USB Device Address Register – USBDEVA ................................................................................. 574
USB Endpoint 0 Control and Status Register – USBEP0CSR ..................................................... 575
USB Endpoint 0 Interrupt Enable Register – USBEP0IER ........................................................... 576
USB Endpoint 0 Interrupt Status Register – USBEP0ISR ............................................................ 578
USB Endpoint 0 Transfer Count Register – USBEP0TCR ........................................................... 579
USB Endpoint 0 Conguration Register – USBEP0CFGR ........................................................... 580

Rev. 1.30 15 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
USB Endpoint 1 ~ 3 Control and Status Register – USBEPnCSR, n = 1 ~ 3............................... 581
USB Endpoint 1 ~ 3 Interrupt Enable Register – USBEPnIER, n = 1 ~ 3..................................... 582
USB Endpoint 1 ~ 3 Interrupt Status Register – USBEPnISR, n = 1 ~ 3...................................... 583
USB Endpoint 1 ~ 3 Transfer Count Register – USBEPnTCR, n = 1 ~ 3 ..................................... 584
USB Endpoint 1 ~ 3 Conguration Register – USBEPnCFGR, n = 1 ~ 3..................................... 585
USB Endpoint 4 ~ 7 Control and Status Register – USBEPnCSR, n = 4 ~ 7............................... 586
USB Endpoint 4 ~ 7 Interrupt Enable Register – USBEPnIER, n = 4 ~ 7..................................... 589
USB Endpoint 4 ~ 7 Interrupt Status Register – USBEPnISR, n = 4 ~ 7...................................... 590
USB Endpoint 4 ~ 7 Transfer Count Register – USBEPnTCR, n = 4 ~ 7 ..................................... 591
USB Endpoint 4 ~ 7 Conguration Register – USBEPnCFGR, n = 4 ~ 7..................................... 592
26 Peripheral Direct Memory Access (PDMA)..................................................... 593
Introduction ........................................................................................................................ 593
Features............................................................................................................................. 593
Functional Description ....................................................................................................... 594
AHB Master .................................................................................................................................. 594
PDMA Channel ............................................................................................................................. 594
PDMA Request Mapping .............................................................................................................. 594
Channel transfer ........................................................................................................................... 596
Channel Priority ............................................................................................................................ 596
Transfer Request .......................................................................................................................... 597
Address Mode............................................................................................................................... 597
Auto-Reload.................................................................................................................................. 597
Transfer Interrupt .......................................................................................................................... 598
Register Map ..................................................................................................................... 598
Register Descriptions......................................................................................................... 600
PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5 .................................................... 600
PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5.................................. 602
PDMA Channel n Destination Address Register – PDMACHnDADR, n=0~5............................... 603
PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5......................................... 604
PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n=0~5............................. 605
PDMA Interrupt Status Register – PDMAISR ............................................................................... 606
PDMA Interrupt Status Clear Register – PDMAISCR................................................................... 607
PDMA Interrupt Enable Register – PDMAIER .............................................................................. 609
27 Extend Bus Interface (EBI)............................................................................... 610
Introduction ........................................................................................................................ 610
Features............................................................................................................................. 610
Function Descriptions ........................................................................................................ 611
Non-multiplexed 8-bit Data 8-bit Address Mode ........................................................................... 612
Non-multiplexed 16-bit Data N-bit Address Mode......................................................................... 613
Multiplexed 16-bit Data, 16-bit Address Mode.............................................................................. 614
Multiplexed 8-bit Data, 20-bit Address Mode................................................................................ 615
Write Buffer and EBI Status.......................................................................................................... 616

Rev. 1.30 16 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Bus Turn-around and Idle Cycles ................................................................................................. 616
AHB Transaction Width Conversion ............................................................................................. 617
EBI Bank Access .......................................................................................................................... 619
PDMA Request ............................................................................................................................. 620
Register Map ..................................................................................................................... 620
Register Descriptions......................................................................................................... 620
EBI Control Register – EBICR ...................................................................................................... 620
EBI Status Register – EBISR........................................................................................................ 622
EBI Address Timing Register – EBIATR ....................................................................................... 623
EBI Read Timing Register – EBIRTR ........................................................................................... 624
EBI Write Timing Register – EBIWTR........................................................................................... 625
EBI Parity Register – EBIPR......................................................................................................... 626
28 Inter-IC Sound (I2S) ........................................................................................... 627
Introduction ........................................................................................................................ 627
Features............................................................................................................................. 627
Functional Description ....................................................................................................... 628
I2S Master and Slave Mode .......................................................................................................... 628
I2S Clock Rate Generator ............................................................................................................. 629
I2S Interface Format...................................................................................................................... 631
FIFO Control and Arrangement .................................................................................................... 638
PDMA and Interrupt ...................................................................................................................... 639
Register Map ..................................................................................................................... 639
Register Descriptions......................................................................................................... 640
I2S Control Register – I2SCR........................................................................................................ 640
I2S Interrupt Enable Register – I2SIER......................................................................................... 642
I2S Clock Divider Register – I2SCDR ........................................................................................... 643
I2S TX Data Register – I2STXDR ................................................................................................. 644
I2S RX Data Register – I2SRXDR................................................................................................. 644
I2S FIFO Control Register – I2SFCR ............................................................................................ 645
I2S Status Register – I2SSR ......................................................................................................... 646
I2S Rate Counter Value Register – I2SRCNTR ............................................................................ 648
29 Cyclic Redundancy Check (CRC).................................................................... 649
Introduction ....................................................................................................................... 649
Features............................................................................................................................. 650
Function Descriptions ........................................................................................................ 650
CRC Computation......................................................................................................................... 650
Byte and Bit Reversal for CRC Computation................................................................................ 650
CRC with PDMA ........................................................................................................................... 651
Register Map ..................................................................................................................... 651
Register Descriptions......................................................................................................... 652
CRC Control Register – CRCCR .................................................................................................. 652
CRC Seed Register – CRCSDR................................................................................................... 653

Rev. 1.30 17 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
CRC Checksum Register – CRCCSR .......................................................................................... 654
CRC Data Register – CRCDR ...................................................................................................... 655

Rev. 1.30 18 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
List of Tables
List of Tables
Table 1. Series Features and Peripheral List.......................................................................................... 32
Table 2. Document Conventions............................................................................................................. 34
Table 3. Register Map............................................................................................................................. 39
Table 4. Flash Memory and Option Byte................................................................................................. 44
Table 5. Relationship Between Wait State Cycle and HCLK .................................................................. 44
Table 6. Booting Modes .......................................................................................................................... 45
Table 7. Option Byte Memory Map ......................................................................................................... 49
Table 8. Access Permission of Protected Main Flash Page.................................................................... 50
Table 9. Access Permission When Security Protection is Enabled......................................................... 51
Table 10. FMC Register Map .................................................................................................................. 52
Table 11. Operation Mode Denitions..................................................................................................... 72
Table 12. Enter/Exit Power Saving Modes.............................................................................................. 73
Table 13. Power Status After System Reset ........................................................................................... 74
Table 14. PWRCU Register Map ............................................................................................................ 74
Table 15. Output Divider2 Value Mapping............................................................................................... 88
Table 16. Feedback Divider2 Value Mapping.......................................................................................... 88
Table 17. CKOUT Clock Source ............................................................................................................. 91
Table 18. CKCU Register Map ............................................................................................................... 92
Table 19. RSTCU Register Map ........................................................................................................... 121
Table 20. AFIO, GPIO and IO Pad Control Signal True Table............................................................... 129
Table 21. GPIO Register Map............................................................................................................... 130
Table 22. AFIO Selection for Peripheral Map Example......................................................................... 177
Table 23. AFIO Register Map................................................................................................................ 177
Table 24. Exception Types.................................................................................................................... 182
Table 25. NVIC Register Map ............................................................................................................... 184
Table 26. EXTI Register Map................................................................................................................ 188
Table 27. Data format in ADCDR [15:0] ................................................................................................ 203
Table 28. A/D Converter Register Map ................................................................................................. 205
Table 29. CMP Register Map................................................................................................................ 224
Table 30. Counting Direction and Encoding Signals............................................................................. 247
Table 31. Compare Match Output Setup .............................................................................................. 248
Table 32. GPTM Register Map ............................................................................................................. 260
Table 33. GPTM Internal Trigger Connection ....................................................................................... 266
Table 34. BFTM Register Map .............................................................................................................. 307
Table 35. Compare Match Output Setup .............................................................................................. 328
Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence.................. 336
Table 37. Lock Level Table.................................................................................................................... 346
Table 38. MCTM Register Map ............................................................................................................. 348
Table 39. MCTM Internal Trigger Connection ....................................................................................... 354

Rev. 1.30 19 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
List of Tables List of Tables
Table 40. Compare Match Output Setup .............................................................................................. 407
Table 41. SCTM Register Map.............................................................................................................. 410
Table 42. LSE Startup Mode Operating Current and Startup Time....................................................... 428
Table 43. RTCOUT Output Mode and Active Level Setting .................................................................. 430
Table 44. RTC Register Map................................................................................................................. 431
Table 45. Watchdog Timer Register Map.............................................................................................. 440
Table 46. Conditions of Holding SCL line.............................................................................................. 459
Table 47. I2C Register Map ................................................................................................................... 461
Table 48. I2C Clock Setting Example .................................................................................................... 471
Table 49. SPI Interface Format Setup................................................................................................... 479
Table 50. SPI Mode Fault Trigger Conditions ....................................................................................... 484
Table 51. SPI Master Mode SEL Pin Status ......................................................................................... 484
Table 52. SPI Register Map .................................................................................................................. 486
Table 53. Baud Rate Deviation Error Calculation – CK_USART = 40 MHz.......................................... 501
Table 54. Baud Rate Deviation Error Calculation – CK_USART = 48 MHz.......................................... 502
Table 55. USART Register Map.............................................................................................................511
Table 56. Baud Rate Deviation Error Calculation – CK_UART = 40 MHz ............................................ 528
Table 57. Baud Rate Deviation Error Calculation – CK_UART = 48 MHz ............................................ 529
Table 58. UART Register Map .............................................................................................................. 530
Table 59. DI Field Based Di Encoded Decimal Values ......................................................................... 540
Table 60. FI Field Based FiEncoded Decimal Values .......................................................................... 540
Table 61. Possible ETU Values Obtained with the Fi/Di Ratio.............................................................. 540
Table 62. SCI Register Map ................................................................................................................. 547
Table 63. Endpoint Characteristics ....................................................................................................... 563
Table 64. USB Data Types and Buffer Size .......................................................................................... 563
Table 65. USB Register Map ................................................................................................................ 566
Table 66. Resume Event Detection ...................................................................................................... 569
Table 67. PDMA Channel Assignments ................................................................................................ 595
Table 68. PDMA Address Modes .......................................................................................................... 597
Table 69. PDMA Register Map.............................................................................................................. 598
Table 70. EBI Maps AHB Transactions Width to External Device Transactions. .................................. 618
Table 71. EBI Maps AHB Transactions Width to External Device Transactions Width ......................... 618
Table 72. EBI Register Map .................................................................................................................. 620
Table 73. Recommend FS List @ 8 MHz PCLK ................................................................................... 630
Table 74. Recommend FS List @ 48 MHz PCLK ................................................................................. 630
Table 75. I2S Register Map .................................................................................................................. 639
Table 76. CRC Register Map ................................................................................................................ 651

Rev. 1.30 20 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
List of Figures
List of Figures
Figure 1. Block Diagram ......................................................................................................................... 33
Figure 2. Cortex®-M0+ Block Diagram.................................................................................................... 36
Figure 3. Bus Architecture ...................................................................................................................... 37
Figure 4. Memory Map............................................................................................................................ 38
Figure 5. Flash Memory Controller Block Diagram................................................................................. 42
Figure 6. Flash Memory Map.................................................................................................................. 43
Figure 7. Vector Remapping ................................................................................................................... 45
Figure 8. Page Erase Operation Flowchart ............................................................................................ 46
Figure 9. Mass Erase Operation Flowchart ............................................................................................ 47
Figure 10. Word Programming Operation Flowchart .............................................................................. 48
Figure 11. PWRCU Block Diagram......................................................................................................... 68
Figure 12. Power On Reset / Power Down Reset Waveform ................................................................. 71
Figure 13. CKCU Block Diagram ............................................................................................................ 83
Figure 14. External Crystal, Ceramic, and Resonators for HSE............................................................. 84
Figure 15. HSI Auto Trimming Block Diagram ....................................................................................... 86
Figure 16. PLL Block Diagram ................................................................................................................ 87
Figure 17. External Crystal, Ceramic, and Resonators for LSE ............................................................ 89
Figure 18. RSTCU Block Diagram.........................................................................................................119
Figure 19. Power On Reset Sequence ................................................................................................. 120
Figure 20. GPIO Block Diagram ........................................................................................................... 127
Figure 21. AFIO/GPIO Control Signal................................................................................................... 129
Figure 22. AFIO Block Diagram ............................................................................................................ 175
Figure 23. EXTI Channel Input Selection ............................................................................................. 176
Figure 24. EXTI Block Diagram ............................................................................................................ 185
Figure 25. EXTI Wake-up Event Management ..................................................................................... 186
Figure 26. EXTI Interrupt Debounce Function ...................................................................................... 187
Figure 27. ADC Block Diagram............................................................................................................. 197
Figure 28. One Shot Conversion Mode ................................................................................................ 200
Figure 29. Continuous Conversion Mode ............................................................................................. 200
Figure 30. Discontinuous Conversion Mode......................................................................................... 202
Figure 31. Comparator Block Diagram ................................................................................................. 221
Figure 32. 6-Bit Scaler for Comparator Voltage Reference Block Diagram.......................................... 222
Figure 33. Interrupt Signals of Comparators......................................................................................... 223
Figure 34. Wakeup Signals of Comparators......................................................................................... 223
Figure 35. GPTM Block Diagram.......................................................................................................... 230
Figure 36. Up-counting Example .......................................................................................................... 232
Figure 37. Down-counting Example...................................................................................................... 233
Figure 38. Center-aligned Counting Example....................................................................................... 234
Figure 39. GPTM Clock Selection Source ............................................................................................ 235