Holtek HT32F52342 User manual

Holtek 32-Bit Microcontroller with Arm®Cortex®-M0+ Core
HT32F52342/HT32F52352
User Manual
Revision: V1.30 Date: September 28, 2018

Rev. 1.30 2 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Table of Contents
1 Introduction........................................................................................................... 26
Overview.............................................................................................................................. 26
Features............................................................................................................................... 27
Device Information............................................................................................................... 32
Block Diagram ..................................................................................................................... 33
2 Document Conventions ....................................................................................... 34
3 System Architecture............................................................................................. 35
Arm®Cortex®-M0+ Processor .............................................................................................. 35
Bus Architecture................................................................................................................... 36
Memory Organization .......................................................................................................... 37
Memory Map................................................................................................................................... 38
Embedded Flash Memory............................................................................................................... 41
Embedded SRAM Memory ............................................................................................................. 41
AHB Peripherals ............................................................................................................................. 41
APB Peripherals ............................................................................................................................. 41
4 Flash Memory Controller (FMC) .......................................................................... 42
Introduction .......................................................................................................................... 42
Features............................................................................................................................... 42
Functional Descriptions ....................................................................................................... 43
Flash Memory Map ......................................................................................................................... 43
Flash Memory Architecture ............................................................................................................. 44
Wait State Setting ........................................................................................................................... 44
Booting Conguration ..................................................................................................................... 45
Page Erase ..................................................................................................................................... 46
Mass Erase..................................................................................................................................... 47
Word Programming......................................................................................................................... 48
Option Byte Description .................................................................................................................. 49
Page Erase/Program Protection ..................................................................................................... 49
Security Protection.......................................................................................................................... 51
Register Map ....................................................................................................................... 52
Register Descriptions........................................................................................................... 53
Flash Target Address Register – TADR .......................................................................................... 53
Flash Write Data Register – WRDR ............................................................................................... 54
Flash Operation Command Register – OCMR ............................................................................... 55
Flash Operation Control Register – OPCR..................................................................................... 56
Flash Operation Interrupt Enable Register – OIER ........................................................................ 57
Flash Operation Interrupt and Status Register – OISR .................................................................. 58
Flash Page Erase/Program Protection Status Register – PPSR.................................................... 60
Flash Security Protection Status Register – CPSR ........................................................................ 61

Rev. 1.30 3 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Flash Vector Mapping Control Register – VMCR ........................................................................... 62
Flash Manufacturer and Device ID Register – MDID...................................................................... 63
Flash Page Number Status Register – PNSR ................................................................................ 64
Flash Page Size Status Register – PSSR ...................................................................................... 65
Flash Cache & Pre-fetch Control Register – CFCR........................................................................ 66
Custom ID Register n – CIDRn, n = 0 ~ 3 ...................................................................................... 67
5 Power Control Unit (PWRCU) .............................................................................. 68
Introduction .......................................................................................................................... 68
Features............................................................................................................................... 69
Functional Descriptions ....................................................................................................... 69
Backup Domain .............................................................................................................................. 69
VDD Power Domain.......................................................................................................................... 70
1.5 V Power Domain....................................................................................................................... 72
Operation Modes ............................................................................................................................ 72
Register Map ....................................................................................................................... 74
Register Descriptions........................................................................................................... 75
Backup Domain Status Register – BAKSR..................................................................................... 75
Backup Domain Control Register – BAKCR ................................................................................... 76
Backup Domain Test Register – BAKTEST .................................................................................... 78
Low Voltage / Brown Out Detect Control and Status Register – LVDCSR ..................................... 79
Backup Register n – BAKREGn, n = 0 ~ 9 ..................................................................................... 81
6 Clock Control Unit (CKCU) .................................................................................. 82
Introduction .......................................................................................................................... 82
Features............................................................................................................................... 84
Function Descriptions .......................................................................................................... 84
High Speed External Crystal Oscillator – HSE ............................................................................... 84
High Speed Internal RC Oscillator – HSI........................................................................................ 85
Auto Trimming of High Speed Internal RC Oscillator – HSI............................................................ 85
Phase Locked Loop – PLL.............................................................................................................. 87
Low Speed External Crystal Oscillator – LSE................................................................................. 89
Low Speed Internal RC Oscillator – LSI ......................................................................................... 89
Clock Ready Flag ........................................................................................................................... 89
System Clock (CK_SYS) Selection ................................................................................................ 90
HSE Clock Monitor ......................................................................................................................... 91
Clock Output Capability .................................................................................................................. 91
Register Map ....................................................................................................................... 92
Register Descriptions........................................................................................................... 93
Global Clock Conguration Register – GCFGR.............................................................................. 93
Global Clock Control Register – GCCR.......................................................................................... 95
Global Clock Status Register – GCSR ........................................................................................... 97
Global Clock Interrupt Register – GCIR.......................................................................................... 98
PLL Conguration Register – PLLCFGR ........................................................................................ 99

Rev. 1.30 4 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
PLL Control Register – PLLCR....................................................................................................... 99
AHB Conguration Register – AHBCFGR .................................................................................... 100
AHB Clock Control Register – AHBCCR ...................................................................................... 101
APB Conguration Register – APBCFGR..................................................................................... 103
APB Clock Control Register 0 – APBCCR0.................................................................................. 104
APB Clock Control Register 1 – APBCCR1.................................................................................. 106
Clock Source Status Register – CKST ......................................................................................... 108
APB Peripheral Clock Selection Register 0 – APBPCSR0........................................................... 109
APB Peripheral Clock Selection Register 1 – APBPCSR1............................................................111
HSI Control Register – HSICR.......................................................................................................113
HSI Auto Trimming Counter Register – HSIATCR .........................................................................114
Low Power Control Register – LPCR ............................................................................................115
MCU Debug Control Register – MCUDBGCR...............................................................................116
7 Reset Control Unit (RSTCU) .............................................................................. 119
Introduction ........................................................................................................................ 119
Functional Descriptions ..................................................................................................... 120
Power On Reset ........................................................................................................................... 120
System Reset ............................................................................................................................... 120
AHB and APB Unit Reset.............................................................................................................. 120
Register Map ..................................................................................................................... 121
Register Descriptions......................................................................................................... 121
Global Reset Status Register – GRSR ......................................................................................... 121
AHB Peripheral Reset Register – AHBPRSTR............................................................................. 122
APB Peripheral Reset Register 0 – APBPRSTR0 ........................................................................ 123
APB Peripheral Reset Register 1 – APBPRSTR1 ........................................................................ 125
8 General Purpose I/O (GPIO)............................................................................... 127
Introduction ........................................................................................................................ 127
Features............................................................................................................................. 128
Functional Descriptions ..................................................................................................... 128
Default GPIO Pin Conguration.................................................................................................... 128
General Purpose I/O – GPIO........................................................................................................ 128
GPIO Locking Mechanism ............................................................................................................ 130
Register Map ..................................................................................................................... 130
Register Descriptions......................................................................................................... 131
Port A Data Direction Control Register – PADIRCR ..................................................................... 131
Port A Input Function Enable Control Register – PAINER ............................................................ 132
Port A Pull-Up Selection Register – PAPUR ................................................................................. 133
Port A Pull-Down Selection Register – PAPDR ............................................................................ 134
Port A Open Drain Selection Register – PAODR .......................................................................... 135
Port A Output Current Drive Selection Register – PADRVR ......................................................... 136
Port A Lock Register – PALOCKR ................................................................................................ 137
Port A Data Input Register – PADINR........................................................................................... 138

Rev. 1.30 5 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Port A Output Data Register – PADOUTR .................................................................................... 139
Port A Output Set/Reset Control Register – PASRR .................................................................... 140
Port A Output Reset Register – PARR.......................................................................................... 141
Port B Data Direction Control Register – PBDIRCR..................................................................... 142
Port B Input Function Enable Control Register – PBINER ........................................................... 143
Port B Pull-Up Selection Register – PBPUR ................................................................................ 144
Port B Pull-Down Selection Register – PBPDR............................................................................ 145
Port B Open Drain Selection Register – PBODR ......................................................................... 146
Port B Output Current Drive Selection Register – PBDRVR ........................................................ 147
Port B Lock Register – PBLOCKR................................................................................................ 148
Port B Data Input Register – PBDINR .......................................................................................... 149
Port B Output Data Register – PBDOUTR ................................................................................... 150
Port B Output Set/Reset Control Register – PBSRR.................................................................... 151
Port B Output Reset Register – PBRR ......................................................................................... 152
Port C Data Direction Control Register – PCDIRCR .................................................................... 153
Port C Input Function Enable Control Register – PCINER ........................................................... 154
Port C Pull-Up Selection Register – PCPUR ................................................................................ 155
Port C Pull-Down Selection Register – PCPDR ........................................................................... 156
Port C Open Drain Selection Register – PCODR ......................................................................... 157
Port C Output Current Drive Selection Register – PCDRVR ........................................................ 158
Port C Lock Register – PCLOCKR ............................................................................................... 159
Port C Data Input Register – PCDINR.......................................................................................... 160
Port C Output Data Register – PCDOUTR ................................................................................... 161
Port C Output Set/Reset Control Register – PCSRR ................................................................... 162
Port C Output Reset Register – PCRR......................................................................................... 163
Port D Data Direction Control Register – PDDIRCR .................................................................... 164
Port D Input Function Enable Control Register – PDINER ........................................................... 165
Port D Pull-Up Selection Register – PDPUR ................................................................................ 166
Port D Pull-Down Selection Register – PDPDR ........................................................................... 167
Port D Open Drain Selection Register – PDODR ......................................................................... 168
Port D Output Current Drive Selection Register – PDDRVR ........................................................ 169
Port D Lock Register – PDLOCKR ............................................................................................... 170
Port D Data Input Register – PDDINR.......................................................................................... 171
Port D Output Data Register – PDDOUTR ................................................................................... 172
Port D Output Set/Reset Control Register – PDSRR ................................................................... 173
Port D Output Reset Register – PDRR......................................................................................... 174
9 Alternate Function Input/Output Control Unit (AFIO)...................................... 175
Introduction ........................................................................................................................ 175
Features............................................................................................................................. 176
Functional Descriptions ..................................................................................................... 176
External Interrupt Pin Selection .................................................................................................... 176
Alternate Function......................................................................................................................... 177
Lock Mechanism .......................................................................................................................... 177
Register Map ..................................................................................................................... 177

Rev. 1.30 6 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Register Descriptions......................................................................................................... 178
EXTI Source Selection Register 0 – ESSR0 ................................................................................ 178
EXTI Source Selection Register 1 – ESSR1 ................................................................................ 179
GPIO x Conguration Low Register – GPxCFGLR, x = A, B, C, D............................................... 180
GPIO x Conguration High Register – GPxCFGHR, x = A, B, C, D ............................................. 181
10 Nested Vectored Interrupt Controller (NVIC).................................................. 182
Introduction ........................................................................................................................ 182
Features............................................................................................................................. 183
Function Descriptions ........................................................................................................ 184
SysTick Calibration ....................................................................................................................... 184
Register Map ..................................................................................................................... 184
11 External Interrupt/Event Controller (EXTI)...................................................... 185
Introduction ........................................................................................................................ 185
Features............................................................................................................................. 185
Function Descriptions ........................................................................................................ 186
Wakeup Event Management......................................................................................................... 186
External Interrupt/Event Line Mapping ......................................................................................... 187
Interrupt and Debounce ................................................................................................................ 187
Register Map ..................................................................................................................... 188
Register Descriptions......................................................................................................... 189
EXTI Interrupt Conguration Register n – EXTICFGRn, n = 0 ~ 15 ............................................. 189
EXTI Interrupt Control Register – EXTICR ................................................................................... 190
EXTI Interrupt Edge Flag Register – EXTIEDGEFLGR................................................................ 191
EXTI Interrupt Edge Status Register – EXTIEDGESR ................................................................. 192
EXTI Interrupt Software Set Command Register – EXTISSCR.................................................... 193
EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR ........................................................ 194
EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR ................................................... 195
EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG........................................................... 196
12 Analog to Digital Converter (ADC) .................................................................. 197
Introduction ........................................................................................................................ 197
Features............................................................................................................................. 198
Function Descriptions ........................................................................................................ 199
ADC Clock Setup.......................................................................................................................... 199
Channel Selection......................................................................................................................... 199
Conversion Mode.......................................................................................................................... 199
Start Conversion on External Event.............................................................................................. 202
Sampling Time Setting.................................................................................................................. 203
Data Format.................................................................................................................................. 203
Analog Watchdog.......................................................................................................................... 203
Interrupts....................................................................................................................................... 204
PDMA Request ............................................................................................................................ 204

Rev. 1.30 7 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Register Map ..................................................................................................................... 205
Register Descriptions......................................................................................................... 206
ADC Conversion Control Register – ADCCR ............................................................................... 206
ADC Conversion List Register 0 – ADCLST0............................................................................... 208
ADC Conversion List Register 1 – ADCLST1............................................................................... 209
ADC Input Sampling Time Register – ADCSTR ........................................................................... 210
ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7 ................................................................211
ADC Trigger Control Register – ADCTCR .................................................................................... 212
ADC Trigger Source Register – ADCTSR..................................................................................... 213
ADC Watchdog Control Register – ADCWCR .............................................................................. 214
ADC Watchdog Threshold Register – ADCTR.............................................................................. 215
ADC Interrupt Enable Register – ADCIER.................................................................................... 216
ADC Interrupt Raw Status Register – ADCIRAW ......................................................................... 217
ADC Interrupt Status Register – ADCISR..................................................................................... 218
ADC Interrupt Clear Register – ADCICLR .................................................................................... 219
ADC DMA Request Register – ADCDMAR................................................................................... 220
13 Comparator (CMP) ............................................................................................ 221
Introduction ........................................................................................................................ 221
Features............................................................................................................................. 221
Function Descriptions ........................................................................................................ 222
Comparator Inputs and Output ..................................................................................................... 222
Comparator Voltage Reference .................................................................................................... 222
Interrupts and Wakeup.................................................................................................................. 223
Power Mode and Hysteresis......................................................................................................... 224
Comparator Write-Protected mechanism ..................................................................................... 224
Register Map ..................................................................................................................... 224
Register Descriptions......................................................................................................... 225
Comparator Control Register n – CMPCRn, n = 0 or 1 ................................................................ 225
Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1................................. 227
Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1 ................................................. 228
Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1 .................................................. 229
14 General-Purpose Timer (GPTM) ...................................................................... 230
Introduction ........................................................................................................................ 230
Features............................................................................................................................. 231
Functional Descriptions ..................................................................................................... 232
Counter Mode ............................................................................................................................... 232
Clock Controller ............................................................................................................................ 235
Trigger Controller.......................................................................................................................... 236
Slave Controller ............................................................................................................................ 237
Master Controller .......................................................................................................................... 240
Channel Controller........................................................................................................................ 241
Input Stage ................................................................................................................................... 244

Rev. 1.30 8 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Quadrature Decoder ..................................................................................................................... 246
Output Stage................................................................................................................................. 248
Update Management .................................................................................................................... 252
Single Pulse Mode........................................................................................................................ 253
Asymmetric PWM Mode ............................................................................................................... 255
Timer Interconnection ................................................................................................................... 256
Trigger ADC Start.......................................................................................................................... 259
PDMA Request ............................................................................................................................. 259
Register Map ..................................................................................................................... 260
Register Descriptions......................................................................................................... 261
Timer Counter Conguration Register – CNTCFR ....................................................................... 261
Timer Mode Conguration Register – MDCFR............................................................................. 263
Timer Trigger Conguration Register – TRCFR............................................................................ 266
Timer Counter Register – CTR ..................................................................................................... 267
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 268
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 270
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 272
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 274
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 276
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 278
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 280
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 282
Channel Control Register – CHCTR............................................................................................. 284
Channel Polarity Conguration Register – CHPOLR.................................................................... 285
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 286
Timer Event Generator Register – EVGR..................................................................................... 288
Timer Interrupt Status Register – INTSR...................................................................................... 290
Timer Counter Register – CNTR................................................................................................... 293
Timer Prescaler Register – PSCR ................................................................................................ 294
Timer Counter Reload Register – CRR ........................................................................................ 295
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 296
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 297
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 298
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 299
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 300
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 301
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 302
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 303
15 Basic Function Timer (BFTM).......................................................................... 304
Introduction ........................................................................................................................ 304
Features............................................................................................................................. 304
Functional Description ....................................................................................................... 305
Repetitive Mode............................................................................................................................ 305
One Shot Mode............................................................................................................................. 306

Rev. 1.30 9 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents Table of Contents
Register Map ..................................................................................................................... 307
Register Descriptions......................................................................................................... 307
BFTM Control Register – BFTMCR .............................................................................................. 307
BFTM Status Register – BFTMSR................................................................................................ 308
BFTM Counter Register – BFTMCNTR ........................................................................................ 309
BFTM Compare Value Register – BFTMCMPR ........................................................................... 310
16 Motor Control Timer (MCTM) ........................................................................... 311
Introduction ........................................................................................................................ 311
Features............................................................................................................................. 312
Functional Descriptions ..................................................................................................... 313
Counter Mode ............................................................................................................................... 313
Clock Controller ............................................................................................................................ 317
Trigger Controller.......................................................................................................................... 318
Slave Controller ............................................................................................................................ 319
Master Controller .......................................................................................................................... 321
Channel Controller........................................................................................................................ 322
Input Stage ................................................................................................................................... 325
Output Stage................................................................................................................................. 327
Update Management .................................................................................................................... 337
Single Pulse Mode........................................................................................................................ 339
Asymmetric PWM Mode ............................................................................................................... 341
Timer Interconnection ................................................................................................................... 342
Trigger ADC Start.......................................................................................................................... 346
Lock Level Table ........................................................................................................................... 346
PDMA Request ............................................................................................................................. 347
Register Map ..................................................................................................................... 348
Register Descriptions......................................................................................................... 349
Timer Counter Conguration Register – CNTCFR ....................................................................... 349
Timer Mode Conguration Register – MDCFR............................................................................. 351
Timer Trigger Conguration Register – TRCFR............................................................................ 354
Timer Counter Register – CTR ..................................................................................................... 355
Channel 0 Input Conguration Register – CH0ICFR .................................................................... 356
Channel 1 Input Conguration Register – CH1ICFR .................................................................... 358
Channel 2 Input Conguration Register – CH2ICFR .................................................................... 360
Channel 3 Input Conguration Register – CH3ICFR .................................................................... 362
Channel 0 Output Conguration Register – CH0OCFR ............................................................... 364
Channel 1 Output Conguration Register – CH1OCFR ............................................................... 366
Channel 2 Output Conguration Register – CH2OCFR ............................................................... 368
Channel 3 Output Conguration Register – CH3OCFR ............................................................... 370
Channel Control Register – CHCTR............................................................................................. 372
Channel Polarity Conguration Register – CHPOLR.................................................................... 374
Channel Break Conguration Register – CHBRKCFR ................................................................. 376
Channel Break Control Register – CHBRKCTR ........................................................................... 377

Rev. 1.30 10 of 656 September 28, 2018
32-Bit Arm®Cortex®-M0+ MCU
HT32F52342/HT32F52352
Table of Contents
Timer PDMA/Interrupt Control Register – DICTR......................................................................... 379
Timer Event Generator Register – EVGR..................................................................................... 381
Timer Interrupt Status Register – INTSR...................................................................................... 383
Timer Counter Register – CNTR................................................................................................... 386
Timer Prescaler Register – PSCR ................................................................................................ 387
Timer Counter Reload Register – CRR ........................................................................................ 388
Timer Repetition Register – REPR ............................................................................................... 389
Channel 0 Capture/Compare Register – CH0CCR ...................................................................... 390
Channel 1 Capture/Compare Register – CH1CCR ...................................................................... 391
Channel 2 Capture/Compare Register – CH2CCR ...................................................................... 392
Channel 3 Capture/Compare Register – CH3CCR ...................................................................... 393
Channel 0 Asymmetric Compare Register – CH0ACR................................................................. 394
Channel 1 Asymmetric Compare Register – CH1ACR................................................................. 395
Channel 2 Asymmetric Compare Register – CH2ACR................................................................. 396
Channel 3 Asymmetric Compare Register – CH3ACR................................................................. 397
17 Single-Channel Timer (SCTM) ......................................................................... 398
Introduction ........................................................................................................................ 398
Features............................................................................................................................. 399
Functional Descriptions ..................................................................................................... 399
Counter Mode ............................................................................................................................... 399
Clock Controller ............................................................................................................................ 400
Trigger Controller.......................................................................................................................... 401
Slave Controller ............................................................................................................................ 402
Channel Controller........................................................................................................................ 404
Input Stage ................................................................................................................................... 406
Output Stage................................................................................................................................. 407
Update Management .................................................................................................................... 409
Register Map ..................................................................................................................... 410
Register Descriptions......................................................................................................... 411
Timer Counter Conguration Register – CNTCFR ........................................................................411
Timer Mode Conguration Register – MDCFR............................................................................. 412
Timer Trigger Conguration Register – TRCFR............................................................................ 413
Timer Counter Register – CTR ..................................................................................................... 414
Channel Input Conguration Register – CHICFR ......................................................................... 415
Channel Output Conguration Register – CHOCFR .................................................................... 417
Channel Control Register – CHCTR............................................................................................. 418
Channel Polarity Conguration Register – CHPOLR.................................................................... 419
Timer Interrupt Control Register – DICTR .................................................................................... 420
Timer Event Generator Register – EVGR..................................................................................... 421
Timer Interrupt Status Register – INTSR...................................................................................... 422
Timer Counter Register – CNTR................................................................................................... 423
Timer Prescaler Register – PSCR ................................................................................................ 424
Timer Counter Reload Register – CRR ........................................................................................ 425
Channel Capture/Compare Register – CHCCR ........................................................................... 426