TMP91C829
2006-03-15
91C829-8
3. Operation
This section describes the basic components, functions and operation of the TMP91C829.
Notes and restrictions which apply to the various items described here are outlined in section 7.
“Points to Note and Restrictions” at the end of this databook.
3.1 CPU
The TMP91C829 incorporates a high-performance 16-bit CPU (The 900/L1 CPU). For a
description of this CPU’s operation, please refer to the section of this databook which describes
the TLCS-900/L1 CPU.
The following sub sections describe functions peculiar to the CPU used in the TMP91C829;
these functions are not covered in the section devoted to the TLCS-900/L1 CPU.
3.1.1 Reset
When resetting the TMP91C829 microcontroller, ensure that the power supply voltage is
within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then set the RESET input to low level at least for 10 system clocks (8.89 μs at
36 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the RESET input to low-level at least for 10 system clocks.
Clock gear is intitialized 1/16 mode by reset operation. It means that the system clock
mode fSYS is set to fc/32 (=fc/16 ×1/2).
When the reset is accept, the CPU:
•Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
PC<0:7> ←Data in location FFFF00H
PC<8:15> ←Data in location FFFF01H
PC<16:23> ←Data in location FFFF02H
•Sets the stack pointer (XSP) to 100H.
•Sets bits <IFF0:2> of the status register (SR) to 111. (Thereby setting the interrupt
level mask register to level 7.)
•Sets the <MAX> bit of the status register to 1 (MAX mode).
(Note: As this product does not support MIN mode, do not write a 0 to the <MAX>
bit.)
•Clears bits <RFP0:2> of the status register to 000. (Thereby selecting register
bank 0.)
When the reset is cleared, the CPU starts executing instructions according to the
program counter settings. CPU internal registers not mentioned above do not change
when the reset is cleared.
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
•Initializes the internal I/O registers.
•Sets the port pins, including the pins that also act as internal I/O, to
general-purpose input or output port mode.
Note: The CPU internal register (except to PC, SR, XSP) and internal RAM data do not
change by resetting.
Figure 3.1.1 shows the timing of a reset for the TMP91C829.
