Toshiba TLCS-900/L1 Series User manual

TOSHIBA Original CMOS 16-Bit Microcontroller
TLCS-900/L1 Series
TMP91C829
Semiconductor Company

Preface
Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION**
How to release the HALT mode
Usually, interrupts can release all halts status. However, the interrupts =(NMI,
INT0 to INT4), which can release the HALT mode may not be able to do so if they
are input during the period CPU is shifting to the HALT mode (for about 5 clocks of
fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this
case, an interrupt request is kept on hold internally.)
If another interrupt is generated after it has shifted to HALT mode completely,
halt status can be released without difficultly. The priority of this interrupt is
compare with that of the interrupt kept on hold internally, and the interrupt with
higher priority is handled first followed by the other interrupt.

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CMOS 16-Bit Microcontroller
TMP91C829FG
1. Outline and Features
TMP91C829 is a high-speed 16-bit microcontroller designed for the control of various mid- to
large-scale equipment.With 2 Kbytes of boot ROM included, it allows your programs to be erased
and rewritten on board. TMP91C829FG comes in a 100-pin flat package. Listed below are the
features.
(1) High-speed 16-bit CPU (900/L1 CPU)
•Instruction mnemonics are upward compatible with TLCS-90/900
•16 Mbytes of linear address space
•General-purpose registers and register banks
•16-bit multiplication and division instructions; bit transfer and arithmetic instructions
•Micro DMA: 4 channels (444 ns/2 bytes at 36 MHz)
(2) Minimum instruction execution time: 111 ns (at 36 MHz)
(3) Built-in RAM: 8 Kbytes
Built-in ROM: None
Built-in Boot ROM: 2 Kbytes

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(4) External memory expansion
•Expandable up to 16 Mbytes (Shared program/data area)
•Can simultaneously support 8-/16-bit width external data bus
… Dynamic data bus sizing
(5) 8-bit timers: 6 channels
(6) 16-bit timer/event counter: 1 channel
(7) Serial bus interface: 2 channels
(8) 10-bit AD converter: 8 channels
(9) Watchdog timer
(10) Chip select/wait controller: 4 blocks
(11) Interrupts: 35 interrupts
•9 CPU interrupts: Software interrupt instruction and illegal instruction
•19 internal interrupts: 7 priority levels are selectable
•7 external interrupts: 7 priority levels are selectable
(Level mode, rising edge mode and falling edge mode are selectable.)
(12) Input/output ports: 46 pins (Except Data bus (8bit), Address bus (16bit) and RD pin)
(13) Standby function
Three HALT modes: IDLE2 (Programmable), IDLE1, STOP
(14) Operating voltage
•VCC (5 V) =4.75 V to 5.25 V (fc max =36 MHz)
•VCC (3 V) =3.0 V to 3.6 V (fc max =36 MHz)
(15) Package
•100-pin QFP: P-LQFP100-1414-0.50F
Power on and power off the supply
Power on and power off of the supply require the simultaneous execution of the 5 V power supply and 3.3 V
power supply. If the both power supplies cannot be turned on or off simultaneously, turn on or off each power
supply within the specifications shown in Figure 3.1.2 and 3.1.2 “Power On and Power Off of the Supply”.
When power on and power off of the supply is performed on eigher of them, overlap current may run into the
internal logic. Leaving overlap current running results in increase of power dissipation and short LSI life. Please
avoid leaving either of power supplies on.

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( ): Initial function after reset
Figure 1.1 TMP91C829 Block Diagram
ADTRG (AN3/PA3)
AN0 to AN7 (PA0 to PA7)
VREFH
VREFL
AVCC
AVSS
RD
WR
PZ2 (HWR )
PZ3
TXD0 (P80)
RXD0 (P81)
SCLK0/CTS0 (P82)
0STS (P83)
TXD1 (P84)
RXD1 (P85)
SCK1/ 1CTS (P86)
1STS (P87)
TA0IN/INT1 (P70)
TA1OUT (P71)
TA3OUT/INT2 (P72)
TA4IN/INT3 (P73)
TA5OUT (P74)
INT4 (P75)
LVCC 3V
HVCC 5V
VSS
BOOT
A
M0/AM1
RESET
X1
X2
EMU0
EMU1
(P10 to P17) D8 to D15
(P20 to P27) A16 to A23
D0 to D7
A
0 to A7
A
8 to A15
BUSRQ (P53)
BUSAK (P54)
WAIT (P55)
CS0 (P60)
CS1 (P61)
CS2 (P62)
3CS (P63)
NMI
INT0 (P56)
TB0IN0 (P93)
TB0IN1 (P94)
TB0OUT0 (P95)
TB0OUT1 (P96)
INT5 (P90)
10-bit 8-ch
AD
converter
Port A
8-bit timer
(Timer 0)
Port Z
8-bit timer
(Timer 1)
8-bit timer
(Timer 2)
8-bit timer
(Timer 3)
Serial I/O
(Channel 0)
OSC
Clock gear
Port 1
CS/WAIT
controller
(4 blocks)
Address bus
Interrupt
controller
16-bit timer
(TMRB0)
Data bus
Port 9
8-Kbyte RAM
Watchdog timer
(WDT)
XWA
XBC
XDE
XHL
XIX
XIY
XIZ
XSP
W A
B C
D E
H L
IX
IY
IZ
SP
32 bits
SRPC
F F
CPU
(
TLCS-900L1
)
Port 2
2-Kbyte boot ROM
Port 5
Serial I/O
(Channel 1)
Port 8
8-bit timer
(Timer 4)
8-bit timer
(Timer 5)
Port 7

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2. Pin Assignment and Pin Functions
The assignment of input/output pins for the TMP91C829FG, their names and functions are as
follows:
2.1 Pin Assignment Diagram
Figure 2.1.1 shows the pin assignment of the TMP91C829FG.
Pin
Pin No. Pin name
Pin name No. 63 HVCC (5 V)
P27/A23 64 62 BOOT
P26/A22 65 61 VSS
P25/A21 66 60 P17/D15
P24/A20 67 59 P16/D14
P23/A19 68 58 P15/D13
P22/A18 69 57 P14/D12
P21/A17 70 56 P13/D11
P20/A16 71 55 P12/D10
A15 72 54 P11/D9
A14 73 53 P10/D8
A13 74 52 D7
A12 75 51 D6
A11 76 50 D5
A10 77 49 D4
A9 78 48 D3
A8 79 47 D2
A7 80 46 D1
A6 81 45 D0
A5 82 44 P96/TB0OUT1
A4 83 43 P95/TB0OUT0
A3 84 42 P94/TB0IN1
A2 85 41 P93/TB0IN0
A1 86 40 P90/INT5
A0 87 39 P75/INT4
RD 88 38 P74/TA5OUT
WR 89 37 P73/TA4IN/INT3
LVCC (3 V) 90 36 P72/TA3OUT/INT2
PZ2/HWR 91 35 P71/TA1OUT
VSS 92 34 P70/TA0IN/INT1
PA0/AN0 93 33 RESET
PA1/AN1 94 32 AM1
PA2/AN2 95 31 X1
ADTRG /PA3/AN3 96 30 DVSS
PA4/AN4 97 29 X2
PA5/AN5 98 28 LVCC (oscillator)
PA6/AN6 99 27 AM0
PA7/AN7 100 26 P63/ CS3
VREFH 1 25 P62/CS2
VREFL 2 24 P61/CS1
AVSS 3 23 P60/ CS0
AVCC 4 22 EMU1
NMI 5 21 EMU0
VSS 6 20 P87/STS1
P53/BUSRQ 7 19 P86/SCLK0/ CTS1
HVCC (5 V) 8 18 P85/RXD1
P54/BUSAK 9 17 P84/TXD1
P55/ WAIT 10 16 P83/STS0
P56/INT0 11 15 P82/SCLK0/ CTS0
PZ3 12 14 P81/RXD0
P80/TXD0 13
Figure 2.1.1 Pin Assignment Diagram (100-pin LQFP)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P-LQFP100-1414-0.50F
TMP91C829FG
Top view

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2.2 Pin Names and Functions
The names of the input/output pins and their functions are described below.
Table 2.2.1 Pin Names and Functions (1/3)
Pin Name Number
of Pins I/O Functions
D0 to D7 8 I/O Data (Lower): Bits 0 to 7 of data bus
P10 to P17
D8 to D15
8 I/O
I/O
Port 1: I/O port that allows I/O to be selected at the bit level
(when used to the external 8-bit bus)
Data (Upper): Bits 8 to15 of data bus
P20 to P27
A16 to A23 8 Output Output Port 2: Output port Address: Bits 16 to 23 of address bus
A8 to A15 8 Output Address: Bits 8 to 15 of address bus
A0 to A7 8 Output Address: Bits 0 to 7 of address bus
RD 1 Output Read: Strobe signal for reading external memory
WR 1 Output Write: Strobe signal for writing data to pins D0 to D7
P53
BUSRQ 1 I/O
Input Port 53: I/O port (with pull-up resistor) Bus request: Signal used to request bus release (High impedance)
P54
BUSAK 1 I/O
Output Port 54: I/O port (with pull-up resistor) Bus acknowledge: Signal used to acknowledge bus release
(High impedance)
P55
WAIT 1 I/O
Input Port 55: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait.
P56
INT0 1 I/O Input Port 56: I/O port (with pull-up resistor) Interrupt request pin0: Interrupt request pin with programmable level/rising
edge/falling edge
P60
CS0 1 Output
Output Port 60: Output port Chip select 0: Outputs 0 when address is within specified address area
P61
CS1 1 Output
Output Port 61: Output port Chip select 1: Outputs 0 when address is within specified address area
P62
CS2 1 Output
Output Port 62: Output port Chip select 2: Outputs 0 when address is within specified address area
P63
3CS 1 Output
Output Port 63: Output port Chip select 3: Outputs 0 when address is within specified address area
P70
TA0IN
INT1
1 I/O
Input
Input
Port 70: I/O port
Timer A0 input
Interrupt request pin2: Interrupt request pin with programmable level/rising
edge/falling edge
P71
TA1OUT 1 I/O Output Port 71: I/O port Timer A0 or timer A1 output
P72
TA3OUT
INT2
1 I/O
Output
Input
Port 72: I/O port
Timer A2 or timer A3 output
Interrupt request pin2: Interrupt request pin with programmable level/rising
edge/falling edge

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Table 2.2.2 Pin Names and Functions (2/3)
Pin Name Number
of Pins I/O Functions
P73
TA4IN
INT3
1 I/O
Input
Input
Port 73: I/O port
Timer A4 input
Interrupt request pin 3: Interrupt request pin with programmable level/rising
edge/falling edge
P74
TA5OUT 1 I/O Output Port 74: I/O port Timer A4 or timer A5 output
P75
INT4 1 I/O Input Port 75: I/O port Interrupt request pin 4: Interrupt request pin with programmable
P80
TXD0 1 I/O Output Port 80: I/O port (with pull-up resistor) Serial send data 0: Programmable open-drain output pin
P81
RXD0 1 I/O Input Port 81: I/O port (with pull-up resistor) Serial receive data 0
P82
SCLK0
CTS0
1 I/O
Input
I/O
Port 82: I/O port: (with pull-up resistor)
Serial clock I/O 0
Serial data send enable 0 (Clear to send)
P830STS 1 I/O Port 83: I/O port (with pull-up resistor)
Serial data request signal 0
P84
TXD1 1 I/O Output Port 84: I/O port (with pull-up resistor) Serial send data 0: Programmable open-drain output pin
P85
RXD1 1 I/O Input Port 85: I/O port (with pull-up resistor) Serial receive data 1
P86
SCLK1
CTS1
1 I/O
Input
I/O
Port 86: I/O port: (with pull-up resistor)
Serial clock I/O 1
Serial data send enable 1 (Clear to send)
P871STS 1 I/O Port 87: I/O port (with pull-up resistor)
Serial data request signal 1
P90
INT5 1 I/O Input Port 90: I/O port Interrupt request pin 5: Interrupt request pin with programmable level/rising
edge/falling edge
P93
TB0IN0 1 I/O Input Port 93: I/O port Timer B0 input 0
P94
TB0IN1 1 I/O Input Port 94: I/O port Timer B0 input 1
P95
TB0OUT0 1 I/O Output Port 95: I/O port Timer B0 output 0
P96
TB0OUT1 1 I/O Output Port 96: I/O port Timer B0 output 1
PA0 to PA7
AN0 to AN7
ADTRG
8 Input
Input
Input
Port A0 to A7: Pin used to input port
Analog input 0 to 7: Pins used to input to AD converter
A/D trigger: Signal used to request AD start (PA3)
PZ2
HWR 1 I/O
Output Port Z2: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins D8 to D15
PZ3 1 I/O Port Z3: I/O port (with pull-up resistor)

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Table 2.2.3 Pin Names and Functions (3/3)
Pin Name Number
of Pins I/O Functions
BOOT 1 Input This pin sets boot mode (with pull-up resistor)
NMI 1 Input Non-maskable interrupt request pin: Interrupt request pin with programmable
falling edge level or with both edge levels programmable
AM0 to AM1 2 Input Address mode : External data bus with select pin
When external 16-bit bus is fixed or external 8- or 16-bit buses are mixed,
AM1 =0 , AM0 =1
When external 8-bit bus is fixed,
AM1 =0 , AM0 =0
RESET 1 Input Reset: Initializes TMP91C829 (with pull-up resistor)
VREFH 1 Input Pin for reference voltage input to AD converter (H)
VREFL 1 Input Pin for reference voltage input to AD converter (L)
AVCC 1 I/O Power supply pin for AD converter
AVSS 1 GND supply pin for AD converter
X1/X2 2 Oscillator connection pins
HVCC 2 Power supply pins (5 V)
LVCC 2 Power supply pins (3 V)
DVSS 3 GND pins (0 V)
EMU0 1 Output Open pin
EMU1 1 Output Open pin
Note 1:An external DMA controller cannot access the device’s built-in memory or built-in I/O devices using
the BUSRQ and BUSAK signal.
Note 2:All pins which have a built-in pull-up resistor (Other than the RESET pin and the BOOT pin ) can be
disconnected from the resistor in software.

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3. Operation
This section describes the basic components, functions and operation of the TMP91C829.
Notes and restrictions which apply to the various items described here are outlined in section 7.
“Points to Note and Restrictions” at the end of this databook.
3.1 CPU
The TMP91C829 incorporates a high-performance 16-bit CPU (The 900/L1 CPU). For a
description of this CPU’s operation, please refer to the section of this databook which describes
the TLCS-900/L1 CPU.
The following sub sections describe functions peculiar to the CPU used in the TMP91C829;
these functions are not covered in the section devoted to the TLCS-900/L1 CPU.
3.1.1 Reset
When resetting the TMP91C829 microcontroller, ensure that the power supply voltage is
within the operating voltage range, and that the internal high-frequency oscillator has
stabilized. Then set the RESET input to low level at least for 10 system clocks (8.89 μs at
36 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the
operating voltage range, and that the internal high-frequency oscillator has stabilized.
Then hold the RESET input to low-level at least for 10 system clocks.
Clock gear is intitialized 1/16 mode by reset operation. It means that the system clock
mode fSYS is set to fc/32 (=fc/16 ×1/2).
When the reset is accept, the CPU:
•Sets the program counter (PC) as follows in accordance with the reset vector stored
at address FFFF00H to FFFF02H:
PC<0:7> ←Data in location FFFF00H
PC<8:15> ←Data in location FFFF01H
PC<16:23> ←Data in location FFFF02H
•Sets the stack pointer (XSP) to 100H.
•Sets bits <IFF0:2> of the status register (SR) to 111. (Thereby setting the interrupt
level mask register to level 7.)
•Sets the <MAX> bit of the status register to 1 (MAX mode).
(Note: As this product does not support MIN mode, do not write a 0 to the <MAX>
bit.)
•Clears bits <RFP0:2> of the status register to 000. (Thereby selecting register
bank 0.)
When the reset is cleared, the CPU starts executing instructions according to the
program counter settings. CPU internal registers not mentioned above do not change
when the reset is cleared.
When the reset is accepted, the CPU sets internal I/O, ports and other pins as follows.
•Initializes the internal I/O registers.
•Sets the port pins, including the pins that also act as internal I/O, to
general-purpose input or output port mode.
Note: The CPU internal register (except to PC, SR, XSP) and internal RAM data do not
change by resetting.
Figure 3.1.1 shows the timing of a reset for the TMP91C829.

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Read Write
fFPH
A23 to A0
Data-in
D0 to D15 D0 to D15
sampling
(After reset released, starting 2 waits read cycle)
Pull up (Internal) High-Z
sampling
0FFFF00H
Data-in
Data-in
CS0, CS1,CS3
(PZ2 input mode)
RESET
CS2
RD
W
R
HW
R
Figure 3.1.1 TMP91C829 Reset Timing Example

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3.1.2 Power On and Power Off of the Supply
Figure 3.1.2 Power Supply On/Off Timing
3.2 Outline of Operation Modes
There are multi chip and multi boot modes. Which mode is selected depends on the device’s
pin state after a reset.
•Multi chip mode: The device normally operations in this mode. After a reset, the device starts
executing the external memory program.
•Multi boot mode: This mode is used to rewrite the external flash memory by serial transfer
(UART) orATAPI transfer.
After a reset, internal boot program starts up, executing a on-board rewrite
program.
Table 3.2.1 Operation Mode Setup Table
Mode Setup Input Pin
Operation Mode RESET BOOT
Multi chip mode H
Multi boot mode L
VCC 5
VCC 3.3
Max 1 [s] Min 10 [ms] Min 0 [s] Max 1 [s]
RESET
Oscillator operation time
+
Clock doubler stabilization time

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3.3 Memory Map
Figure 3.3.1 is a memory map of the TMP91C829.
Multi chip mode Multi boot mode
000000H
000100H
Internal I/O
(4 Kbytes)
000000H
000100H
Internal I/O
(4 Kbytes) Direct area (n)
001000H Internal RAM
(8 Kbytes)
001000H Internal RAM
(8 Kbytes)
003000H
External memory
003000H
01F800H
16-Mbyte area
01FFFFH
Internal boot ROM
(2 Kbytes) (r32)
(−r32)
External memory
External memory
(r32+)
(r32 +d8/16)
(r32 +r8/16)
(nnn)
FFF800H FFFEFFH Internal boot ROM
(2 Kbytes)
FFFF00H
FFFFFFH Vector table
(256 bytes) FFFF00H
FFFFFFH Vector table
(256 bytes)
( = Internal area)
Figure 3.3.1 TMP91C829 Memory Map

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3.4 Triple Clock Function and Standby Function
The TMP91C829 contains (1) a clock gearing system, (2) a standby controller, and (3) a
noise-reducing circuit. It is used for low-power, low-noise systems.
The clock operating mode is as follows: (a) Single clock mode (X1, X2 pins only).
Figure 3.4.1 shows a transition figure.
Reset
(fOSCH/32)
Release reset
Instruction
Interrupt STOP mode
(Stops all circuits)
NORMAL mode
(fOSCH/gear value/2)
IDLE2 mode
(I/O operate)
IDLE1 mode
(Operate only oscillator) Clock mode transition figure
Instruction
Instruction
Interrupt
Interrupt
Figure 3.4.1 System Clock Block Diagram
The clock frequency input from the X1 and X2 pins is called fc. In case of TMP91C829, fc =
fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is
regarded as one state.

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3.4.1 Block Diagram of System Clock
fOSCH
fc/8
fFPH
Clock gear
TMRA01 to TMRA45
SYSCR0
<PRCK1:0>
Warm-up timer (High-frequency oscillator)
SYSCR0<WUEF>
SYSCR2<WUPTM1:0>
X1
X2 ÷2÷16
÷4
fc/16
fc/4
fc/2
fc
SYSCR1<GEAR2,0>
÷2 ÷4
fc/16
fFPH
fSYS
÷2
fSYS CPU
ROM
RAM
Interrupt
controller
WDT
I/O ports
Prescaler
φT0
TMRB0
SIO0, SIO1
φT0
φT
High-frequency
oscillator ÷8
Prescaler
Prescaler
Figure 3.4.2 Block Diagram of System Clock

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3.4.2 SFRs
7 6 5 4 3 2 1 0
Bit symbol − − −−−WUEF PRCK1 PRCK0SYSCR0
(00E0H) Read/Write R/W
After reset 1 0 1 0 0 0 0 0
Function Always
write “1”. Always write “0”.
Always
write “1”. Always write “0”.
Always
write “0”.
Warm-up
timer
Write 0:
Don’t care
Write 1:
Start timer
Read 0:
End
warm-up
Read 1:
Do not end
warm-up
Select prescaler clock
00: fFPH
01: Reserved
10: fc/16
11: Reserved
7 6 5 4 3 2 1 0
Bit symbol
−GEAR2 GEAR1 GEAR0SYSCR1
(00E1H) Read/Write R/W
After reset 0 0 0 0
Function Always
write “0”. Select gear value of high frequency (fc) 000: fc
001: fc/2
010: fc/4
011: fc/8
100: fc/16
101: (Reserved)
110: (Reserved)
111: (Reserved)
7 6 5 4 3 2 1 0
Bit symbol −WUPTM1 WUPTM0 HALTM1 HALTM0 DRVESYSCR2
(00E2H) Read/Write R/W R/W R/W R/W R/W R/W
After reset 0 1 0 1 1 0
Function Always
write “0”. Warm-up timer 00: Reserved
01: 28 inputted frequency
10: 214 inputted frequency
11: 216 inputted frequency
HALT mode
00: Reserved
01: STOP mode
10: IDLE1 mode
11: IDLE2 mode
1:Drive the
pin during
STOP
mode
Figure 3.4.3 SFR for System Clock

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7 6 5 4 3 2 1 0
Bit symbol PROTECT −−−−EXTIN −− EMCCR0
(00E3H) Read/Write R R/W R/W R/W R/W R/W R/W R/W
After reset 0 0 1 0 0 0 1 1
Function Protect flag
0: OFF
1: ON
Always
write “0”. Always write “1”. Always write “0”.
Always
write “0”. 1: External clock Always write “1”. Always write “1”.
Bit symbol
Read/Write
After reset
EMCCR1
(00E4H)
Function
Writing 1FH turns protections OFF.
Writing any value other than 1FH turns protection ON.
Figure 3.4.4 SFR for Noise Reducing

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3.4.3 System Clock Controller
The system clock controller generates the system clock signal (fSYS) for the CPU core and
internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register
SYSCR1<GEAR0:2> sets the high-frequency clock gear to either 1, 2, 4, 8, or 16 (fc, fc/2, fc/4,
fc/8, or fc/16). These functions can reduce the power consumption of the equipment in which
the device is installed.
The initialization<GEAR0:2> =100 will cause the system clock (fSYS) to be set to fc/32
(fc/16 ×1/2) after a reset.
For example, fSYS is set to 1.125 MHz when the 36 MHz oscillator is connected to the X1
and X2 pins.
Clock gear controller
The fFPH is set according to the contents of the clock gear select register SYSCR1
<GEAR0:2> to either fc, fc/2, fc/4, fc/8, or fc/16. Using the clock gear to select a lower
value of fFPH reduces power consumption.
Example: Changing to a high-frequency gear
SYSCR1 EQU 00E1H
LD (SYSCR1), XXXX0000B ; Changes fSYS to fc/2.
X: Don’t care
(Changing to high-frequency clock gear)
To change the clock gear, write the appropriate value to the SYSCR1<GEAR0:2>
register. The value of fFPH will not change until a period of time equal to the warm-up
time has elapsed from the point at which the register is written to.
There is a possibility that the instruction immediately following the instruction
which changes the clock gear will be executed before the new clock setting comes into
effect. To ensure that this does not happen, insert a dummy instruction (to execute a
write cycle) as follows:
Example:
SYSCR1 EQU 00E1H
LD (SYSCR1), XXXX0001B ; Changes fSYS to fc/4.
LD (DUMMY), 00H ; Dummy instruction.
Instruction to be executed after clock gear has changed.

TMP91C829
2006-03-15
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3.4.4 Prescaler Clock Controller
For the internal I/O (TMRA01:45, TMRB0 and SIO0, SIO1), there is a prescaler which
can divide the clock.
The φT clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16
divided by 2. The setting of the SYSCR0<PRCK0:1> register determines which clock signal
is input.
The φT0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16
divided by 4. The setting of the SYSCR0<PRCK0:1> register determines which clock signal
is input.
3.4.5 Noise Reduction Circuits
Noise reduction circuits are built in, allowing implementation of the following features.
(1) Single drive for high-frequency oscillator
(2) Protection of register contents
The above functions are performed by making the appropriate settings in the EMCCR0
and EMCCR1 registers.
(1) Single drive for high-frequency oscillator
(Purpose)
Not need twin drive and protect mistake operation by inputted noise to X2 pin
when the external oscillator is used.
(Block diagram)
X1 pin
X2 pin
Enable oscillation
fOSCH
(STOP + EMCCR0<EXTIN>)
(Setting method)
When a 1 is written to the EMCCR0<EXTIN>, the oscillator is disabled and is
operated as a buffer. The X2 pin always outputs a 1.
<EXTIN> is initialized to 0 by a reset.
Note: Do not write EMCCR0<EXTIN> =“1” when using external resonator.

TMP91C829
2006-03-15
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(2) Protection of register contents
(Purpose)
An item for mistake operation by inputted noise.
To execute the program certainty which is occurred mistake operation, the
protect-register can be disabled write operation for the specific SFR.
Write disabled SFRs
1. CS/WAIT controller
B0CS, B1CS, B2CS, B3CS, BEXCS,
MSAR0, MSAR1, MSAR2, MSAR3,
MAMR0, MAMR1, MAMR2, MAMR3
2. Clock gear (only EMCCR1 can be written to.)
SYSCR0, SYSCR1, SYSCR2, EMCCR0
(Block diagram)
Protect register
EMCCR0<PROTECT>
To EMCCR1
Write value other than 1FH
Write 1FH S Q
R Write signal to the disabled SFR
Write signal to the other SFR
Write signal SF
R
(Setting method)
Writing any value other than 1FH to the EMCCR1 register turns on protection,
thereby preventing the CPU from writing to the specific SFR.
Writing 1FH to EMCCR1 turns off protection.
The protection status is set in EMCCR0<PROTECT>.
Resetting initializes the protection status to off.