Fujitsu MB90M405 User manual

FUJITSU SEMICONDUCTOR
MICROCONTROLLER
MB90M405
F2MC-16LX FAMILY
16-BIT MICROCONTROLLERS
HARDWARE MANUAL ABSTRACTS
查询MB90M405供应商 捷多邦，专业PCB打样工厂，24小时加急出货

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iii
MB90M405
F2MC-16LX FAMILY
16-BIT MICROCONTROLLERS
HARDWARE MANUAL ABSTRACTS
©1999 FUJITSU LIMITED Printed in Japan
1. Circuit diagrams utilizing Fujitsu products are included as a mean of illustrating typical
semiconductor applications. Complete information sufficient for construction proposes is
not necessarily given.
2. The information contained in this document has been carefully checked and is believed to
be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
3. The information contained in this document does not convey any license under the copy
right, patent right to trademarks claimed and owned by Fujitsu.
4. Fujitsu reserved the right to change products or specifications without notice.
5. No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.
6. The products described in this document are not intended for use in equipment requiring
high reliability, such as marine relays and medical life-support systems. For such
applications, contact your Fujitsu sales representative.
7. If the products and technologies described in this document are controlled by the Foreign
Exchange and Foreign Trade Control Act established in Japan, their export is subject to
prior approval based on the said act.

iv
Preface
n Objective of Manual and Target Audience
The MB90M405 Series is a general-purpose semiconductor device in the F2MC-16LX family. It is a 16-bit
single-chip microcontroller ASIC (Application Specific IC). This manual explains the functionsand
operationsof the MB90M405 Series for engineers who design products using this device.
How to Read This Manual
n Page Organization
A summary is given below the title of each section. A title of the main section is noted in the sub-section to
recognize a current-reading section.
n Index Organization
(1) Register map index
The register map index formatis similar to the I/O map and it allows search for the page explaining the
bits of each register from the address, register abbreviation, register name, and resource macro name.
Use the register map index at searching for the register function when designing aresource macro.
(2) Pin function index
The pin function index is similar to the explanation ofthe pin function and it allows serch for the block
diagram of each resource macro, the explanation ofthe pin function, and notes from the package pin
number, pin name, circuit type, and resource macro name. Use the pin function index when creating
the system board, etc. (The pin function index will be provided in the next revision of this manual).
n Organization of Notes and Checks
Notes :Reference information is given here. Use this as a hint or note when usingthe MB90M405.
This also gives a section(s) to refer.
Check :Precautions when usingthe MB90M405 are given here. Specification restrictions, etc., are
included.

1.1 Features
................................
................................
............
1-3
1.2 Resources.........................................................................1-4
1.3 Product Lineup..................................................................1-5
1.4 Block Diagram...................................................................1-6
1.5 Pin Assignment.................................................................1-7
1.6 Pin Description..................................................................1-8
1.7 I/O Circuit Type...............................................................1-11
1.8 Notes on Handling Devices.............................................1-13
1.9 Clock Supply Map...........................................................1-15
1.10 Low Power Consumption Mode.......................................1-16
1. GENERAL

MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-2

GENERAL
1-3
This chapter explains the features and basic specifications of the Monolith (MB90M405).
The MB90M405 Series is a general-purpose 16-bit microcontroller developed for applications requiring
fluorescent lamp panel control and contains 60 high-voltage withstand output pins required for afluorescent
lamp.
As with the original F2MC-8L and F2MC-16L families, the instruction system inherits the AT architecture, and
has extended high-level language interface instructions and the extended addressing modes, enhanced
multiplication/division instructions (signed), and enhanced bit processing. In addition, a32-bit accumulator
enables handle long word processing.
1.1 Features
•Clock:
•PLL Clock multiplication circuit built-in
•Operating clock (PLL clock) generated by dividing original oscillation by 2 or by multiplying original
oscillation by 1 to 4 (2.1 MHz to 16.8 MHz at original oscillation of 4.2 MHz). Can be selected.
•Minimum instruction execution time is 59.5 ns (when the original oscillation is 4.2 MHz, the PLL clock is
generated by multiplying the original oscillation by 4, and Vcc = 3 V).
•It is possible to generate an external output as a clock output by dividing the original oscillation by 16, 32,
64, or 128.
•Maximum memory space: 16 Mbytes
•24-bit addressing in memory space
•Instruction system suited for controller
•Applicable data types (bit, byte, word, long-word)
•Various addressing modes: 23 types
•High code efficiency
•High-precision operation with 32-bit accumulator
•Signed multiplication and division instructions and enhanced RETI instruction
•Powerful instruction system applicable to high-level language (C) or multitasking
•System stack pointer
•Symmetric instruction set and barrel shift instruction
•Program patch function (2-address pointer)
•Shortened execution time: 4-byte instruction queue
•Powerful interrupt function (eight programmable priority levels)
•Powerful interrupt function for 32 interrupt factors
•Data transfer function (extended intelligent I/O service function: 16 channels maximum)
•Low-power consumption (standby mode)
•Sleep mode (stops CPU operating clock)
•Pseudo-timermode (stops everything except original oscillation and time-base timer)
•Stop mode (stops original oscillation)
•CPU Intermittent operation mode
•Package
•QFP-100 (FPT-100P-M06: 0.65 mm pin pitch)
•Process
•CMOS technology

MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-4
1.2 Resources
•I/O port: 26 pins maximum (All 26 pins can also serve as resource pins).
•18-bit time-base timer: 1 channel
•Watchdog timer: 1 channel
•16-bit reload timer: 3 channels
•16-bit free-run timer: 1 channel
•16-bit output compare: 1 channel
•16-bit input capture: 2 channels
•When the count value of the 16-bit free-run timer matches the setting value of the output compare, the
timer is cleared and an interrupt request is issued.
•Serial I/O: 2 channels
•UART: 2 channels
•Clock-synchronous serial transfer (I/O extended serial) can be used.
•The direction of the shift clock level can be selected arbitrarily (MSB or LSB).
•DTP/external interrupt (4 channels)
•Start extended intelligent I/O services by an external input, and generate an external interrupt.
•Delayed interrupt generation module
•Atask-switching interrupt request is generated.
•8-/10-bit A/D converter (16 channel)
•8- or 10-bit resolution can be selected.
•FL controller
•Enables FL driver control.(The auto display control is performed for 32 digits max. and 59 segments
max.)
1 to 32 digits can be set (can be set on a digit-by-digit basis).
The dimmer can be set.
•Enables LED driver control (Auto display control is performed for 16 segments maximum).
The auto display control can be performed for 16 segments max. at 1/2 duty.
•Timerclock divider
•The original oscillation can be divided by 32, 64, 128, or 256.

GENERAL
1-5
1.3Product Lineup
Table 1-1 lists the Monolith (MB90M405) series product lineup. Functionsother than the ROM/RAM capacity
are shared.
Table 1-1 MB90M405 Series Product Lineup
Product name MB90MV405 MB90MF408 MB90M408 MB90M407
Classification Evaluate Flash Type ROM Mass-produced product (mask ROM)
ROM capacity Not provided 128 Kbytes 96 Kbytes
RAM capacity 4Kbytes 4Kbytes 4Kbytes
CPU Function
Count of basic instructions: 351
Minimum instruction execution time: 59.5 ns (at original oscillation of 4.2 MHz, with
PLL clock generated by multiplying original
oscillation by 4)
Addressing types: 23
Program patch function: 2-address pointer
Maximum memory space: 16 Mbytes
Port I/O port (CMOS) 26 pins (all of 26 pins also serve as resource pins)
FL Controller
60 FL output pins can be used (Under LED control, 43 FL output pins and 17 LED
control pins are required).
Enables FL driver control and LED driver control can be performed.
Under FL driver control, the dimmer can be set for both digits and segments.
Serial I/O (UART) Can also be used as the clock-synchronous method extended I/O serial. Adedicated baud rate generator is built-in.
Four channels are built-in (two channels also serve as UART channels).
16-bit reload timer 16-bit reload timer operation (Toggle output or one-shot output can be selected.)
An event count function can be selected. Three channels are built-in.
16-bit free-run timer 16-bit output compare x 1 channel (for clearing free-run timer)
16-bit input capture x 2 channels
8-/10-bit A/D
converter 8-/10-bit resolution x 16 channels (input multiplex)
Minimum conversion time: 6.2 µs (at internal operation of 16 MHz)
Timerclock divider The external input clock can be divided and output to the outside.
Clock division rates: 16, 32, 64, or 128 (programmable)
External interrupt Four independent channels (also serve for A/D input)
Interrupt factor: L →H edge, H →L edge, L level, or H level
Low power
consumption mode Sleep mode, stop mode, CPU intermittent mode, or pseudo-timermode
Process CMOS
Package PGA256 QFP-100 (0.65 mm pitch)
Operating voltage 3.3 V ±0.3 V(16.8 MHz: 4.2 MHz multiplied by 4)

MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-6
1.4Block Diagram
FIP0/LED0
to
FIP16/LED16
FIP17 to FIP59
FL Controller
Timer clock
divider
V-RAM
8-/10-bit A/D
Converter
Serial I/O
(ch 2)
External interrupt
input controller
ROM
(96/128 KB)
RAM
(4 KB)
Clock
controller
CPU
Controller
X0,X1
RSTX
MD2,1,0
16-bit free-run timer
16-bit input capture
(ch 0, 1)
16-bit output
compare
I2C Interface
16-bit reload timer
(ch 0, 1, 2)
FMC-16LX Bus
PA0/AN0/TMCK
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
PB0/AN8
PB1/AN9
PB2/AN10
PB3/AN11/SI2
PB4/AN12/SC2/TIN
PB5/AN13/SO2/TO
PB6/AN14/INT3
PB7/AN15/INT2
P80/IC0/INT0
P81/IC1/INT1
P82/SI0
P83/SC0
P84/SO0
P85/SI1
P86/SI2
P87/SI3
P90/SDA/SO3
P91/SCL/SC3
Port A
Port BPort 8
Port 9
UART
(ch.0,1)
Serial I/O
(ch 3)
Fig. 1.1 Block Diagram (MB90M405)

GENERAL
1-7
1.5Pin Assignment
FPT-100P-M06 Pin Assignment
FIP16/LED16
1
FIP17
2
FIP18
3
FIP19
4
FIP20
5
FIP21
6
FIP22
7
FIP23
8
FIP24
9
FIP25
10
VSS-IO
11
FIP26
12
FIP27
13
FIP28
14
FIP29
15
FIP30
16
FIP31
17
FIP32
18
FIP33
19
FIP34
20
FIP35
21
FIP36
22
VDD-FIP
23
FIP37
24
FIP38
25
FIP39
26
FIP40
27
FIP41
28
FIP42
29
FIP43
30
31
FIP44
32
FIP45
33
FIP46
34
FIP47
35
FIP48
36
FIP49
37
FIP50
38
FIP51
39
FIP52
40
FIP53
41
FIP54
42
VSS-IO
43
FIP55
44
FIP56
45
FIP57
46
FIP58
47
FIP59
48
VKK
49
MD0
50
MD1/VDD-VFT
60
59
58
57
56
55
54
53
52
51
P82/SI0
P81/IC1/INT1
P80/IC0/INT0
MD2
P86/SC1
P85/SI1
P84/SO0
P83/SC0
P90/SDA/SO3
P87/SO1
70
69
68
67
66
65
64
63
62
61
PA0/AN0/TMCK
AVSS
AVCC
P91/SCL/SC3
PA4/AN4
PA3/AN3
PA2/AN2
PA1/AN1
PA6/AN6
PA5/AN5
80
79
78
77
76
75
74
73
72
71
PB2/AN10
PB1/AN9
PB0/AN8
PA7/AN7
PB5/AN13/SO2/TO0
RSTX
PB4/AN12/SC2/TIN0
PB3/AN11/SI2
PB7/AN15/INT3
PB6/AN14/INT2
82
X0
81
VSS-CPU
84
VCC-CPU
83
X1
86
FIP1/LED1
85
FIP0/LED0
88
FIP3/LED3
87
FIP2/LED2
90
FIP5/LED5
89
FIP4/LED4
92
FIP7/LED7
91
FIP6/LED6
94
FIP9/LED9
93
FIP8/LED8
96
FIP11/LED11
95
FIP10/LED10
98
FIP13/LED13
97
FIP12/LED12
100
FIP15/LED15
99
FIP14/LED14

MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-8
1.6 Pin Description
Tables1-2, 1-3and 1-4list the pin name, function, circuit type, and reset-time state/function.
Table 1-2Pin Description
Pin No.
QFP-100M06 Pin Name Circuit
Type State/function at reset Function
82, 83 X0, X1 AOscillation state Oscillation input pins.
77 RSTX BReset input External reset input pin
FIP0 to FIP15 This function is selected when the FL driver is enabled.
85 to 100 LED0 to LED15 This function is selected when the LED driver is enabled.
FIP16 This function is selected when the FL driver is enabled.
1LED16 This function is selected when the LED driver is enabled.
2 to 10
12 to 19 FIP17 to FIP33
C
20 to 22
24 to 41
43 to 47 FIP34 to FIP59 D
VKK Pull-down
output
Dedicated pins for the FL driver output.
P80 General-purpose I/O port
IC0 External trigger input pin for input capture 0
52 INT0 External factor input pin for external interrupt input 0
This pin is only accepted when it is enabled by the EN0 bit.
P81 General-purpose I/O port
IC1 External trigger input pin for input capture 1
53 INT1 External factor input pin for external interrupt input 1
This pin is only accepted when it is enabled by the EN1 bit.
P82 General-purpose I/O port
54 SI0 Serial data input pin for serial I/O channel 0
This pin is always effective when channel 0 isunder input operation.
P83 General-purpose I/O port
55 SC0 Serial clock I/O pin for serial I/O channel 0
This pin is effective when the channel-0 clock output is enabled.
P84 General-purpose I/O port
56 SO0 Serial data output pin for serial I/O channel 0
This pin is effective when the channel-0 serial data output is
enabled.
P85 General-purpose I/O port
57 SI1 Serial data input pin for serial I/O channel 1
This pin is always effective when channel 0 is under input operation.
P86 General-purpose I/O port
58 SC1 Serial clock I/O pin for serial I/O channel 1
This pin is effective when the channel-0 clock output is enabled.
P87 This pin is a general-purpose I/O port.
59 SO1 Serial data output pin for serial I/O channel 1
This pin is effective when the channel-0 serial data output is
enabled.
P90 General-purpose I/O port (However, the N ch is open drain.)
SDA
Data I/O pin for the I2C interface. This function is effective when
operation of the I2C interface is enabled.
Also, set the port output to the Hi-Z state when operating the I2C
interface.
60
SO3
G
Hi-Z
Serial data output pin for serial I/O channel 3
This pin is effective when the channel-3 serial data output is
enabled.

GENERAL
1-9
Table 1-3Pin Description
Pin No.
QFP-100M06 Pin Name Circuit
Type State/function at reset Function
P91 General-purpose I/O port (However, the N ch is open drain.)
SCL
Clock I/O pin for the I2C interface
This function is effective when operation of the I2C interface is
enabled.
Also, set the port output to the Hi-Z state when operating the I2C
interface.
61
SC3
GHi-Z
Serial clock I/O pin for serial I/O channel 3
This pin is effective when the channel-3 clock output is enabled.
PA0 General-purpose I/O port
AN0 Analog input pin 0 for the A/D converter This function is effective when the analog input specification is
enabled (using ADER).
64
TMCK Timerclock output pin This pin is only effective when output is enabled. This pin is null
when analog input is enabled using ADER.
PA1 to PB2 General-purpose I/O port
65 to 74 AN1 to AN10 Analog input pins (1 to 10) for the A/D converter
This function is effective when the analog input specification is
enabled (using ADER).
PB3 General-purpose I/O port
AN11 Analog input pin (11) for the A/D converter
This function is effective when the analog input specification is
enabled (using ADER).
75
SI2 Serial data input pin for serial I/O channel 2
This pin is always effective when channel 2 is under input
operation.
PB4 General-purpose I/O port
AN12 Analog input pin (12) for the A/D converter This function is effective when the analog input specification is
enabled (using ADER).
SC2 Serial clock I/O pin for serial I/O channel 2
This pin is effective when the channel-2 clock output is enabled.
76
TIN0 External clock input pin for reload timer channel 0
This pin is enabled when the external clock input is effective
(ADER takes precedence).
PB5 General-purpose I/O port
AN13 Analog input pin (13) for the A/D converter This function is effective when the analog input specification is
enabled (using ADER).
SO2 Serial data output pin for serial I/O channel 2 This pin is effective when the channel-2 serial data output is
enabled.
78
TO0 External event output pin for reload timer channel 0
This pin is effective when the external event output is enabled
(ADER takes precedence).
PB6 and PB7 General-purpose I/O port
AN14 and AN15 Analog input pins (14, 15) for the A/D converter This function is effective when the analog input specification is
enabled (using ADER).
79, 80
INT2 and INT3
FAnalog input
External factor input pins for external interrupt inputs 2 and 3
These pins are accepted only when they are enabled using the
EN2 bit and the EN3 bit.
62 AVCC Vcc power input pin for the analog macro
63 AVSS HVss power input pin for the analog macro
48 VKK —Power input Power pin on the pull-down side at high-voltage withstand output.

MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-10
Table 1-4Pin Description
Pin No.
QFP-100M06 Pin Name Circuit
Type State/function at reset Function
49 MD0 Input pin for specifying the operating mode Connect this pin to Vcc. Also, always switch this pin to Vss at boot
programming to flash memory.
50 MD1/VDD-VFT Input pin for specifying the operating mode
Connect this pin to Vcc. This pin also serves as the VDD-VFT pin.
51 MD2
BMode pin
Input pin for specifying the operating mode
Connect this pin to Vss. Also, always switch this pin to Vcc at boot
programming to flash memory.
11, 42 VSS-IO Power (0 V: GND) input pins for I/O
23 VDD-FIP Power (3 V: Vcc) input pin for the FIP
81 VSS-CPU Power (0 V: GND) input pin for the controller
84 VCC-CPU
—Power input
Power (3 V: Vcc) input pin for the controller

GENERAL
1-
1.7I/O Circuit Type
Tables1-5 and 1-6 show the circuit type for each pin.
Table 1-5 I/O Circuits
X1
X0
Classification
A
•Oscillator
•Oscillation feedback resistor:
about 1 MΩ
R
B
•Hysteresis input pin
•
Resistor value: about 50 kΩ(TYP)
C
•P-ch open-drain output
- High-voltage withstand port output
IOL = -25 mA
D
•P-ch open-drain output
- High-voltage withstand port output
IOL = -12 mA
Circuit
Remarks
Xout
Pout
R
KK
V
KK
When using the pin as a normal port,
connect adiode clamp, etc.,to
prevent application of VKK voltage to
the pin at output of the L level (see
Handling notes).
Pout
R
KK
V
KK
When using the pin as a normal port,
connect adiode clamp, etc.,to
prevent application of VKK voltage to
the pin at output of the L level (see
Handling notes).
Standby control signal

MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-12
Table 1-6 I/O Circuits
E
•CMOS hysteresis I/O pin
•CMOS-level output
•CMOS Hysteresis input
(The input cutoff function is
provided in the standby mode.)
IOL = 4 mA
F
G
•N-ch open drain output
•CMOS Level hysteresis input
(The input cutoff function is
provided in the standby mode.)
H
•Analog/CMOS hysteresis I/O pin
•CMOS-level output
•CMOS hysteresis input
(The input cutoff function is provided
in the standby mode.)
•Analog input
(Analog input is effective when the
corresponding bit of ADER is 1.)
IOL = 4 mA
Classification
Circuit
Remarks
Standby control
Pout
Hysteresis input
Standby control
Nout
Analog input
R
Hysteresis input
Standby control
Nout
R
IN
Unlike the CMOS I/O pin, there is no
P-ch transistor at this pin.
Consequently, even when an
external voltage is applied to this pin
with the power to the device set to
OFF, no current flowsto the device
power (Vcc-IO/Vcc-CPU).
•Analog power input protector
Hysteresis input
Pout
Nout
R

GENERAL
1-13
1.8Notes on Handling Devices
(1)Be careful not to exceed the maximum rated voltage (Prevention of latch up).
For aCMOS IC, latch-up may occurif a voltage higher than Vcc or a voltage lower thanVss is applied to the
I/O pin other than medium-/high-voltage withstand I/O pins, or when a voltage that exceeds the rated
voltage is applied between Vcc and Vss.
Latch up rapidly increases the power current, and the device may be destroyed by heat.
When using the device,take care not to exceed the maximum rating. Also,take care thatthe analog power
(AVcc) and the analog inputdo not exceed the digital power (Vcc) when turning the AC/DC power on or off.
(2)Design the device so the supply voltage is as stable as possible.
Asudden change in the powervoltage may cause a malfunction even within the operating assurance range
of the VCC power supply voltage. For safety, the VCC ripple (p-p) of the commercial frequency (50/60
MHz) must be 10% or less of the standard VCC value, and the transient fluctuation at instantaneous power
switching must be 0.1 V/ms or less. Also, take countermeasures to power noise, etc.
(3)Notes at power-on
The voltage rise time at power-on must be 50 µs or more (0.2 to 2.7 V).
(4)Setting unused input pins
Leaving unused input pins open may cause a malfunction. Therefore, these pins must be set to the pull-
up or pull-down state.
(5) Handling of power pins for A/D converter
Even when the A/D converter is not used, connect the pins so that the following relationships are
established: AVCC = VCC, AVSS = VSS.
(6)Notes on using external clock
Even when an external clock is used, the oscillation stabilization wait time isrequired at the power-on reset
or the cancellation of the stop mode. In this case, drive the X0 pin only and leave the X1 pin open.
Example of using external clock
X0
X1
MB90M405 Series
OPEN

MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-14
(7)Power pins
When two or more Vcc pins and Vss pins are provided, pins are designed to be at the same electric
potential are internally connected to the device to prevent malfunctionssuch as latch-up.However, always
connect all same electric potential pins to power and ground outside the device to prevent decrease of
extraneous and radiation the malfunction of the strobe signal due to a ground level rise, and follow the
standards on total output current, etc. Also,consider to connecting the pins to Vcc and Vss of this device at
the lowest possible impedance from the current supply source (It is recommended to connect a bypass
capacitor of about 0.1 µF of the device between Vcc and Vss).
(8)Application sequence for power analog inputs for A/D converter
Apply the digital power (Vcc) first, and then apply the power (AVcc) and analog inputs (AN0 to AN15) for the
A/D converter. Disconnect the power and analog inputs for the A/D converter first, and then disconnect the
digital power (Vcc).
Also, do notallow the input voltage to exceed AVcc even when using a pin shared with an analog input as
an input port (Simultaneous application and disconnection of analog power and digital power is allowed).
(9)Output of high-voltage withstand output pin (circuit type C or D)
When the high-voltage withstand output pin (circuit type is C or D) is used as an ordinary output port, the
port outputs the VKK pin voltage pull-down value at the L level output. In this case, the VKK pin level
voltage is applied to the external circuit, so it is recommended to add adiode clamp circuit as shown in the
figure below.
Pout
R
KK
V
KK
Diode clamp circuit

GENERAL
1-15
1.9 Clock Supply Map
The clock supply map for this device (Monolith: MB90M405) is shown below.
HCLK: Oscillation clock
MCLK: Main clock (operating clock: clock generated by dividing oscillation clock by 2)
PCLK: PLL clock
Clock generator
Oscillator Selector
Timerclock divider
Time-base timer
PLL Multiplication circuit
PCLK
Selector
Divide-by-2
circuit
MCLKHCLK
1 2 3 4
Watchdog timer
Resources
FL Controller
16-bit reload timer
10-bit A/D converter
8-bit serial I/O
6-bit free-run timer
16-bit input capture
16-bit output compare
I2C Communications interface
CPU (F2MC-16LX)
ROM/RAM (memory)
X0
X1

MB90M405 F2MC-16LX FAMILY HARDWARE MANUAL
1-16
1.10
This section provides an overview of the low power consumption mode.
The onolith (MB90M405) has the following modes that stop various functions and clocks
Chapter 4.
•Relationships between operating modes and power
Operating mode Main clock PLL Clock CPU Resources Timer clock
PLL Run Operates Operates Operates Operates Operates
Main Run Operates Stops Operates Operates Operates
PLL Sleep Operates Operates Stops Operates*Operates
Main sleep Operates Stops Stops Operates*Operates
Pseudo-time Operates Stops Stops Stops Operates
Stop Stops Stops Stops Stops Stops
In the above table, the power consumption decreases as the operating mode goes down from the top of the
table.
In the PLL Run mode, operation is performed on the PCLK generated by multiplying the original oscillation by
1 to 4. In the Main Run mode,operation is performed on the MCLK generated by dividing the original
oscillation by 2.
*: In the sleep mode, the CPU stops, so resources cannot be accessed from the CPU.