Renesas ISL81806EVAL1Z User manual

User Manual
X0119392 Rev.1.1 Page 1
May 13, 2021 © 2021 Renesas Electronics
The ISL81806EVAL1Z dual-phase evaluation board (shown in Figure 4) features the ISL81806, an 80V high
voltage dual synchronous buck controller, optimized for E-mode GaN FET, with external soft-start, independent
enable functions and UV/OV/OC/OT protection. A programmable switching frequency ranging from 100kHz to
2MHz helps to optimize the inductor size while the strong gate driver delivers up to 20A for the buck output.
Key Features
▪Wide input range: 18V to 80V
▪High light-load efficiency in pulse skipping DEM operation
▪Programmable soft-start
▪Optional DEM/PWM operation
▪Optional CC/HICCUP OCP protection
▪Supports pre-bias output with soft-start
▪PGOOD indicator
▪OVP, OTP, and UVP protection
▪Back-biased from output to improve efficiency
Specifications
The ISL81806EVAL1Z dual-phase evaluation board is designed for high current applications. The current rating of
the ISL81806EVAL1Z is limited by the FETs and inductor selected. The ISL81806EVAL1Z electrical ratings are
shown in Table 1.
Ordering Information
Related Literature
For a full list of related documents, visit our website:
▪ISL81806 device page
Table 1. ISL81806EVAL1Z Electrical Ratings
Parameter Rating
Input Voltage 18V to 80V
Switching Frequency 500kHz
Output Voltage 12V
Output Current 20A
Average Current OCP Setting Point 25A (Constant Current Setting Point)
Pulse by Pulse OCP Setting Point 20.5A (Each phase)
Hiccup OCP Setting point 24.5A (Each phase)
Part Number Description
ISL81806EVAL1Z High Voltage Dual Phase Buck Controller GaN FETs Evaluation Board
ISL81806EVAL1Z
Evaluation Board

X0119392 Rev.1.1 Page 2 May 13, 2021 ISL81806EVAL1Z User Manual
Figure 1. ISL81806EVAL1Z Block Diagram
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X0119392 Rev.1.1 Page 3
May 13, 2021
ISL81806EVAL1Z User Manual
1. Functional Description
The ISL81806EVAL1Z is the same test board used by Renesas application engineers and IC designers to
evaluate the performance of the ISL81806. The board provides an easy and complete evaluation of all the IC and
board functions.
As shown in Figure 3, 18V to 80V VIN is supplied to VIN and GND. The regulated 12V output on VOUT and GND
can supply up to 20A to the load. Because of the high power efficiency, the evaluation board can run at 20A
continuously with airflow 1700LFM at room ambient temperature conditions.
1.1 Recommended Testing Equipment
The following materials are recommended for testing:
▪0V to 80V power supply with at least 20A source current capability
▪Electronic loads capable of sinking current up to 30A
▪Digital Multimeter (DMMs)
▪100MHz quad-trace oscilloscope
1.2 Operating Range
The input voltage range is from 18V to 80V for an output voltage of 12V. If the output voltage is set to a lower
value, the minimum VIN can be reset to a lower value by changing the ratio of R10 and R11. The minimum EN
threshold that VIN can be set to is 4.5V.
The rated load current is 20A with the OCP point set at 20.5A at room ambient temperature conditions. The
operating temperature range of this board is -40°C to +85°C.
Note: Airflow is needed for higher temperature conditions.
1.3 Quick Test Guide
1. Ensure that the circuit is correctly connected to the power supply and electronic loads before applying any
power. See Figure 3 for the proper setup.
2. Turn on the power supply.
3. Adjust the input voltage (VIN) within the specified range and observe the output voltage. The output voltage
variation should be within 3%.
4. Adjust the load current within the specified range and observe the output voltage. The output voltage variation
should be within 3%.
5. Use an oscilloscope to observe output voltage ripple and phase node ringing. For accurate measurement, see
Figure 2 for the proper test setup.
Figure 2. Proper Probe Setup to Measure Output Ripple
Output Capacitor
or Power FET

X0119392 Rev.1.1 Page 4
May 13, 2021
ISL81806EVAL1Z User Manual
Figure 3. Proper Test Setup
A
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X0119392 Rev.1.1 Page 5
May 13, 2021
ISL81806EVAL1Z User Manual
2. Board Design
2.1 PCB Layout Guidelines
Careful attention to the Printed Circuit Board (PCB) layout requirements is necessary for the successful
implementation of an ISL81806 based DC/DC converter. The ISL81806 switches at a high frequency; therefore,
the switching times are short. At these switching frequencies, even the shortest trace has significant impedance
and the peak gate drive current rises significantly in an extremely short time. The transition speed of the current
from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit
elements. These voltage spikes can degrade efficiency, generate EMI, and increase device voltage stress and
ringing. Careful component selection and proper PCB layout minimize the magnitude of these voltage spikes.
Three sets of components are critical when using the ISL81806 DC/DC converter:
▪Controller
▪Switching power components
▪Small-signal components
The switching power components are the most critical to the layout because they switch a large amount of energy,
which tends to generate a large amount of noise. The critical small-signal components are those connected to
sensitive nodes or those supplying critical bias currents. A multilayer PCB is recommended.
Complete the following steps to optimize the PCB layout.
1. Place the input capacitors, GaN FETs, inductor, and output capacitor first. Isolate these power components on
dedicated areas of the board with their ground terminals adjacent to one another. Place the input and output
high frequency decoupling ceramic capacitors very close to the GaN FETs.
2. If signal components and the IC are placed separately from the power train, Renesas recommends using full
ground planes in the internal layers with shared SGND and PGND to simplify the layout design. Otherwise, use
separate ground planes for the power ground and the small signal ground. Connect the SGND and PGND
together close to the IC. Note: DO NOT connect them together anywhere else.
3. Keep the loop formed by the input capacitor, the top FET, and the bottom FET as small as possible.
4. Ensure the current paths from the input capacitor to the FETs, the power inductor, and the output capacitor are
as short as possible with maximum allowable trace widths.
5. Place the PWM controller IC close to the FETs Gates. Especially the high side FET. The FETs gate drive
connections should be short and wide. Place the IC over a quiet ground area. Avoid switching ground loop
currents in this area.
6. Place the VDD bypass capacitor very close to the VDD pin of the IC and connect its ground end to the PGND
pin. Connect the PGND pin to the ground plane by a via.
Note: DO NOT connect the PGND pin directly to the SGND EPAD.
7. Place the gate drive components (BOOT diodes and BOOT capacitors) together near the controller IC.
8. Place the output capacitors as close to the load as possible. Use short, wide copper regions to connect output
capacitors to load to avoid inductance and resistances.
9. Use copper filled polygons or wide, short traces to connect the junction of the upper FET, lower FET, and output
inductor. Keep the PHASE nodes connection to the IC short. Note: DO NOT unnecessarily oversize the copper
islands for the PHASE nodes. Because the phase nodes are subjected to high dv/dt voltages, the stray
capacitor formed between these islands and the surrounding circuitry tends to couple switching noise.
10. Create a separate small analog ground plane near the IC. Connect the SGND pin to this plane. Connect all
small signal grounding paths including feedback resistors, current monitoring resistors and capacitors,
soft-starting capacitors, loop compensation capacitors and resistors, and EN pull-down resistors to this SGND
plane.
11. Use a pair of traces with minimum loop for the input or output current sensing connection.

X0119392 Rev.1.1 Page 6
May 13, 2021
ISL81806EVAL1Z User Manual
12. Ensure the feedback connection to the output capacitor is short and direct.
2.2 ISL81806EVAL1Z Evaluation Board
Figure 4. ISL81806EVAL1Z Evaluation Board, Top View
Figure 5. ISL81806EVAL1Z Evaluation Board, Bottom View

X0119392 Rev.1.1 Page 7 May 13, 2021 ISL81806EVAL1Z User Manual
2.3 ISL81806EVAL1Z Circuit Schematic
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X0119392 Rev.1.1 Page 8
May 13, 2021
ISL81806EVAL1Z User Manual
2.4 Bill of Materials
Qty Reference Designator Description Manufacturer Manufacturer Part
1PWB-PCB,
ISL81806EVAL1Z, REVF,
ROHS
MTL (Multilayer PCB
International)
ISL81806EVAL1ZREVFPCB
1 C65 CAP, SMD, 0603, 0.01µF,
50V, 5%, C0G/NP0, SOFT
TERMINATION, ROHS
TDK C1608C0G1H103J080AE
3 C52, C54, C55 CAP, SMD, 0603, 1000pF,
50V, 10%, X7R, ROHS
TDK C1608X7R1H102K
1 C51 CAP, SMD, 0603, 0.1µF,
100V, 10%, X7S, ROHS
TDK C1608X7S2A104K080AB
14 C16, C17, C18, C19, C20,
C21, C22, C41, C42, C43,
C44, C45, C46, C47
CAP, SMD, 0805, 22µF, 25V,
20%, X5R, LOW ESL,
ROHS
TDK C2012X5R1E226M125AC
24 C11, C12, C13, C36, C37,
C38, C39, C68, C69, C70,
C71, C72, C73, C76, C77,
C79, C81, C82, C83, C84,
C85, C86, C87, C88
CAP, SMD, 0805, 1µF, 100V,
10%, X7S, ROHS
TDK C2012X7S2A105K125AB
1 C66 CAP-AEC-Q200, SMD,
0603, 820pF, 50V, 5%,
C0G/NP0, ROHS
TDK CGA3E2C0G1H821J080AA
4 C24, C25, C49, C50 CAP, SMD, 0402, 0.01µF,
50V, 10%, X7R, ROHS
VENKEL C0402X7R500-103KNE
1 C61 CAP, SMD, 0402, 10µF, 10V,
20%, X5R, ROHS
SAMSUNG CL05A106MP8NUB8
2 C57, C64 CAP, SMD, 0402, 2.2µF,
25V, 10%, X5R, ROHS
TDK C1005X5R1E225K050BC
0 C15, C40 CAP, SMD, 0402, DNP-
PLACE HOLDER, ROHS
1 C62 CAP, SMD, 0603, 10µF, 16V,
10%, X5R, ROHS
MURATA GRM188R61C106KAALD
1 C53 CAP, SMD, 0603, 10µF, 25V,
20%, X5R, ROHS
TDK C1608X5R1E106M080AC
1 C59 CAP, SMD, 0603, 0.027µF,
50V, 10%, X7R, ROHS
VENKEL C0603X7R500-273KNE
1 C74 CAP, SMD, 0603, 47pF, 50V,
5%, C0G, NP0, ROHS
AVX 06035A470JAT2A
1 C58 CAP, SMD, 0603, 560pF,
50V, 5%, C0G, ROHS
VENKEL C0603C0G500-561JNE
1 C60 CAP, SMD, 0603, 0.056µF,
50V, 10%, X7R, ROHS
MURATA GRM188R71H563KA93D
0 C56, C63 CAP, SMD, 0603, DNP-
PLACE HOLDER, ROHS
10 C1, C2, C3, C4, C5, C26,
C27, C28, C29, C30
CAP-AEC-Q200, SMD,
0603, 0.22µF, 100V, 10%,
X7S, ROHS
TAIYO YUDEN HMK107C7224KAHTE

X0119392 Rev.1.1 Page 9
May 13, 2021
ISL81806EVAL1Z User Manual
5 C6, C7, C8, C31, C32 CAP-OSCON, SMD,
10.3mm, 27µF, 100V, 20%,
30mΩ, POLYMER, ROHS
PANASONIC 100SXV27M
1 C23 CAP, SMD, 10.3mm,
1200µF, 16V, 20%, 12mΩ,
ALUM.POLYMER, ROHS
PANASONIC 16SVPK12000M
2 L1, L2 COIL-PWR INDUCTOR,
AEC-Q200, SMD, 10.5x10,
3.3µH, 14.5A, WW, ROHS
TDK SPM10065VT-3R3M-D
4 TP1, TP2, TP3, TP4 CONN-PC PIN, W/FLANGE,
TH, 6.55mmPOST,
2.67mmTAIL, ROHS
KEYSTONE 1377-2
6 TP5, TP6, TP7, TP8, TP9,
TP10
CONN-COMPACT TEST PT,
VERTICAL, WHT, ROHS
KEYSTONE 5007
2 D6, D9 DIODE-ZENER, SMD, 0402,
5.6V, 250mW, 7%, 40Ω,
ROHS
DIODES, INC. BZT52C5V6LP-7
2 D13, D14 DIODE-SCHOTTKY, SMD,
SOD-323, 100V, 200mA,
ROHS
ON SEMICONDUCTOR NSR02100HT1G
3 D4, D7, D8 DIODE-SCHOTTKY, SMD,
2P, TUMD2M, 100V, 700mA,
ROHS
ROHM RB578VAM100TR
1 D2 LED, SMD, 0603, GREEN
CLEAR, 2V, 20mA, 574nm,
35mcd, ROHS
LITEON/VISHAY LTST-C191KGKT
1 U1 IC-80V PWM
CONTROLLER for GaN,
32P, TQFN, 5X5, ROHS
RENESAS ELECTRONICS ISL81806FRTZ
4 Q1, Q2, Q3, Q4 TRANSISTOR-GaNFET,
N-CHNL, 100V, 60A, SMD,
BUMPED-DIE, ROHS
EPC (Efficient Power
Conversion)
EPC2218
1 R10 RES, SMD, 0603, 48.7k,
1/10W, 1%, TF, ROHS
VISHAY/DALE CRCW060348K7FKEAC
1 R11 RES-AEC-Q200, SMD,
0805, 430k, 1/8W, 1%, TF,
ROHS
VISHAY/DALE CRCW0805430KFKEA
4 R2, R3, R7, R8 RES, SMD, 0402, 1Ω,
1/16W, 1%, TF, ROHS
VISHAY/DALE CRCW04021R00FKED
2 R38, R39 RES, SMD, 0402, 2.4Ω,
1/16W, 1%, TF, ROHS
VISHAY/DALE CRCW04022R40FKED
2 R21, R25 RES, SMD, 0402, 5.1Ω,
1/16W, 1%, TF, ROHS
YAGEO AC0402FR-075R1L
2 R40, R41 RES, SMD, 0402, 2k,
1/16W, 1%, TF, ROHS
PANASONIC ERJ-2RKF2001
2 R5, R9 RES, SMD, 0402, 20k,
1/16W, 1%, TF, ROHS
PANASONIC ERJ2RKF2001
2 R34, R35 RES, SMD, 0603, 2Ω,
1/10W, 1%, TF, ROHS
YAGEO 9C06031A2R00FGHFT
Qty Reference Designator Description Manufacturer Manufacturer Part

X0119392 Rev.1.1 Page 10
May 13, 2021
ISL81806EVAL1Z User Manual
1 R13 RES, SMD, 0603, 5.1Ω,
1/10W, 1%, TF, ROHS
YAGEO RC0603FR-075R1L
2 R14, R28 RES, SMD, 0603, 10k,
1/10W, 1%, TF, ROHS
VENKEL CR0603-10W-1002FT
4 R30, R32, R42, R43 RES, SMD, 0603, 100k,
1/10W, 1%, TF, ROHS
VENKEL CR0603-10W-1003FT
1 R12 RES, SMD, 0603, 200Ω,
1/10W, 1%, TF, ROHS
VENKEL CR0603-10W-2000FT
1 R15 RES, SMD, 0603, 20k,
1/10W, 1%, TF, ROHS
VENKEL CR0603-10W-2002FT
1 R19 RES, SMD, 0603, 34.8k,
1/10W, 1%, TF, ROHS
VENKEL CR0603-10W-3482FT
1 R31 RES, SMD, 0603, 36k,
1/10W, 1%, TF, ROHS
PANASONIC ERJ-3EKF3602V
1 R20 RES, SMD, 0603, 4.7k,
1/10W, 1%, TF, ROHS
YAGEO 9C06031A4701FKHFT
1 R16 RES, SMD, 0603, 487k,
1/10W, 1%, TF, ROHS
VENKEL CR0603-10W-4873FT
2 R27, R29 RES, SMD, 0603, 51k,
1/10W, 1%, TF, ROHS
YAGEO RC0603FR-0751KL
1 R22 RES, SMD, 0603, 68k,
1/10W, 1%, TF, ROHS
YAGEO RC0603FR-0768KL
1 R17 RES, SMD, 0603, 8.2k,
1/10W, 1%, TF, ROHS
ROHM MCR03EZPFX8201
0 R36, R37 RES, SMD, 0603, DNP-
PLACE HOLDER, ROHS
1 R4 RES, SMD, 0805, 5.1k,
1/8W, 1%, TF, ROHS
PANASONIC ERJ-6ENF5101V
2 R1, R6 RES-AEC-Q200, SMD,
0805-WIDE, 0.004Ω, 1W,
1%, ROHS
SUSUMU KRL2012E-M-R004-F-T5
1 R23 RES-AEC-Q200, SMD,
0603, 2.7k, 1/4W, 1%, TF,
ROHS
VISHAY/DALE RCS06032K70FKEA
4 Bottom four corners BUMPONS,
0.44inWx0.20inH,
CYLINDRICAL DOME, BLK,
ROHS
3M SJ-5003 (BLACK)
Qty Reference Designator Description Manufacturer Manufacturer Part

X0119392 Rev.1.1 Page 11
May 13, 2021
ISL81806EVAL1Z User Manual
2.5 Board Layout
Figure 7. Silkscreen Top
Figure 8. Top Layer

X0119392 Rev.1.1 Page 12
May 13, 2021
ISL81806EVAL1Z User Manual
Figure 9. Second Layer (Solid Ground)
Figure 10. Third Layer

X0119392 Rev.1.1 Page 13
May 13, 2021
ISL81806EVAL1Z User Manual
Figure 11. Fourth Layer
Figure 12. Fifth Layer

X0119392 Rev.1.1 Page 14
May 13, 2021
ISL81806EVAL1Z User Manual
Figure 13. Bottom Layer
Figure 14. Silkscreen Bottom

X0119392 Rev.1.1 Page 15
May 13, 2021
ISL81806EVAL1Z User Manual
3. Design Example
3.1 Design Requirements
3.2 Frequency Setting
The default switching frequency of the PWM controller is determined by the resistor RT (R22). It adjusts the default
switching frequency from 100kHz to 2MHz. The RT value for fSW = 500kHz is calculated using Equation 1.
where fSW is the switching frequency in MHz. Select a standard value resistor RT = 68kΩ.
3.3 Output Voltage Setting
The output voltage can be set from 0.8V up to a level determined by the feedback voltage divider. A resistive
divider from the output to ground sets the output voltage. Connect the center point of the divider to the FB_OUT
pin. With VOUT = 12V and RFBO1 (R16) = 487k, the RFBO2 (R19) value is calculated using Equation 2.
where RFBO1 (R16) is the top resistor of the feedback divider network and RFBO2 (R19) is the bottom resistor
connected from FB_OUT to ground. Select a standard value resistor RFBO2 = 34.8kΩ.
3.4 UVLO Setting
The ISL81806 has input UVLO protection. When the voltage on the EN/UVLO pin reaches 1.8V, the PWM
modulator is enabled. Accurate UVLO feature can be implemented by feeding the VIN into the EN/UVLO pin using
a voltage divider, RUV1 (R11) and RUV2 (R10). The VIN UVP rising threshold is calculated using Equation 3.
Parameter Rating
Input Voltage 18V to 80V
Switching Frequency 500kHz
Output Voltage 12V
Output Current 20A
Peak Current Limit Set Point 20.5A per phase
Output Mode Dual phase
PWM Mode Forced PWM
OCP Mode Constant current
(EQ. 1)
(EQ. 2)
(EQ. 3)
RT
34.7
fSW
----------- 4.78–


34.7
0.5
----------- 4.78–64.62kΩ===
RFBO2
0.8V RFBO1 ×
VOUT 0.8V–
-------------------------------------- 0.8V 487kΩ×
12V 0.8V–
------------------------------------- 34.78kΩ===
VUVRISE
VUVLO_THR RUV1 RUV2 +()ILEAK –RUV1RUV2
RUV2
----------------------------------------------------------------------------------------------------------------------------------1.8V 430kΩ48.7kΩ+()2.8μA–430kΩ()48.7kΩ()
48.7kΩ
-------------------------------------------------------------------------------------------------------------------------------------16.49V== =

X0119392 Rev.1.1 Page 16
May 13, 2021
ISL81806EVAL1Z User Manual
The VIN UVP falling threshold is calculated using Equation 4.
where VUVLO_THR is the 1.8V UVLO rising threshold and IUVLO_HYST is the 6.8µA UVLO hysteresis current.
3.5 Soft-Start Capacitor
The soft-start time for dual-phase is set by the value of the soft-start capacitor CSS (C59) connected from SS/TRK1
to GND. The soft-start time with CSS = 27nF is calculated using Equation 5.
When the soft-start time set by external CSS or tracking is less than 1.7ms, an internal soft-start circuit of 1.7ms
takes over the soft-start.
3.6 GaN FETs Considerations
The GaN FETs are selected based on rDS(ON), gate supply requirements, and thermal management
considerations. The maximum operation voltage of the GaN FETs in Buck mode is decided by the maximum VIN
voltage.
The power loss of the upper and lower GaN FETs for each phase is calculated using Equation 6 and Equation 7.
The equations assume linear voltage current transitions and do not model power loss due to the reverse recovery
for the body diode of the lower GaN FET.
Ensure that all GaN FETs are within their maximum junction temperature at high ambient temperature by
calculating the temperature rise according to package thermal resistance specifications.
(EQ. 4)
(EQ. 5)
(EQ. 6)
(EQ. 7)
VUVFALL
VUVLO_THR RUV1 RUV2 +()IUVLO_HYST–RUV1RUV2
RUV2
--------------------------------------------------------------------------------------------------------------------------------------------------------
1.8V 430kΩ48.7kΩ+()6.8μA–430kΩ()48.7kΩ()
48.7kΩ
-------------------------------------------------------------------------------------------------------------------------------------14.77V
==
=
tSS 0.8V
CSS
4μA
-----------


0.8V 27nF
4μA
--------------


×5.4ms== =
PUPPERMAX
IOUT
2
()rDS ON() ()VOUT ()
VINMAX
-----------------------------------------------------------------------IOUT
()VINMAX ()tSW ()fSW ()
2
------------------------------------------------------------------------------+
10A2
()3.2mΩ()12V()
80V
-----------------------------------------------------------
10A()80V()
1.5nC
5V 1.1V–
8.1Ω
--------------------------


--------------------------------1.5nC
1.1V
2Ω
------------


------------------+





477kHz()
2
---------------------------------------------------------------------------------------------------------------------------+ 0.048W 1.115W+1.163W
=
===
PLOWERMAX
IOUT
2
()rDS ON() ()VINMAX VOUT –()
VINMAX
---------------------------------------------------------------------------------------------------
10A()
23.2mΩ()80V 12V–()
80V
-----------------------------------------------------------------------------0.272W
=
==

X0119392 Rev.1.1 Page 17
May 13, 2021
ISL81806EVAL1Z User Manual
3.7 Inductor Selection
The inductor value determines the ripple current of the converter. The ripple voltage is a function of the ripple
current and the output capacitor(s) ESR. Assume the ripple current ratio is 80% of the inductor average current at
the maximum input voltage and the full output load condition. The inductor value for each phase is calculated
using Equation 8.
The recommended inductor value is 3.3µH. Then the ripple current and peak current are calculated using
Equation 9, Equation 10, and Equation 11.
The saturation current of the inductor should be larger than OCP point of 20.5A. The heat rating current of the
inductor should be larger than 10.17A.
The maximum DC power dissipation in the inductor is calculated using Equation 12.
3.8 Output Capacitor Selection
The minimum capacitor value required to provide the full, rising step, transient load current during the response
time of the inductor is shown in Equation 13.
where COUTMIN is the minimum output capacitor(s) required, ITRAN is the transient load current step, and ΔVOUT is
the drop in output voltage allowed during the load transient. Choose a capacitor no less than 152.8µF for each
phase. A 1200µF electrolytic capacitor and 154µF MLCC in total are used for each phase on this board.
The output voltage ripple is because of the inductor ripple current and the ESR of the output capacitors as defined
by Equation 14.
(EQ. 8)
(EQ. 9)
(EQ. 10)
(EQ. 11)
(EQ. 12)
(EQ. 13)
(EQ. 14)
LINMIN
VINMAX VOUT –()VOUT ()
fSW
()0.8 IOUTMAX ×()VINMAX ()
------------------------------------------------------------------------------------------80V 12V–()12V()
477kHz()0.8 10A×()80V()
--------------------------------------------------------------------------2.67μH===
ΔILMAX
VINMAX VOUT –()VOUT ()
fSW
()L()VINMAX ()
---------------------------------------------------------------------- 80V 12V–()12V()
477kHz()3.3μH()80V()
-----------------------------------------------------------------6.48A===
ILRMS IOUTMAX ()
2ΔILMAX
()
2
12
-----------------------------+10A()
26.48A()
2
12
------------------------+ 10.17A===
ILPEAKMAX
IOUTOCP
2
--------------------------ΔILMAX
2
---------------------+20A
2
-----------6.48A
2
----------------+ 13.24A===
PLMAX IOUT ()
2DCR()10A() 26mΩ()×0.6W== =
COUTMIN
LI
TRAN
()
2
2V
INMIN VOUT
–()ΔVOUT ()
-----------------------------------------------------------------------------3.3μH10A0A–()
2
×
218V 12V–()12V 1.5
100
----------
×


---------------------------------------------------------------------- 152.8μF===
VRIPPLE ΔILMAX ESR×6.48A 5mΩ× 32.4mV===

X0119392 Rev.1.1 Page 18
May 13, 2021
ISL81806EVAL1Z User Manual
3.9 Input Capacitor Selection
The important parameters for the input capacitors are the voltage rating and the RMS current rating. The capacitor
voltage rating should be at least 1.25 times greater than the maximum input voltage and 1.5 times is a
conservative guideline. The AC RMS input current varies with the load given in Equation 15.
where floor(2xD) equals 0 when D < 0.5 and equals 1 when D ≥0.5.
The maximum RMS current for two phases in total supplied by the input capacitance occurs at D = 0.25 and
D = 0.75, and only D = 0.25 is within the range of this application. Therefore, the maximum AC RMS current is
shown in Equation 16.
Renesas recommends using a mix of input bypass capacitors to control the voltage ripple across the GaN FETs.
Use ceramic capacitors for the high frequency decoupling and bulk capacitors to supply the RMS current. Five
27µF electrolytic capacitors with 0.94A rating current and eight 25.2µF ceramic capacitors are used to share the
2.5A RMS input current on this board.
3.10 First Level Peak Current Limit and Sense Resistor Selection
The inductor peak current is sensed by the sense resistor RS (R1/R6). When the voltage drop on RSreaches the
set point VOCSET-CS typical 82mV, it triggers the pulse-by-pulse peak current limit. With the current limit set point
IOCPP1 =2xI
OUTMAX = 20A for each phase, the value of the sense resistor is calculated using Equation 17.
Select a standard value resistor RS=4mΩ. Then the actual peak current limit is calculated using Equation 18.
The maximum power dissipation in RSis calculated by Equation 19.
Therefore, a sense resistor with 1W power rating is sufficient for this application.
3.11 Second Level Hiccup Peak Current Protection
In the output dead short condition especially at high VIN, the inductor current runs away with the minimum on
PWM duty. The ISL81806 integrates a second level hiccup type of peak current protection. The second level peak
current protection set point IOCPP2 is calculated using Equation 20.
(EQ. 15)
(EQ. 16)
(EQ. 17)
(EQ. 18)
(EQ. 19)
(EQ. 20)
IRMS Dfloor 2 D×()
2
--------------------------------–


1floor2D×()+
2
------------------------------------------ D–


×IOUT
×=
IRMSMAX D1
2
---D–


×IOUTMAX
×0.25 1
2
---0.25–


×10A×2.5A===
RS
VOCSET CS–
IOCPP1
---------------------------------- 82mV
20A
---------------- 4.1mΩ===
IOCPP1
VOCSET CS–
RS
---------------------------------- 82mV
4mΩ
---------------- 20.5A===
PRSMAX IOUT ()
2RS10A() 24mΩ()0.4W== =
IOCPP2
VOCSET-CS-HIC
RS
--------------------------------------------98mV
4mΩ
---------------- 24.5A===

X0119392 Rev.1.1 Page 19
May 13, 2021
ISL81806EVAL1Z User Manual
3.12 Output Average Overcurrent Protection and RIM Selection
The ISL81806 provides either constant current or hiccup type of overcurrent protection for output average current.
The OCP mode is set by a resistor connected between the LG2/OC_MODE pin and ground. With output constant
current/hiccup set point IOUTOCP = 25A for two phases in total, the current monitoring resistor RIM (R15) is
calculated using Equation 21.
where ICSOFFSET is the output current sense op amp internal offset current, typical 20μA. Select a standard value
resistor RIM =20kΩ. (RIM Should be within 17k to 24k to ensure good current sharing.)
3.13 Output Mode Selection
The IMON2 pin voltage is set to be higher than 3V, and the IC is set for one output dual-phase application. The
original IMON2 current monitor function pin is disconnected from the IMON2 pin and internally connected to the
IMON1 pin.
3.14 PWM Mode Selection
The ISL81806 can be set to either forced PWM mode or DE mode. The mode is set by a resistor RPWMMODE (R5)
connected between the LG1/PWM_MODE pin and GND. The boundary resistor value for RPWMMODE is calculated
using Equation 22.
A resistor less than 30kΩsets the converter to forced PWM mode, while a resistor higher than 30kΩsets the
converter to DE mode. Considering the tolerance in all temperature ranges, Renesas recommends using 20kΩto
set Forced PWM mode and 39kΩto set DE mode. With a GaN FET application, there is an approximately 1MΩ
resistance between the drain and the gate. The pre-bias voltage on the VOUT supplies to the gate using this 1MΩ
resistor. The equation must be corrected by this factor. Most importantly, the gate voltage must be kept lower than
the minimum gate threshold voltage of the GaN FET, which is typically 0.8V to avoid GaN FET damage in the
initial stage.
3.15 Overcurrent Protection Mode Selection
The ISL81806 is set to either a constant current or hiccup type of overcurrent protection for output average current
by selecting a different value of the resistor ROCMODE (R9) connected between LG2/OC_MODE and GND. The
boundary resistor value for ROCMODE is calculated using Equation 23.
A resistor less than 30kΩsets the converter to constant current mode, while a resistor higher than 30kΩsets the
converter to Hiccup mode. Considering the tolerance in all temperature ranges, Renesas recommends using
20kΩto set constant current and 39kΩto set the Hiccup mode. With a GaN FET application, there is an
approximately 1MΩresistance between the drain and the gate. The pre-bias voltage on the VOUT supplies to the
gate using this 1MΩresistor. The equation must be corrected by this factor. Most importantly, the gate voltage
must be kept lower than the minimum gate threshold voltage of the GaN FET, which is typically 0.8V to avoid GaN
FET damage in the initial stage.
(EQ. 21)
(EQ. 22)
(EQ. 23)
RIM
1.2
IOUTOCP RSGmCS
×× 2I
CSOFFSET
×+
----------------------------------------------------------------------------------------------------------------- 1.2V
25Ax4mΩx200μS220×μA+
----------------------------------------------------------------------------------20kΩ===
RPWMMODE
0.3V
10μA
---------------30kΩ==
ROCMODE
0.3V
10μA
---------------30kΩ==

X0119392 Rev.1.1 Page 20
May 13, 2021
ISL81806EVAL1Z User Manual
3.16 Phase Lock Loop (PLL)
The PLL of the ISL81806 ensures the wide range of accurate clock frequency and phase setting. It also makes the
internal clock easily synchronized to an external clock with the frequency either lower or higher than the internal
setting. The external compensation network of RPLL (R23), CPLL1 (C65), and CPLL2 (C66) are needed to connect to
the PLL_COMP pin to ensure PLL stable operation. Renesas recommends choosing 2.7kΩfor RPLL, 10nF for
CPLL1, and 820pF for CPLL2.
3.17 Feedback Loop Compensation
Due to the current loop feedback, the modulator has a single pole response with -20dB slope at a frequency
determined by the load using Equation 24.
where ROis load resistance and COis total load capacitance for each phase. For this type of modulator, a Type 2
compensation circuit is usually sufficient.
Figure 15 shows a Type 2 amplifier and its response, along with the responses of the current mode modulator and
the converter. The Type 2 amplifier, in addition to the pole at origin, has a zero-pole pair that causes a flat gain
region at frequencies between the zero and the pole. The RCOMP, CCOMP1, and CCOMP2 network connected on
the Gm regulator output COMP pin is needed to compensate the loop for stable operation. The loop stability can
be affected by many different factors such as VIN, VOUT, load current, switching frequency, inductor value, output
capacitance, and the compensation network on the COMP pin.
High amplifier zero frequency gain and modulator gain are chosen to satisfy most typical applications. The
crossover frequency appears at the point where the modulator attenuation equals the amplifier high-frequency
gain. The crossover frequency FCis usually about 1/10 to 1/30 of switching frequency. To fulfill the various
applications, large value capacitors are used on the output side. Therefore, a reasonable target crossover
frequency FCin this application is 4kHz.
The compensation zero FZ is usually placed between FPO and FC. Setting FZto 0.5kHz, with
CCOMP1 (C60) = 56nF, the RCOMP (R20) is calculated using Equation 25.
(EQ. 24)
Figure 15. Feedback Loop Compensation
(EQ. 25)
FPO
1
2πROCO
⋅⋅
---------------------------------1
2π12V
10A
-----------1354μF⋅⋅
------------------------------------------------ 98Hz== =
Compensation
Converter
F
Z
F
P
F
P0
Vo
COMP
Vref
(0.8V)
Gm C
COMP1
R
FBO1
Type 2 Compensation
F
C
R
FBO2
Modulator
C3
C
COMP2
R
COMP
RCOMP
1
2πFZCCOMP1
⋅⋅
------------------------------------------------1
2π1.6kHz 56nF⋅⋅
-------------------------------------------------- 4.74kΩ== =