Renesas 8V97003 User manual

8V97003 EVB Manual
© 2020 Renesas Electronics Corporation
1
January 10, 2020
Description
The 8V97003 evaluation board is designed to enable customers to
evaluate the functionality and performance of the 8V97003
RF/Microwave Wideband Synthesizer. The 8V97003 device on the
evaluation board can be programmed and configured via a PC-
based GUI, called Timing Commander, to generate output
frequency from 187.5MHz to 18GHz with very low phase noise and
RMS phase jitter.
This document discusses the setup of the EVB, and the
programming of the 8V97003 using Timing Commander.
Kit Contents
8V97003 Evaluation Board
Micro USB Cable
Required Software
IDT Timing Commander Software Installer (available at
www.idt.com/timingcommander)
Network access during installation if the .NET framework
is not currently installed on the system
8V97003 GUI (available at www.idt.com/8V97003)
USB 2.0 or USB 3.0 interface
8V97003 Evaluation Board

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Important Notes
Disclaimer
Integrated Device Technology, Inc. and its affiliated companies (herein referred to as “IDT”) shall not be liable for any damages arising out
of defects resulting from
(i) delivered hardware or software
(ii) non-observance of instructions contained in this manual and in any other documentation provided to user, or
(iii) Misuse, abuse, use under abnormal conditions, or alteration by anyone other than IDT.
TO THE EXTENT PERMITTED BY LAW, IDT HEREBY EXPRESSLY DISCLAIMS AND USER EXPRESSLY WAIVES ANY AND ALL
WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF
MERCHANTABILITY AND OF FITNESS FOR A PARTICULAR PURPOSE, STATUTORY WARRANTY OF NON-INFRINGEMENT, AND
ANY OTHER WARRANTY THAT MAY ARISE BY REASON OF USAGE OF TRADE, CUSTOM, OR COURSE OF DEALING.
Important Equipment Warning:
Ensure the correct connection of all cables. Supplying the board using the wrong
polarity could result in damage to the board and/or the equipment. Check that all jumpers have been removed from the
board before applying power.
!

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Contents
1. Hardware Setup............................................................................................................................................................................................5
1.1 Evaluation Board Overview .................................................................................................................................................................5
1.2 Required Equipment............................................................................................................................................................................6
Power Supply .......................................................................................................................................................................6
Signal Generator ..................................................................................................................................................................6
Phase Noise Analyzer/Spectrum Analyzer...........................................................................................................................6
Balun ....................................................................................................................................................................................6
PC.........................................................................................................................................................................................6
1.3 Hardware Connection..........................................................................................................................................................................7
1.4 Power-up Procedures..........................................................................................................................................................................7
2. Working with Timing CommanderTM for Programming/Configuration...........................................................................................................8
2.1 Opening an Existing Configuration......................................................................................................................................................8
2.2 Making Changes to an Existing Configuration...................................................................................................................................10
2.3 Creating a New Configuration ...........................................................................................................................................................11
3. Performance Evaluation with the 8V97003 EVB ........................................................................................................................................12
3.1 Output Matching ................................................................................................................................................................................12
3.2 AC-coupling Capacitor.......................................................................................................................................................................13
3.3 Termination........................................................................................................................................................................................13
3.4 Transmission Line Loss.....................................................................................................................................................................13
4. Schematics.................................................................................................................................................................................................15
5. Bill of Materials (BOM)................................................................................................................................................................................18
6. Board Layout ..............................................................................................................................................................................................20
7. Ordering Information...................................................................................................................................................................................20
Appendix A – New Configuration Examples........................................................................................................................................................21
Example 1 – New Configuration for Integer Mode of Operation.................................................................................................................21
Example 2 – New Configuration for Fractional Mode of Operation ............................................................................................................24
Appendix B – Input Reference Phase Noise Performance..................................................................................................................................28
Revision History...................................................................................................................................................................................................29

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List of Figures
Figure 1. Evaluation Board Overview .................................................................................................................................................................5
Figure 2. Starting Up Timing Commander GUI...................................................................................................................................................8
Figure 3. Open Settings File Dialog Box.............................................................................................................................................................8
Figure 4. Connect to the 8V97003......................................................................................................................................................................9
Figure 5. Program the 8V97003 .........................................................................................................................................................................9
Figure 6. Input Configuration Settings ..............................................................................................................................................................10
Figure 7. Feedback Divider Settings.................................................................................................................................................................10
Figure 8. “Locked” Settings View in “Bit Sets” Tab...........................................................................................................................................10
Figure 9. New Settings GUI..............................................................................................................................................................................11
Figure 10. 8V97003 Output Power over Frequencies – Resistive vs. Inductive Matching .................................................................................12
Figure 11. Transmission Line Loss – 8V97003 EVB Revision D........................................................................................................................14
Figure 12. Transmission Line Loss – 8V97003 EVB Revision C........................................................................................................................14
Figure 13. Evaluation Board Schematic – Page 1 ..............................................................................................................................................15
Figure 14. Evaluation Board Schematic – Page 2 ..............................................................................................................................................16
Figure 15. Evaluation Board Schematic – Page 3 ..............................................................................................................................................17
Figure 16. Evaluation Board – Top Layer...........................................................................................................................................................20
Figure 17. Evaluation Board – Second Layer .....................................................................................................................................................20
Figure 18. Evaluation Board – Third Layer.........................................................................................................................................................20
Figure 19. Evaluation Board – Bottom Layer......................................................................................................................................................20
Figure 20. Timing Commander GUI for Creating New Integer Mode Configuration ...........................................................................................22
Figure 21. Expected Performance of 8110.08MHz Output from Example 1.......................................................................................................23
Figure 22. Timing Commander GUI for Creating New Fractional Mode Configuration.......................................................................................25
Figure 23. Expected Performance of 8200MHz Output without Bleeder Current from Example 2.....................................................................26
Figure 24. Expected Performance of 8200MHz Output with 1.1mA of Bleeder Current from Example 2...........................................................27
Figure 25. Phase Noise Performance of 245.76MHz Input Reference Clock.....................................................................................................28
List of Tables
Table 1. Evaluation Board Connection Descriptions .........................................................................................................................................7
Table 2. Evaluation Board BOM......................................................................................................................................................................18

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1. Hardware Setup
This section provides an overview of the different components on the evaluation board. In addition, it discusses the necessary bench equipment,
the hardware connection, and the power-up sequence.
1.1 Evaluation Board Overview
The following diagram identifies various components of the board: power supply jacks, input and output SMA connectors, USB interface port,
and lock indicator LED.
Figure 1. Evaluation Board Overview
Detailed descriptions of these components are as follows (clock-wise from upper left):
Power supply (Banana) jacks: +5V DC at J10, GND at J11
PCB layout revision: For RF Transmission Line Loss information
Reference clock input SMA connectors: Use J6 and J8 for differential reference clock input; use J6 for single-ended reference clock input
•Maximum Vpp = 3.3V
•f_max = 1000MHz when input reference doubler is disabled
•f_max = 250MHz when input reference doubler is enabled
Lock detect LED: LED indicator of PLL Lock status
RF_OUTB/nRF_OUTB output SMA connectors: differential RF/Microwave outputs at J3, J4
RF_OUTA/nRF_OUTA output SMA connectors: differential RF/Microwave outputs at J1, J2
SYNC input: J16

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Reset push button: SW1
Micro USB: J12
1.2 Required Equipment
Several pieces of bench equipment are required for the evaluation of the 8V97003. This section describes the functions of the required
equipment.
Power Supply
The evaluation board uses a single +5V DC supply for its power supply. When running the board, set the bench power supply at 5V/1A. The
+5V terminal is connected to J10, and the Ground terminal is connected to J11. Multiple LDOs on board are used to generate 3.3V to the
8V97003.
Signal Generator
A signal generator is necessary to generate the reference clock to the 8V97003. A single-ended reference clock is connected to J6, while J8
can be left unconnected. When a differential reference clock is available, connect them to J6 and J8.
Oscillators such as Oven Controlled Oscillators (OCXO) from Wenzel Associates, Inc. can also be used to generate a reference clock to the
8V97003. Some examples of these Wenzel Oscillators are the VHF ULN OCXO (for frequencies from 15MHz to 160MHz) or MXO-FR OCXO
(for frequencies greater than 200MHz). However, a signal generator is recommended for the flexibility to experiment with different reference
clock frequencies.
Phase Noise Analyzer/Spectrum Analyzer
A phase noise analyzer is necessary to evaluate phase noise performance of the 8V97003. A spectrum analyzer is required to evaluate
harmonic performance. Both of these pieces of equipment have (output) power measurement capability.
Balun
Balun is optional. A balun can be used to convert single-ended output of a signal generator to differential output which is used to provide a
reference clock to the 8V97003. Another balun can be used to combine the differential outputs of the 8V97003 to a single-ended signal for
measurement with a phase noise analyzer/spectrum analyzer.
PC
A PC is required to run the IDT Timing Commander GUI.

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1.3 Hardware Connection
Complete the following procedures to set up the evaluation board:
1. Without connecting the bench power supply to the EVB, turn on the bench power supply to make sure the output voltage and current clamp
are set to +5V/1A respectively. Then turn off the bench power supply.
2. Connect the bench power supply to the EVB: +5V to J10, GND to J11
3. Connect the Signal Generator’s output to J6 if single-ended reference input clock configuration is desired. If differential reference input
clock configuration is desired, connect the Signal Generator’s output to a balun’s unbalanced port, then connect the balun’s balanced ports
to J6 and J8.
4. Connect the RF outputs to measurement equipment.
5. Terminate unused outputs.
6. Connect micro-USB cable: micro-B end of the cable is connected to J12, A-plug is connected to PC.
Table 1. Evaluation Board Connection Descriptions
Equipment Type Connection on EVB Description
(DC) Power Supply +5V at J10 / GND at J11 5V/1A power supply
Signal Generator J6 for single-ended) /
balun for differential) Reference clock input to 8V97003
Phase Noise Analyzer J1, J2, J3, J4 Measure phase noise at RF outputs
Spectrum Analyzer J1, J2, J3, J4 Measure output power or harmonic performance at RF outputs
Balun (Macom H-183-4) J6, J8 Differential reference clock input to 8V97003
Balun (Marki BAL 0026) J1, J2, J3, J4 Convert differential outputs to single-ended signal for measurements
Micro-USB J12
1.4 Power-up Procedures
Complete the following steps to power up the evaluation board once the “Hardware Connection” have been completed:
1. Turn the bench power supply on. Initial current consumption of the whole EVB should be around 500mA.
2. Set the reference clock input frequency and amplitude on the Signal Generator – enable Signal Generator output.
3. Program the 8V97003 using IDT’s Timing Commander GUI.

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2. Working with Timing CommanderTM for Programming/Configuration
2.1 Opening an Existing Configuration
When a customer’s user case information is provided to IDT prior to when the EVB is sampled, an optimized configuration is usually provided
to the customer for the evaluation. Complete the following procedure to open a setting file:
1. Power up the evaluation board.
2. Start the Timing Commander software. You will see options of “New Setting File” and “Open Setting File”. Select “Open Setting File”.
Figure 2. Starting Up Timing Commander GUI
3. At the “Open Settings File” dialog box, browse to select the setting file (*.tcs) and the personality file (*.tcp), then click “Open.”
Figure 3. Open Settings File Dialog Box

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4. The GUI window with the 8V97003 block diagram will open to show the existing configuration; all configured values will be displayed. In
order to connect the board with Timing Commander (PC) and to set up the communication interface, click the “Connect” button (chip
symbol) at the upper right corner of the GUI.
The connection will be established if a valid 8V97003 is detected, and a green band appears at the upper right corner of the GUI window.
Figure 4. Connect to the 8V97003
5. Click “Write All” to program the 8V97003.
Figure 5. Program the 8V97003
6. The 8V97003 is now configured. If the lock detection function is properly configured, the Lock Detect LED should lit once PLL locked status
is achieved. The output frequency displayed in the Desired REF_OUTA/B box should also be available for measurements.

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2.2 Making Changes to an Existing Configuration
When changes to an existing configuration are necessary, make sure none of the settings in the affected signal path is locked as to allow the
GUI to make appropriate calculation for optimal settings. A locked setting is indicated by a white lock symbol in a red box ( ). Complete steps
1 to 3 in “Opening an Existing Configuration” before making changes to the existing configuration.
For example, when changing the input reference frequency, make sure the input doubler enable and the input reference divider settings are
unlocked, as shown in Figure 6.
Figure 6. Input Configuration Settings
Another example is when changing the desired output frequency, make sure the Feedback Divider settings are unlocked, as shown in Figure
7.
Figure 7. Feedback Divider Settings
A quick way to view all “Locked” settings in an existing configuration is to select “Locked” option in “Bit Sets” tab, as shown in Figure 8.
Figure 8. “Locked” Settings View in “Bit Sets” Tab

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2.3 Creating a New Configuration
Complete the following procedure to create a new setting file:
1. Power up the evaluation board.
2. Start the Timing Commander software. You will see options of “New Setting File” and “Open Setting File”. Select “New Setting File”.
3. In the “New Settings File” dialog box, select “8V97003” and click OK.
4. The GUI window with the 8V97003 block diagram will open with no setting on any of the blocks.
Figure 9. New Settings GUI
5. Click on each functional block of the block diagram to enter the desired settings/configuration or to check automatically calculated
settings/configuration. An invalid setting/configuration will result in an “Error”. Settings/configurations that are not invalid but not optimum
will result in “Warning”. Errors must be resolved before proceeding.
6. Once all settings have valid values, click the Connect button (chip symbol) at the upper right corner of the GUI to set up the communication
interface.
The connection will be established if a valid 8V97003 is detected, and a green band appears at the upper right corner of the GUI window.
7. Click “Write All” to program the 8V97003.
For examples of creating New Configurations for 8V97003, see Appendix A.

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3. Performance Evaluation with the 8V97003 EVB
Because the 8V97003 supports a very wide range of output frequencies, careful consideration must be given to component selection and
termination to ensure signal integrity, especially at high output frequencies. In addition, because impedance is a function of frequency,
(amplitude) loss of transmission line should also be characterized over frequency to ensure accurate de-embed of trace loss.
This section discusses the following topics when evaluating performance of the 8V97003:
Output matching
AC-coupling (series) capacitor
Proper termination when making measurements on single-ended output
Transmission line loss
3.1 Output Matching
The 8V97003 provides two differential outputs of CML type. The outputs are “open collector outputs” and can be matched in different ways. By
default, a simple resistive matching is used on the 8V97003 EVB. This resistive matching consists of a 50Ω resistor to VDD, with a series AC
coupling capacitor. This matching scheme gives the output amplitude a “broadband” response but is not ideal to achieve maximum output
power transmission, especially for high frequencies.
An inductive matching is recommended for better performance and optimal power transmission. For the inductive matching scheme, the 50Ω
resistors connected to VDD are replaced by inductors. The inductor value is frequency dependent.
Figure 10. 8V97003 Output Power over Frequencies – Resistive vs. Inductive Matching
For impedance matching of 50Ω, the inductor value can be calculated as L = 50 ÷ (2 × π × f) where f is the operating frequency. In the data
shown in Figure 10, a 1nH would provide a 50.24Ω match at f = 8GHz Therefore, for the same output power setting, the measured output
power with the 1nH inductive matching is 2dB higher than that with 50Ω resistive match at 8GHz.
When selecting the inductors for output matching, it is critical to select inductors whose self-resonant frequency is higher than the operating
frequency.

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3.2 AC-coupling Capacitor
AC-coupling capacitors are populated on the 8V97003 EVB to ensure 0V DC on the output signals when they are connected to the input of
(RF) measurement equipment. The part number of the (series) AC-coupling capacitor used on the 8V97003 EVB is 520L103KT16T, which is
specified for operation up to 16GHz. The same consideration regarding self-resonant frequency also applies when selecting this capacitor.
For output frequencies above 16GHz, IDT recommends these AC-coupling capacitors be replaced with 0Ω resistors, and a high-performance
external DC block be used to ensure 0V DC input to (RF) measurement equipment.
3.3 Termination
As mentioned in “Output Matching”, the outputs of the 8V97003 are “open collector outputs.” Therefore, when making single-ended
measurements on one branch of the differential pair, it is critical to properly terminate the unused port to minimize distortion (due to reflection)
of the output signal.
Because the built-in load of most (RF) measurement equipment is 50Ω, when making single-ended measurements on one branch of the
differential pair, terminate the unused port with a 50Ω load. At high frequencies, the mismatch in electrical length at which each branch of the
differential pair is terminated could result in reflection that would distort the output signal. IDT recommends that at high frequencies, each branch
of the differential pair be terminated at the same electrical length. This means when making single-ended measurements on one branch of the
differential pair at high frequency, connect the unused port to a cable of the same length with the cable connecting the port being measured,
and terminate that cable with 50Ω load.
3.4 Transmission Line Loss
To accurately characterize the output power of the 8V97003 RF/Microwave Synthesizer, insertion loss of all components in the measurement
path should be accurately accounted. Besides the insertion loss of the RF cables, and balun (if applicable), loss across frequencies due to
transmission line on the EVB must also be characterized.
To assist customers with the measurement of trace loss on the 8V97003 EVB, a test “coupon” is included in the same PCB manufacturing
panel with the main EVB. This test coupon consists of the exact copy of the transmission lines on the board and the SMA connectors.
The insertion loss of the transmission lines on EVB Revision D is displayed in Figure 11. The measurement was taken on the test coupon using
a network analyzer, with Zsource = Zload = 50Ω. On the actual EVB with the 8V97003 as device-under-test (DUT), the source impedance
(including output buffer, bond wire, package, and external matching components) is probably not a perfect 50Ω. Therefore, the mismatch
between the source impedance and the transmission line could cause reflection that would likely present more loss to the output signal. The
insertion loss measured on the test structure shown above should be used as the minimum loss the output signal will suffer.

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Figure 11. Transmission Line Loss – 8V97003 EVB Revision D
The insertion loss of the transmission lines on EVB Revision C is displayed in Figure 12. The high insertion loss is caused by reflection along
the transmission line which was due to larger-than-expected tolerance of the designed characteristic impedance of 50Ω. This issue causes
performance degradation in output power, harmonic, and phase noise. This trace loss should be considered if you are evaluating the 8V97003
RF/Microwave Synthesizer on IDT’s EVB Revision C.
Figure 12. Transmission Line Loss – 8V97003 EVB Revision C

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4. Schematics
Figure 13. Evaluation Board Schematic – Page 1

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Figure 14. Evaluation Board Schematic – Page 2

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Figure 15. Evaluation Board Schematic – Page 3

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5. Bill of Materials (BOM)
Table 2. Evaluation Board BOM
Item Qty. Designator Reference Value PCB Footprint Manufacturer Part Number
1 35
C2, C3, C4, C6, C7, C8, C9,
C10, C32, C33, C35, C39, C40,
C41, C42,C49, C52, C53, C55,
C59, C61, C65,C66, C67, C68,
C71, C75, C76, C78,C82, C83,
C85, C87, C96, C99
0.1u 0402M Murata
Electronics NA
GRM155R61A10
4KA01D
2 8 C11, C12, C36, C56, C62, C72,
C79, C86 0.01u 0402M Taiyo Yuden EMK105B7103KV
-F
3 11 C15, C16, C17, C18, C22, C23,
C24, C25, C29, C30, C31 22u 0402M
4 1 C19 2.2nF 0402M
5 1 C20 680pF 0402M
6 1 C88 47nF 0402M
7 14
C34, C38, C43, C48, C54, C58,
C60, C64, C69, C70, C77, C81,
C84, C97
10uF 402 Samsung CL05A106MQ5N
UNC
8 5 C37, C47, C57, C63, C80 22uF 0402M
9 4 C50, C51, C73, C74 4.7uF 402
10 2 C89,C90 33PF 603
11 6 FB1, FB2, FB3, FB4, FB5, FB6 BLM18BB221SN1D 0603M
12 6 J1, J2, J3, J4, J6, J8, J16 JACK, SMA,
EDGE MOUNT EDGE-MOUNT SMA Samtec SMA-J-P-X-ST-
EM1
13 2 J10, J11 3V3 BANANA_PCB_H_164 Emerson
Network Power 108-0740-001
14 1 J12 USB PORT CONN RCPT USB2.0
MICRO B SMD R/A
Hirose Electric
Co Ltd ZX62-B-5PA(33)
15 4 J5, J13, J14, J15 Test_Point TP
16 2 LD1, LD2 LED_0603_1206_H_GR
EEN LED_0603_1206_H Panasonic LNJ616C8WRA
17 1 L1 600 ohm 500mA 603 TDK
Corporation MMZ1608Y601B
18 2 L2, L3 18nH,0.4A,360mOhm 402 Murata
Electronics NA LQG15HS18NJ02
19 2 R10, R15 50 0402M Vishay-Dale FC0402E50R0BS
T1
20 7 R7, R19, R26, R50, R51, R52,
R53 1K 0402M Panasonic ERJ-2GEJ102X
21 1 R6 62 0402M

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Item Qty. Designator Reference Value PCB Footprint Manufacturer Part Number
22 4 R8, R9, R12, R13 2.2K 603
23 12 R17, R18, R20, R21, R38, R39,
R24, R25, R27, R28, R36, R37 0 0402M Yageo RC0402JR-
070RL
24 4 R1, R2, R3, R4 50 201
25 1 R16 100 603 Panasonic ERJ-3GEYJ101V
26 2 R22, R29 74K 402
27 2 R23, R30 DNP_50 402 Vishay-Dale FC0402E50R0BS
T1
28 1 R31 680 603 Yageo RC0603FR-
07680FL
29 1 R32 470 603 Yageo RC0603FR-
07470RL
30 2 R34, R35 27 603 Yageo RC0603FR-
0727RL
31 1 R40 1.5K 603 Yageo RC0603FR-
071K5L
32 3 R41, R42, R43 10K 603 Yageo RC0603FR-
0710KL
33 1 SW1 Pushbutton_EVQPAC04
M PB_EVQPAC04M Panasonic EVQ-PAC04M
34
6
TP1, TP2, TP3, TP4, TP5, TP7
VCC_D
TP
35
1
U1
8V97003
QFN48
IDT
8V97003
36
2
U2, U3
HMC1060LP3E
QFN16
HITTITE
HMC1060LP3E
37
1
U4
ft2232_chip
lqfp48_l
FTDI
FT2232D
38 1 X1 6MHz XTAL_5mmx7mm
Abracon
Corporation
ABMM-
6.000MHZ-B2-T
39
6
C1, C5, C13, C14, C91, C92
10000pF
402
AT Ceramics
520L103KT16T
40
1
R5
20
0402M
Panasonic
ERJ-2GEJ200X
41
1
C21
220nF
0402M
42 13
U5, U7, R47, R46, R48, R44,
R49, R45, C26, C27, C28,
R54, R55
DNP

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6. Board Layout
Figure 16. Evaluation Board – Top Layer Figure 17. Evaluation Board – Second Layer
Figure 18. Evaluation Board – Third Layer Figure 19. Evaluation Board – Bottom Layer
7. Ordering Information
Contact Renesas Sales at https://www.idt.com/buy-sample/locations.