Renesas R-IN32M4-CL2 TESSERA User manual

Renesas Electronics
www.renesas.com
R-IN32M4-CL2
User
’s Manual Gigabit Ethernet PHY Edition
R9J03G019GBG
Document number: R18UZ0043EJ0100
Issue date: Mar 4, 2016
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com)
Userʼs Manual

Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the
operation of semiconductor products and application examples. You are fully responsible for the incorporation of these
circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for
any losses incurred by you or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas
Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for
any damages incurred by you resulting from errors in or omissions from the information included herein.
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which the product is not intended by Renesas Electronics.
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General Precautions in the Handling of Products
The following usage notes are applicable to CMOS devices from Renesas. For detailed usage notes on the
products covered by this document, refer to the relevant sections of the document as well as any technical
updates that have been issued for the products.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual.
- The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in
the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, associated shoot-through
current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal
become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
- The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are
undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states of pins are not
guaranteed from the moment when power is supplied until the reset process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not
guaranteed from the moment when power is supplied until the power reaches the level at which resetting has
been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
- The reserved addresses are provided for the possible future expansion of functions. Do not access these
addresses; the correct operation of LSI is not guaranteed if they are accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching
the clock signal during program execution, wait until the target clock signal has stabilized.
- When the clock signal is generated with an external resonator (or from an external oscillator) during a reset,
ensure that the reset line is only released after full stabilization of th
e clock signal. Moreover, when switching to a
clock signal produced with an external resonator (or by an external oscillator) while program execution is in
progress, wait until the target clock signal is stable.
▪ARM, AMBA, ARM Cortex, Thumb and ARM Cortex-M4F are trademarks or registered trademarks of ARM Limited in
EU and other countries.
▪Ethernet is a registered trademark of Fuji Zerox Limited.
▪IEEE is a registered trademark of the Institute of Electrical and Electronics Engineers, Inc.
▪CC-Link and CC-Link IE Field are registered trademarks of CC-Link Partner Association (CLPA).
▪All other product names and service names in this document are trademarks or registered trademarks of their
respective owners.
▪This product uses Vitesse’s PHY.

How to Use This Manual
1. Purpose and Target Readers
This manual is intended for users who wish to understand the functions of industrial Ethernet communications
ASSP (Application Specific Standard Product) “R-IN32M4-CL2” (R9J03G019GBG) and design application
systems using it.
Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and
microcomputers.
When designing an application system that includes this MCU, take all points to note into account.
Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised
items. For details on the revised points, see the actual locations in the manual.
The mark “<R>” in the text indicates the major revisions to this version. You can easily find these revisions by copying
“<R>” and entering it in the search-string box for the PDF file.
Literature Literature may be preliminary versions. Note, however, that the following descriptions do not
indicate "Preliminary". Some documents on cores were created when they were planned or still
under development. So, they may be directed to specific customers. Last four digits of document
number (described as ****) indicate version information of each document. Please download the
latest document from our web site and refer to it.
Documents related to R-IN32M4-CL2
Document Name
Document Number
R-IN32M4-CL2 User’s Manual
R18UZ0033EJ****
R-IN32M4-CL2 User’s Manual: Peripheral Modules
R18UZ0035EJ****
R-IN32M4-CL2 User’s Manual: Gigabit Ethernet PHY Edition (This manual)
R18UZ0043EJ****
R-IN32M4-CL2 User’s Manual: Board Design
R18UZ0046EJ****
R-IN32M4-CL2 Programming Manual: Driver
R18UZ0038EJ****
R-IN32M4-CL2 Programming Manual: OS
R18UZ0040EJ****

2. Numbers and Symbols
Data significance: Higher digits on the left and lower digits on the right
Active low representation:
xxxZ (capital letter Z after pin or signal name)
or xxx_N (capital letter _N after pin or signal name)
or xxnx (pin or signal name contains small letter n)
Note: Footnote for item marked with Note in the text
Caution:
Information requiring particular attention
Remark:
Supplementary information
Numeric representation:
Binary … xxxx , xxxxB or n’bxxxx (n bits)
Decimal … xxxx
Hexadecimal … xxxxH or n’hxxxx (n bits)
Prefix indicating power of 2 (address space, memory capacity):
K (kilo) … 210 = 1024
M (mega) … 220 = 10242
G (giga) … 230 = 10243
Data Type:
Word … 32 bits
Halfword … 16 bits
Byte … 8 bits

Contents-1
Contents
1. Product Overview ..........................................................................................................................................1
1.1 Key Features ....................................................................................................................................................... 1
1.1.1 Superior PHY and Interface Technology................................................................................................... 1
1.1.2 Best in Class Power Consumption............................................................................................................. 1
1.1.3 Key Specifications..................................................................................................................................... 1
1.2 Caution in This Manual<R> ............................................................................................................................... 1
2. Functional Descriptions .................................................................................................................................2
2.1 Twisted Pair Media Interface .............................................................................................................................. 2
2.1.1 Voltage Mode Line Driver......................................................................................................................... 2
2.1.2 Autonegotiation and Parallel Detection..................................................................................................... 3
2.1.3 Automatic Crossover and Polarity Detection............................................................................................. 3
2.1.4 Manual MDI/MDIX Setting ...................................................................................................................... 4
2.1.5 Link Speed Downshift ............................................................................................................................... 4
2.2 ActiPHY Power Management............................................................................................................................. 5
2.2.1 Low Power State........................................................................................................................................ 6
2.2.2 Link Partner Wake-Up State...................................................................................................................... 6
2.2.3 Normal Operating State ............................................................................................................................. 6
2.3 LED Interface ..................................................................................................................................................... 7
2.3.1 LED Modes................................................................................................................................................ 7
2.3.2 LED Port Swapping................................................................................................................................... 8
2.3.3 LED Behavior............................................................................................................................................ 8
2.4 Fast Link Failure Indication ................................................................................................................................ 9
2.5 Testing Features................................................................................................................................................ 10
2.5.1 Ethernet Packet Generator ....................................................................................................................... 10
2.5.2 Far-End Loopback ................................................................................................................................... 11
2.5.3 Near-End Loopback................................................................................................................................. 11
2.5.4 Connector Loopback................................................................................................................................ 12
3. Registers......................................................................................................................................................13
3.1 Register and Bit Conventions............................................................................................................................ 14
3.2 IEEE 802.3 and Main Registers ........................................................................................................................ 15
3.2.1 Mode Control........................................................................................................................................... 16
3.2.2 Mode Status ............................................................................................................................................. 17
3.2.3 Device Identification................................................................................................................................ 17
Userʼs Manual

Contents-2
3.2.4 Autonegotiation Advertisement............................................................................................................... 18
3.2.5 Link Partner Autonegotiation Capability................................................................................................. 18
3.2.6 Autonegotiation Expansion...................................................................................................................... 19
3.2.7 Transmit Autonegotiation Next Page....................................................................................................... 19
3.2.8 Autonegotiation Link Partner Next Page Receive ................................................................................... 20
3.2.9 1000BASE-T Control.............................................................................................................................. 20
3.2.10 1000BASE-T Status................................................................................................................................. 21
3.2.11 1000BASE-T Status Extension 1............................................................................................................. 21
3.2.12 100BASE-TX Status Extension............................................................................................................... 22
3.2.13 1000BASE-T Status Extension 2............................................................................................................. 22
3.2.14 Extended PHY Control 0......................................................................................................................... 23
3.2.15 Error Counter 1........................................................................................................................................ 23
3.2.16 Error Counter 2........................................................................................................................................ 23
3.2.17 Error Counter 3........................................................................................................................................ 24
3.2.18 Extended Control and Status.................................................................................................................... 24
3.2.19 Extended PHY Control 1......................................................................................................................... 25
3.2.20 Extended PHY Control 2......................................................................................................................... 25
3.2.21 Interrupt Mask ......................................................................................................................................... 26
3.2.22 Interrupt Status......................................................................................................................................... 27
3.2.23 Auxiliary Control and Status ................................................................................................................... 28
3.2.24 LED Mode Select .................................................................................................................................... 29
3.2.25 LED Behavior.......................................................................................................................................... 29
3.2.26 Extended Page Access ............................................................................................................................. 30
3.3 Extended Page 1 Registers ................................................................................................................................ 31
3.3.1 Cu Media CRC Good Counter................................................................................................................. 31
3.3.2 Extended Mode Control........................................................................................................................... 32
3.3.3 ActiPHY Control ..................................................................................................................................... 32
3.3.4 Ethernet Packet Generator Control 1....................................................................................................... 34
3.3.5 Ethernet Packet Generator Control 2....................................................................................................... 35
3.4 Extended Page 2 Registers ................................................................................................................................ 36
3.4.1 LED Control ............................................................................................................................................ 36
3.5 General Purpose Registers................................................................................................................................. 37
3.5.1 Reserved General Purpose Address Space............................................................................................... 37
3.5.2 Reserved .................................................................................................................................................. 37
3.5.3 Fast Link Failure Control......................................................................................................................... 37
3.5.4 Enhanced LED Control............................................................................................................................ 37
3.5.5 Global Interrupt Status............................................................................................................................. 38
4. Design Considerations ................................................................................................................................39

Contents-3
FIGURES
Figure 2.1 Media Interface.....................................................................................................................................2
Figure 2.2 ActiPHY State Diagram........................................................................................................................ 5
Figure 2.3 Far-End Loopback Diagram................................................................................................................ 11
Figure 2.4 Near-End Loopback Diagram.............................................................................................................. 11
Figure 2.5 Connector Loopback Diagram ............................................................................................................ 12
Figure 3.1 Register Space Diagram...................................................................................................................... 13

Contents-4
TABLES
Table 2.1 Supported MDI Pair Combinations........................................................................................................... 3
Table 2.2 LED Mode and Function Summary .......................................................................................................... 7
Table 2.2 LED Mode and Function Summary .......................................................................................................... 8
Table 3.1 IEEE 802.3 Registers .............................................................................................................................. 15
Table 3.2 Main Registers ........................................................................................................................................ 15
Table 3.3 Mode Control, Address 0 (0x00)............................................................................................................. 16
Table 3.4 Mode Status, Address 1 (0x01) ............................................................................................................... 17
Table 3.5 PHY Identifier 1, Address 2 (0x02)......................................................................................................... 17
Table 3.6 PHY Identifier 2, Address 3 (0x03)......................................................................................................... 17
Table 3.7 AutonegotiationAdvertisement,Address 4 (0x04).................................................................................. 18
Table 3.8 AutonegotiationLink Partner Ability, Address 5 (0x05)......................................................................... 18
Table 3.9 AutonegotiationExpansion, Address 6 (0x06)........................................................................................ 19
Table 3.10 AutonegotiationNext Page Transmit, Address 7 (0x07)..................................................................... 19
Table 3.11 Autonegotiation LP Next Page Receive, Address 8 (0x08)................................................................. 20
Table 3.12 1000BASE-T Control, Address 9 (0x09)............................................................................................ 20
Table 3.13 1000BASE-T Status, Address 10 (0x0A)............................................................................................ 21
Table 3.14 1000BASE-T Status Extension 1, Address 15 (0x0F)......................................................................... 21
Table 3.15 100BASE-TXStatus Extension, Address 16 (0x10)............................................................................ 22
Table 3.16 1000BASE-T Status Extension 2, Address 17 (0x11)......................................................................... 22
Table 3.16 1000BASE-T Status Extension 2, Address 17 (0x11)......................................................................... 23
Table 3.17 Extended PHY Control 0, Address 18 (0x12)..................................................................................... 23
Table 3.18 Error Counter 1, Address 19 (0x13).................................................................................................... 23
Table 3.19 Error Counter 2, Address 20 (0x14).................................................................................................... 23
Table 3.20 Error Counter 3, Address 21 (0x15).................................................................................................... 24
Table 3.21 Extended Control and Status, Address 22 (0x16)................................................................................ 24
Table 3.22 Extended PHY Control 1, Address 23 (0x17) ..................................................................................... 25
Table 3.23 Extended PHY Control 2, Address 24 (0x18) ..................................................................................... 25
Table 3.24 Interrupt Mask, Address 25 (0x19)...................................................................................................... 26
Table 3.25 Interrupt Status, Address 26 (0x1A).................................................................................................... 27
Table 3.26 Auxiliary Control and Status, Address 28 (0x1C) ............................................................................... 28
Table 3.27 LED Mode Select, Address 29 (0x1D)................................................................................................ 29
Table 3.28 LED Behavior, Address 30 (0x1E)...................................................................................................... 29
Table 3.28 LED Behavior, Address 30 (0x1E)...................................................................................................... 30
Table 3.29 Extended/General PurposeRegister Page Access, Address 31 (0x1F) ............................................... 30
Table 3.30 Extended Registers Page 1 Space........................................................................................................ 31
Table 3.31 Cu Media CRC Good Counter, Address 18E1 (0x12)......................................................................... 31
Table 3.32 Extended Mode Control, Address 19E1 (0x13)................................................................................... 32
Table 3.33 ActiPHY Control, Address 20E1 (0x14)............................................................................................. 32

Contents-5
Table 3.33 ActiPHY Control, Address 20E1 (0x14)............................................................................................. 33
Table 3.34 EPG Control Register 1, Address 29E1 (0x1D) .................................................................................. 34
Table 3.35 EPG Control Register 2, Address 30E1 (0x1E)................................................................................... 35
Table 3.36 Extended Registers Page 2 Space ........................................................................................................ 36
Table 3.37 LED Control, Address 17E2 (0x11).................................................................................................... 36
Table 3.38 Reserved, Address 14G (0x0E)........................................................................................................... 37
Table 3.39 Fast Link Failure Control, Address 19G (0x13).................................................................................... 37
Table 3.40 Enhanced LED Control, Address 25G (0x19)..................................................................................... 37
Table 3.41 Global Interrupt Status, Address 29G (0x1D)..................................................................................... 38

R18UZ0043EJ0100
R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition Mar 4, 2016
R18UZ0043EJ0100 Page 1 of 39
Mar 4, 2016
1. Product Overview
The GbE-PHY is a dual-port Gigabit Ethernet PHY.
The GbE-PHY is designed for space-constrained 10/100/1000BASE-T applications. It features integrated, line-side
termination to conserve board space, lower EMI, and improved system performance.
1.1 Key Features
This section lists the main features and benefits of the GbE-PHY.
1.1.1 Superior PHY and Interface Technology
•Two integrated 10/100/1000BASE-T Ethernet copper transceiver (IEEE 802.3ab)
•HP Auto-MDIX and manual MDI/MDIX support
•Jumbo frame support up to 12 kilobytes
1.1.2 Best in Class Power Consumption
•EcoEthernet™ v2.0 green energy efficiency with ActiPHY™
•Fully optimized power consumption for all link speeds
1.1.3 Key Specifications
•Compliant with IEEE 802.3 (10BASE-T, 100BASE-TX, and 1000BASE-T) Specifications
•Devices support operating temperatures of –40 °C ambient to 125 °C junction
1.2 Caution in This Manual<R>
Registers and bits used in this manual are expressed in accordance with the IEEE Standard. For details, see Section 3.1,
Register and Bit Conventions.

R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions
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Mar 4, 2016
2. Functional Descriptions
This section describes the functional aspects of the GbE-PHY, including available operational features, and testing
functionality.
2.1 Twisted Pair Media Interface
The twisted pair interface is compliant with IEEE 802.3-2008.
2.1.1 Voltage Mode Line Driver
The GbE-PHY uses a voltage mode line driver that allows it to fully integrate the series termination resistors, which are
required to connect the PHY’s media interface to an external 1:1 transformer. Also, the interface does not require the user to
place an external voltage on the center tap of the magnetic. The following illustration shows the connections.
PHY Port_n Transformer
Pn_D0P
0.1µF
Pn_D0N
1A+
2A–
RJ-45
Pn_D1P
Pn_D1N
Pn_D2P
Pn_D2N
Pn_D3P
Pn_D3N
0.1µF
0.1µF
0.1µF
3B+
6B–
4C+
5C–
7D+
8D–
75 Ω
75 Ω
75 Ω
75 Ω
1000 pF,
2 kV
(n=[1:0])
Figure 2.1 Media Interface

R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions
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Mar 4, 2016
2.1.2 Autonegotiation and Parallel Detection
The GbE-PHY supports twisted pair autonegotiation, as defined by IEEE 802.3-2008 Clause 28. The autonegotiation
process evaluates the advertised capabilities of the local PHY and its link partner to determine the best possible operating
mode. In particular, autonegotiation can determine speed, duplex configuration, and master or slave operating modes for
1000BASE-T.
If the link partner does not support autonegotiation, the GbE-PHY automatically uses parallel detection to select the
appropriate link speed.
Autonegotiation is disabled by clearing register 0, bit 12. When autonegotiation is disabled, the state of register bits 0.6,
0.13, and 0.8 determine the device operating speed and duplex mode.
Caution:
While 10BASE
-T and 100BASE-TX do not require autonegotiation, IEEE 802.3-
2008 Clause 40
has defined 1000BASE-T to require autonegotiation.
2.1.3 Automatic Crossover and Polarity Detection
For trouble-free configuration and management of Ethernet links, the GbE-PHY includes a robust automatic crossover
detection feature for all three speeds on the twisted pair interface (10BASE-T, 100BASE-TX, and 1000BASE T). Known
as HP Auto-MDIX, the function is fully compliant with Clause 40 of IEEE 802.3-2008.
Additionally, the device detects and corrects polarity errors on all MDI pairs — a useful capability that exceeds the
requirements of the standard.
Both HP Auto-MDIX detection and polarity correction are enabled in the device by default. Default settings can be
changed using device register bits 18.5:4. Status bits for each of these functions are located in register 28.
Caution:
The GbE
-PHY can be configured to perform HP Auto-MDIX, even when autonegotiation is
disabled and the link is forced into 10/100 speeds. To enable this feature, set register 18.7 to
0. To use the feature, also set register 0.12 to 0.
The HP Auto
-MDIX algorithm successfully detects, corrects, and operates with any of the
MDI
wiring pair combinations listed in the following table, which shows that twisted pair A (of four
twisted pairs A, B, C, and D) is connected to the RJ45 connector 1,2 in normal MDI mode.
Table 2.1 Supported MDI Pair Combinations
RJ45 Connections
1, 2
3, 6
4, 5
7, 8
Mode
A
B
C
D
Normal MDI
B
A
D
C
Normal MDI-X
A
B
D
C
Normal MDI with pair swap on C and D pair
B
A
C
D
Normal MDI-X with pair swap on C and D pair

R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions
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Mar 4, 2016
2.1.4 Manual MDI/MDIX Setting
As an alternative to HP Auto-MDIX detection, the PHY can be forced to be MDI or MDI-X using register 19E1, bits 3:2.
Setting these bits to 10 forces MDI and setting 11 forces MDI-X. Leaving the bits 00 enables the HP Auto-MDIX setting
to be based on register 18, bits 7 and 5.
2.1.5 Link Speed Downshift
For operation in cabling environments that are incompatible with 1000BASE-T, the GbE-PHY provides an automatic
link speed downshift option. When enabled, the device automatically changes its 1000BASE-T autonegotiation
advertisement to the next slower speed after a set number of failed attempts at 1000BASE-T. No reset is required to get
out of this state when a subsequent link partner with 1000BASE-T support is connected. This feature is useful in setting
up in networks using older cable installations that include only pairs A and B, and not pairs C and D.
To configure and monitor link speed downshifting, set register 20E1, bits 4:2. For more information, see Table 3.33
ActiPHY Control, Address 20E1 (0x14).

R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions
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Mar 4, 2016
2.2 ActiPHY Power Management
In addition to the IEEE-specified power-down control bit (device register bit 0.11), the GbE-PHY also includes an
ActiPHY power management mode for each PHY. This mode enables support for power-sensitive applications. It utilizes
a signal-detect function that monitors the media interface for the presence of a link to determine when to automatically
power-down the PHY. The PHY wakes up at a programmable interval and attempts to wake up the link partner PHY by
sending a burst of fast link pulse over copper media.
The ActiPHY power management mode is enabled on a per-port basis during normal operation at any time by setting
register bit 28.6 to 1.
The following operating states are possible when ActiPHY mode is enabled:
•Low power state
•Link partner wake-up state
•Normal operating state (link-up state)
The GbE-PHY switches between the low power state and link partner wake- up state at a programmable rate until
signal energy has been detected on the media interface pins. When signal energy is detected, the PHY enters the normal
operating state. If the PHY is in its normal operating state and the link fails, the PHY returns to the low power state after
the expiration of the link status time-out timer. After reset, the PHY enters the low power state.
When autonegotiation is enabled in the PHY, the ActiPHY state machine operates as described.
When autonegotiation is disabled and the link is forced to use 10BASE-T or 100BASE-TX modes while the PHY is in
its low power state, the PHY continues to transition between the low power and link partner wake-up states until signal
energy is detected on the media pins. At that time, the PHY transitions to the normal operating state and stays in that state
even when the link is dropped. When autonegotiation is disabled while the PHY is in the normal operation state, the PHY
stays in that state when the link is dropped and does not transition back to the low power state.
The following illustration shows the relationship between ActiPHY states and timers.
Low Power State
FLP Burst Signal Energy Detected on
Media
Sleep Timer Expires
Timeout Timer Expires and
Auto-negotiation Enabled
LP Wake-up
State Normal Operation State
Figure 2.2 ActiPHY State Diagram

R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions
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Mar 4, 2016
2.2.1 Low Power State
In the low power state, all major digital blocks are powered down. However, the SMI interface (MDC, MDIO, and
MDINT) functionality is provided.
In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low power state and
transitions to the normal operating state when signal energy is detected on the media. This happens when the PHY is
connected to one of the following:
•Autonegotiation-capable link partner
•Another PHY in enhanced ActiPHY link partner wake-up state
In the absence of signal energy on the media pins, the PHY periodically transitions from low-power state to link partner
wake-up state, based on the programmable sleep timer (register bits 20E1.14:13). The actual sleep time duration is
randomized from –80 ms to 60 ms to avoid two linked PHYs in ActiPHY mode entering a lock-up state during operation.
2.2.2 Link Partner Wake-Up State
In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete fast link pulse
bursts are sent on alternating pairs A and B of the media for a duration based on the wake-up timer, which is set using
register bits 20E1.12:11.
In this state, SMI interface (MDC, MDIO, and MDINT) functionality is provided.
After sending signal energy on the relevant media, the PHY returns to the low power state.
2.2.3 Normal Operating State
In the normal operating state, the PHY establishes a link with a link partner. When the media is unplugged or the link
partner is powered down, the PHY waits for the duration of the programmable link status time-out timer, which is set
using register bit 28.7 and bit 28.2. It then enters the low power state.

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2.3 LED Interface
The polarity of the LED outputs is programmable and can be changed using register 17E2, bits 13:10. The default
polarity is active low.
It provides four LED signals per port, LED0 through LED3. The mode and function of each LED signal can be
configured independently.
Caution:
LED number is listed using the convention, LED<LED#>_<Port#>.
2.3.1 LED Modes
Each LED pin can be configured to display different status information that can be selected by setting the LED mode
in register 29. The default LED state is active low and can be changed by modifying the value in register 17E2, bits 13:10.
The blink/pulse stretch is dependent on the LED behavior setting in register 30.
The following table provides a summary of the LED modes and functions. The modes listed are equivalent to the
setting used in register 29 to configure each LED pin.
Table 2.2 LED Mode and Function Summary (1/2)
Mode
Function Name
LED State and Description
0 Link/Activity 1: No link in any speed on any media interface.
0: Valid link at any speed on any media interface.
Blink or pulse-stretch = Valid link at any speed on any media interface with activity present.
1 Link1000/Activity 1: No link in 1000BASE-T.
0: Valid 1000BASE-T.
Blink or pulse-stretch = Valid 1000BASE-T link with activity present.
2 Link100/Activity 1: No link in 100BASE-TX.
0: Valid 100BASE-TX.
Blink or pulse-stretch = Valid 100BASE-TX link with activity present.
3 Link10/Activity 1: No link in 10BASE-T.
0: Valid 10BASE-T link.
Blink or pulse-stretch = Valid 10BASE-T link with activity present.
4 Link100/1000/Activity 1: No link in 100BASE-TX or 1000BASE-T.
0: Valid 100BASE-TX or 1000BASE-T link. Blink or pulse- stretch = Valid 100BASE-TX or
1000BASE-T link with activity present.
5 Link10/1000/Activity 1: No link in 10BASE-T or 1000BASE-T.
0: Valid 10BASE-T or 1000BASE-T link.
Blink or pulse-stretch = Valid 10BASE-T or 1000BASE-T link with activity present.
6 Link10/100/Activity 1: No link in 10BASE-T or 100BASE-TX.
0: Valid 10BASE-T or 100BASE-TX link.
Blink or pulse-stretch = Valid 10BASE-T or 100BASE-TXlink with activity present.
7 Reserved Reserved.
8 Duplex/Collision 1: Link established in half-duplex mode, or no link established.
0: Link established in full-duplex mode.
Blink or pulse-stretch = Link established in half-duplex mode but collisions are present.
9 Collision 1: No collision detected.
Blink or pulse-stretch = Collision detected.

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Table 2.2 LED Mode and Function Summary (2/2)
Mode
Function Name
LED State and Description
10 Activity 1: No activity present.
Blink or pulse-stretch = Activity present.
11 Reserved Reserved.
12 Autonegotiation Fault 1: No autonegotiation fault present.
0: Autonegotiation fault occurred.
13 Reserved Reserved.
14 Force LED Off 1: De-asserts the LED
Note
.
15 Force LED On 0: Asserts the LED
Note
.
Note:
Setting this mode suppresses LED blinking after reset.
2.3.2 LED Port Swapping
For additional hardware configurations, the GbE-PHY can have its LED port order swapped. This is a useful feature to
help simplify PCB layout design. Register 25G bit 0 controls the LED port swapping mode. LED port swapping only
applies to the general mode LEDs.
2.3.3 LED Behavior
LED behaviors can be programmed into the GbE-PHY. Use the settings in register 30 to program LED behavior, which
includes the following:
LED Combine Enables an LED to display the status for a combination of primary and secondary modes. This can
be enabled or disabled for each LED pin. For example, a copper link running in 1000BASE-T mode and activity present
can be displayed with one LED by configuring an LED pin to Link1000/Activity mode. The LED asserts when linked to
a 1000BASE-T partner and also blinks or performs pulse-stretch when activity is either transmitted by the PHY or
received by the Link Partner. When disabled, the combine feature only provides status of the selected primary function. In
this example, only Link1000 asserts the LED, and the secondary mode, activity, does not display when the combine
feature is disabled.
LED Blink or Pulse-Stretch This behavior is used for activity and collision indication. This can be uniquely
configured for each LED pin. Activity and collision events can occur randomly and intermittently throughout the link-up
period. Blink is a 50% duty cycle oscillation of asserting and de-asserting an LED pin. Pulse-stretch guarantees that an
LED is asserted and de-asserted for a specific period of time when activity is either present or not present. These rates
can also be configured using a register setting.
Rate of LED Blink or Pulse-Stretch This behavior controls the LED blink rate or pulse-stretch length when
blink/pulse-stretch is enabled on an LED pin. The blink rate, which alternates between a high and low voltage level at a
50% duty cycle, can be set to 2.5 Hz, 5 Hz, 10 Hz, or 20 Hz. For pulse-stretch, the rate can be set to 50 ms,
100 ms, 200 ms, or 400 ms. The blink rate selection for PHY0 globally sets the rate used for all LED pins on all PHY
ports.
LED Pulsing Enable To provide additional power savings, the LEDs (when asserted) can be pulsed at 5 kHz.

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2.4 Fast Link Failure Indication
The GbE-PHY exceeds IEEE 802.3 standards by indicating the onset of a link failure in less than 1 ms (worst case <3
ms). (IEEE 802.3 standard establishes a delay of up to 750 ms before indicating that a 1000BASE-T link is no longer
present.) A fast link failure indication is critical to support ports used in a synchronization timing link application. The
fast link failure indication works for all copper media speeds.
Caution:
For all links except 1000BASE
-T, the fast link failure indication matches the link status
register (address 1, bit 2). For 1000BASE
-T links, the link failure is based on a circuit that
analyzes the integrity of the link, and asserts at the indication of failure.

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2.5 Testing Features
The GbE-PHY includes several testing features designed to facilitate performing system-level debugging and
in-system production testing. This section describes the available features.
2.5.1 Ethernet Packet Generator
The Ethernet packet generator (EPG) can be used at each of the 10/100/1000BASE-T speed settings for copper media
to isolate problems between the MAC and the GbE-PHY, or between a locally connected PHY and its remote link partner.
Enabling the EPG feature disables all MAC interface transmit pins and selects the EPG as the source for all data
transmitted onto the twisted pair interface.
Caution:
The EPG is intended for use with laboratory or in
-system testing equipment only. Do
not use
the EPG testing feature when the GbE-PHY is connected to a live network.
To enable the EPG feature, set the device register bit 29E1.15 to 1.
When the EPG is enabled, packet loss occurs during transmission of packets from the MAC to the PHY. However, the
PHY receive output data to the MAC are still active when the EPG is enabled. When it is necessary to disable the MAC
receive data as well, set the register bit 0.10 to 1.
When the device register bit 29E1.14 is set to 1, the PHY begins transmitting Ethernet packets based on the settings in
registers 29E1 and 30E1. These registers set:
•Source and destination addresses for each packet
•Packet size
•Interpacket gap
•FCS state
•Transmit duration
•Payload pattern
When register bit 29E1.13 is set to 0, register bit 29E1.14 is cleared automatically after 30,000,000 packets are
transmitted.