Rohm Kionix KX134-1211 Product manual

A ROHM Group Company
KX134-1211
Rev. 1.0
31-Jul-2019
Kionix, Inc.
36 Thornwood Drive
Ithaca, NY 14850
USA
TEL: [phone]
http://www.kionix.com
[email protected]
TECHNICAL REFERENCE MANUAL

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 2 of 73
Overview
This technical reference manual contains information for KX134-1211. Explanation for embedded registers
and embedded applications are included. For pin assignment and specifications of the device, please also
refer to KX134-1211 Specifications.

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 3 of 73
Table of Contents
OVERVIEW ................................................................................................................................................................................. 2
TABLE OF CONTENTS.................................................................................................................................................................. 3
1EMBEDDED REGISTERS ...................................................................................................................................................... 6
1.1 REGISTER MAP...................................................................................................................................................................... 6
1.2 MAN_ID (0X00).................................................................................................................................................................. 7
1.3 PART_ID (0X01) ................................................................................................................................................................. 7
1.4 ADP OUTPUT REGISTERS (0X02 –0X07) ............................................................................................................................. 8
XADP_L ...................................................................................................................................................................................... 8
XADP_H...................................................................................................................................................................................... 8
YADP_L ...................................................................................................................................................................................... 8
YADP_H...................................................................................................................................................................................... 8
ZADP_L....................................................................................................................................................................................... 9
ZADP_H...................................................................................................................................................................................... 9
1.5 ACCELEROMETER OUTPUT REGISTERS (0X08 –0X0D) ..................................................................................................... 10
XOUT_L .................................................................................................................................................................................... 11
XOUT_H ................................................................................................................................................................................... 11
YOUT_L .................................................................................................................................................................................... 11
YOUT_H ................................................................................................................................................................................... 11
ZOUT_L .................................................................................................................................................................................... 12
ZOUT_H ................................................................................................................................................................................... 12
1.6 COTR (0X12).................................................................................................................................................................... 12
1.7 WHO_AM_I (0X13).......................................................................................................................................................... 12
1.8 TILT POSITION REGISTERS (0X14 –0X15) ......................................................................................................................... 13
TSCP......................................................................................................................................................................................... 13
TSPP ......................................................................................................................................................................................... 13
1.9 INTERRUPT SOURCE REGISTERS (0X16 –0X18) ................................................................................................................ 14
INS1 ......................................................................................................................................................................................... 14
INS2 ......................................................................................................................................................................................... 14
INS3 ......................................................................................................................................................................................... 16
1.10 STATUS_REG (0X19)........................................................................................................................................................ 17
1.11 INT_REL (0X1A) ............................................................................................................................................................... 17
1.12 CONTROL REGISTERS (0X1B –0X20) ................................................................................................................................ 18
CNTL1....................................................................................................................................................................................... 18
CNTL2....................................................................................................................................................................................... 19
CNTL3....................................................................................................................................................................................... 20
CNTL4....................................................................................................................................................................................... 22
CNTL5....................................................................................................................................................................................... 23
CNTL6....................................................................................................................................................................................... 24
1.13 ODCNTL (0X21) ............................................................................................................................................................... 25
1.14 INTERRUPT CONTROL REGISTERS (0X22 –0X27)............................................................................................................. 27
INC1 ......................................................................................................................................................................................... 27
INC2 ......................................................................................................................................................................................... 28
INC3 ......................................................................................................................................................................................... 29
INC4 ......................................................................................................................................................................................... 30
INC5 ......................................................................................................................................................................................... 31
INC6 ......................................................................................................................................................................................... 32
1.15 TILT_TIMER (0X29).......................................................................................................................................................... 33

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 4 of 73
1.16 TAP /DOUBLE-TAP CONTROL REGISTERS (0X2A –0X31) ................................................................................................. 33
TDTRC ...................................................................................................................................................................................... 33
TDTC ........................................................................................................................................................................................ 34
TTH .......................................................................................................................................................................................... 34
TTL ........................................................................................................................................................................................... 34
FTD........................................................................................................................................................................................... 35
STD........................................................................................................................................................................................... 35
TLT ........................................................................................................................................................................................... 35
TWS.......................................................................................................................................................................................... 36
1.17 FREE FALL CONTROL REGISTERS (0X32 –0X34)................................................................................................................ 36
FFTH......................................................................................................................................................................................... 36
FFC ........................................................................................................................................................................................... 36
FFCNTL..................................................................................................................................................................................... 37
1.18 TILT ANGLE CONTROL REGISTERS (0X37 –0X39)............................................................................................................. 38
TILT_ANGLE_LL ........................................................................................................................................................................ 38
TILT_ANGLE_HL ....................................................................................................................................................................... 38
HYST_SET ................................................................................................................................................................................. 38
1.19 LP_CNTL1 (0X3A)............................................................................................................................................................. 39
1.20 LP_CNTL2 (0X3B)............................................................................................................................................................. 39
1.21 WAKE-UP &BACK-TO-SLEEP THRESHOLD AND COUNTER SETUP REGISTERS (0X49 –0X4D) ........................................... 40
WUFTH, BTSWUFTH, BTSTH .................................................................................................................................................... 40
BTSC......................................................................................................................................................................................... 40
WUFC....................................................................................................................................................................................... 40
1.22 SELF_TEST (0X5D)............................................................................................................................................................ 41
1.23 OUTPUT BUFFER REGISTERS (0X5E –0X63) ..................................................................................................................... 42
BUF_CNTL1 .............................................................................................................................................................................. 42
BUF_CNTL2 .............................................................................................................................................................................. 43
BUF_STATUS_1 and BUF_STATUS_2 ....................................................................................................................................... 44
BUF_CLEAR .............................................................................................................................................................................. 44
BUF_READ ............................................................................................................................................................................... 44
1.24 ADVANCED DATA PATH CONTROL REGISTERS (0X64 –0X76) .......................................................................................... 45
ADP_CNTL1.............................................................................................................................................................................. 45
ADP_CNTL2.............................................................................................................................................................................. 46
ADP_CNTL3.............................................................................................................................................................................. 47
ADP_CNTL4, ADP_CNTL5, ADP_CNTL6 .................................................................................................................................... 47
ADP_CNTL7, ADP_CNTL8, ADP_CNTL9 .................................................................................................................................... 48
ADP_CNTL10............................................................................................................................................................................ 48
ADP_CNTL11............................................................................................................................................................................ 48
ADP_CNTL12, ADP_CNTL13..................................................................................................................................................... 49
ADP_CNTL14, ADP_CNTL15, ADP_CNTL16, ADP_CNTL17 ....................................................................................................... 49
ADP_CNTL18............................................................................................................................................................................ 49
ADP_CNTL19............................................................................................................................................................................ 49
2EMBEDDED APPLICATIONS .............................................................................................................................................. 50
2.1 ORIENTATION DETECTION FEATURE......................................................................................................................................... 50
Hysteresis................................................................................................................................................................................. 50
Device Orientation Angle (Tilt Angle) ...................................................................................................................................... 51
Tilt Timer.................................................................................................................................................................................. 51
2.2 MOTION INTERRUPT FEATURE DESCRIPTION ............................................................................................................................. 52
Enabling / Disabling................................................................................................................................................................. 52

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 5 of 73
Debounce Counter ................................................................................................................................................................... 52
Pulse Reject Mode ................................................................................................................................................................... 52
Integration with Advanced Data Path (ADP) ........................................................................................................................... 52
Threshold Resolution ............................................................................................................................................................... 53
Threshold Calculation .............................................................................................................................................................. 53
Relative / Absolute Threshold Modes Select............................................................................................................................ 53
Examples.................................................................................................................................................................................. 56
2.3 DIRECTIONAL-TAP DETECTION FEATURE DESCRIPTION ................................................................................................................ 61
Performance Index................................................................................................................................................................... 61
Single Tap Detection................................................................................................................................................................ 62
Double-Tap Detection.............................................................................................................................................................. 63
2.4 FREE FALL DETECT................................................................................................................................................................ 64
2.5 SAMPLE BUFFER FEATURE DESCRIPTION................................................................................................................................... 66
FIFO Mode ............................................................................................................................................................................... 66
Stream Mode ........................................................................................................................................................................... 66
Trigger Mode ........................................................................................................................................................................... 66
Buffer Operation...................................................................................................................................................................... 67
2.6 ADVANCED DATA PATH FEATURE............................................................................................................................................ 72
3REVISION HISTORY .......................................................................................................................................................... 73

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 6 of 73
1 Embedded Registers
1.1 Register Map
The KX134-1211 has embedded 8-bit registers that are accessible by the user. This section contains the addresses for
all embedded registers and describes bit functions of each register. Table 1 below provides a listing of the accessible
8-bit registers and their addresses.
Address
Register Name
R/W
Address
Register Name
R/W
Address
Register Name
R/W
00
MAN_ID
R
1B
CNTL11
R/W
33
FFC2
R/W
01
PART_ID
R
1C
CNTL22
R/W
34
FFCNTL1
R/W
02
XADP_L
R
1D
CNTL31
R/W
35-36
Kionix Reserved3
03
XADP_H
R
1E
CNTL41
R/W
37
TILT_ANGLE_LL2
R/W
04
YADP_L
R
1F
CNTL52
R/W
38
TILT_ANGLE_HL2
R/W
05
YADP_H
R
20
CNTL62
R/W
39
HYST_SET2
R/W
06
ZADP_L
R
21
ODCNTL1
R/W
3A
LP_CNTL11
R/W
07
ZADP_H
R
22
INC11
R/W
3B
LP_CNTL21
R/W
08
XOUT_L
R
23
INC21
R/W
3C-48
Kionix Reserved3
09
XOUT_H
R
24
INC31
R/W
49
WUFTH2
R/W
0A
YOUT_L
R
25
INC41
R/W
4A
BTSWUFTH2
R/W
0B
YOUT_H
R
26
INC51
R/W
4B
BTSTH2
R/W
0C
ZOUT_L
R
27
INC61
R/W
4C
BTSC2
R/W
0D
ZOUT_H
R
28
Kionix Reserved3
4D
WUFC2
R/W
0E-11
Kionix Reserved3
29
TILT_TIMER2
R/W
4E-5C
Kionix Reserved3
12
COTR
R
2A
TDTRC2
R/W
5D
SELF_TEST
W
13
WHO_AM_I
R
2B
TDTC2
R/W
5E
BUF_CNTL12
R/W
14
TSCP
R
2C
TTH2
R/W
5F
BUF_CNTL22
R/W
15
TSPP
R
2D
TTL2
R/W
60
BUF_STATUS_1
R
16
INS1
R
2E
FTD2
R/W
61
BUF_STATUS_2
R
17
INS2
R
2F
STD2
R/W
62
BUF_CLEAR2
W
18
INS3
R
30
TLT2
R/W
63
BUF_READ
R
19
STATUS_REG
R
31
TWS2
R/W
64-76
ADP_CNTL(1-19)2
R/W
1A
INT_REL
R
32
FFTH2
R/W
77-7F
Kionix Reserved3
Table 1: Register Map
Notes
1. When changing the contents of these registers, the PC1 bit in CNTL1 must first be set to “0”.
2. On-The-Fly (OTF) register can be written to while the KX134-1211 is enabled (PC1 bit in
CNTL1 register is 1) and the change will be accepted with no interruption in the operation.
3. Reserved registers should not be written.

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 7 of 73
1.2 MAN_ID (0x00)
A burst read (reading using the auto-increment) of 4 bytes starting at address 00, returns the manufacturing ID: "K" "i"
"o" "n" in ASCII codes "0x4B" "0x69" "0x6F" "0x6E".
R
R
R
R
R
R
R
R
MANID7
MANID6
MANID5
MANID4
MANID3
MANID2
MANID1
MANID0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x00
1.3 PART_ID (0x01)
A burst read (reading using the auto-increment) of 2 bytes starting at address 01, returns Who-Am-I value ("WAI") as
the first byte (LSB) and a 2nd byte (MSB) that returns silicon specific ID.
R
R
R
R
R
R
R
R
PARTID7
PARTID6
PARTID5
PARTID4
PARTID3
PARTID2
PARTID1
PARTID0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x01
Note: A burst read (reading using the auto-increment) of 6 bytes starting at address 00, returns the MAN_ID followed
by the 2 bytes of PART_ID

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 8 of 73
1.4 ADP OUTPUT REGISTERS (0x02 –0x07)
Output from the Advanced Data Path is routed to registers 0x02 –0x07 (XADP_L –ZADP_H) when ADPE bit is set to
1 in CNTL5 register. Data is updated at the rate set by OADP<3:0> bits in ADP_CNTL1 register. However, if data is
routed via RMS block first (ADP_RMS_OSEL bit is set to 1 in ADP_CNTL2 register), the rate is also scaled down by
RMS_AVC<2:0> bits in ADP_CNTL1 register. The output data is provided in 2’s complement data format and is
protected while reading using auto increment mode.
XADP_L
X-axis Advanced Data Path (ADP) output least significant byte.
R
R
R
R
R
R
R
R
XHP7
XHP6
XHP5
XHP4
XHP3
XHP2
XHP1
XHP0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x02
XADP_H
X-axis Advanced Data Path (ADP) output most significant byte.
R
R
R
R
R
R
R
R
XHP15
XHP14
XHP13
XHP12
XHP11
XHP10
XHP9
XHP8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x03
YADP_L
Y-axis Advanced Data Path (ADP) output least significant byte.
R
R
R
R
R
R
R
R
YHP7
YHP6
YHP5
YHP4
YHP3
YHP2
YHP1
YHP0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x04
YADP_H
Y-axis Advanced Data Path (ADP) output most significant byte.
R
R
R
R
R
R
R
R
YHP15
YHP14
YHP13
YHP12
YHP11
YHP10
YHP9
YHP8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x05

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 9 of 73
ZADP_L
Z-axis Advanced Data Path (ADP) output least significant byte.
R
R
R
R
R
R
R
R
ZHP7
ZHP6
ZHP5
ZHP4
ZHP3
ZHP2
ZHP1
ZHP0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x06
ZADP_H
Z-axis Advanced Data Path (ADP) output most significant byte.
R
R
R
R
R
R
R
R
ZHP15
ZHP14
ZHP13
ZHP12
ZHP11
ZHP10
ZHP9
ZHP8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x07

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 10 of 73
1.5 ACCELEROMETER OUTPUT REGISTERS (0x08 –0x0D)
When accelerometer is enabled (PC1 bit is set to 1 in CNTL1 register), the 16-bits of valid acceleration data for each
axis is routed to registers 0x08-0x0D (XOUT_L –ZOUT_H). However, the user may choose to read only the most
significant byte(s) of the output data thus reading an effective 8-bit resolution. The data is updated every user-defined
ODR period at the rate set by OSA<3:0> bits in ODCNTL register. It is recommended to read the output registers using
the auto-increment mode to ensure that content of the registers doesn’t change during the data read out. The output
data is available in 2’s complement data format and can be converted from digital counts to acceleration (g) per Table
2 below. For example, if N = 16 bits, then the Counts range is from -32768 to 32767, and if N = 8 bits, then the Counts
range is from -128 to 127.
16-bit
Register Data
(2’s complement)
Equivalent
Counts in
decimal
Range = ±8g
Range = ±16g
Range = ±32g
Range = ±64g
0111 1111 1111 1111
32767
+7.99976g
+15.99951g
+31.99902g
+63.99805g
0111 1111 1111 1110
32766
+7.99951g
+15.99902g
+31.99805g
+63.99609g
…
…
…
…
…
…
0000 0000 0000 0001
1
+0.00024g
+0.00049g
+0.00098g
+0.00195g
0000 0000 0000 0000
0
0.00000g
0.00000g
0.00000g
0.00000g
1111 1111 1111 1111
-1
-0.00024g
-0.00049g
-0.00098g
-0.00195g
…
…
…
…
…
…
1000 0000 0000 0001
-32767
-7.99976g
-15.99951g
-31.99902g
-63.99805g
1000 0000 0000 0000
-32768
-8.00000g
-16.00000g
-32.00000g
-64.00000g
8-bit
Register Data
(2’s complement)
Equivalent
Counts in
decimal
Range = ±8g
Range = ±16g
Range = ±32g
Range = ±64g
0111 1111
127
+7.93750g
+15.87500g
+31.75000g
+63.50000g
0111 1110
126
+7.87500g
+15.75000g
+31.50000g
+63.00000g
…
…
…
…
…
…
0000 0001
1
+0.06250g
+0.12500g
+0.25000g
+0.50000g
0000 0000
0
0.0000g
0.0000g
0.0000g
0.0000g
1111 1111
-1
-0.06250g
-0.12500g
-0.25000g
-0.50000g
…
…
…
…
…
…
1000 0001
-127
-7.93750g
-15.87500g
-31.75000g
-63.50000g
1000 0000
-128
-8.00000g
-16.00000g
-32.00000g
-64.00000g
Table 2: Acceleration (g) Calculation

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 11 of 73
XOUT_L
X-axis accelerometer output least significant byte.
R
R
R
R
R
R
R
R
XOUT7
XOUT6
XOUT5
XOUT4
XOUT3
XOUT2
XOUT1
XOUT0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x08
XOUT_H
X-axis accelerometer output most significant byte.
R
R
R
R
R
R
R
R
XOUT15
XOUT14
XOUT13
XOUT12
XOUT11
XOUT10
XOUT9
XOUT8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x09
YOUT_L
Y-axis accelerometer output least significant byte.
R
R
R
R
R
R
R
R
YOUT7
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x0A
YOUT_H
Y-axis accelerometer output most significant byte.
R
R
R
R
R
R
R
R
YOUT15
YOUT14
YOUT13
YOUT12
YOUT11
YOUT10
YOUT9
YOUT8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x0B

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 12 of 73
ZOUT_L
Z-axis accelerometer output least significant byte.
R
R
R
R
R
R
R
R
ZOUT7
ZOUT6
ZOUT5
ZOUT4
ZOUT3
ZOUT2
ZOUT1
ZOUT0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x0C
ZOUT_H
Z-axis accelerometer output most significant byte.
R
R
R
R
R
R
R
R
ZOUT15
ZOUT14
ZOUT13
ZOUT12
ZOUT11
ZOUT10
ZOUT9
ZOUT8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x0D
1.6 COTR (0X12)
The Command Test Response (COTR) register is used to verify proper integrated circuit functionality. The value of this
register will change from a default value of 0x55 to 0xAA when COTC bit in CNTL2 register is set. After reading 0xAA
from this register, the byte value returns to the default value of 0x55 and COTC bit in CNTL2 register is cleared.
R
R
R
R
R
R
R
R
DCSTR7
DCSTR6
DCSTR5
DCSTR4
DCSTR3
DCSTR2
DCSTR1
DCSTR0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
01010101
Address:
0x12
1.7 WHO_AM_I (0X13)
This register can be used for supplier recognition, as it can be factory written to a known byte value.
WHO_AM_I is the first byte (LSB) of the new PART ID. The default value is 0x46.
R
R
R
R
R
R
R
R
WAI7
WAI6
WAI5
WAI4
WAI3
WAI2
WAI1
WAI0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
01000110
Address:
0x13

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 13 of 73
1.8 TILT POSITION REGISTERS (0x14 –0x15)
These two registers report previous and current position data that is updated at the user-defined ODR frequency
determined by OTP<1:0> in CNTL3. Data is protected during register read. Table 3 describes the reported position for
each bit value.
TSCP
Current Tilt Position Register.
R
R
R
R
R
R
R
R
0
0
LE
RI
DO
UP
FD
FU
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00100000
Address:
0x14
TSPP
Previous Tilt Position Register.
R
R
R
R
R
R
R
R
0
0
LE
RI
DO
UP
FD
FU
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00100000
Address:
0x15
Bit
Description
LE
Left State (X-)
RI
Right State (X+)
DO
Down State (Y-)
UP
Up State (Y+)
FD
Face-Down State (Z-)
FU
Face-Up State (Z+)
Table 3: Tilt Position

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 14 of 73
1.9 INTERRUPT SOURCE REGISTERS (0x16 –0x18)
These three registers report interrupt state changes. The status is updated when a new interrupt event occurs, and the
bit remains set until it is cleared as indicated in each case.
INS1
This register contains TapTM/Double-TapTM axis specific interrupts. Data is updated at the ODR settings determined
by OTDT<2:0> in CNTL3. These bits are cleared when the interrupt latch release register (INT_REL) is read.
R
R
R
R
R
R
R
R
Reserved
Reserved
TLE
TRI
TDO
TUP
TFD
TFU
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x16
Bit
Description
TLE
X Negative (X-) Reported
TRI
X Positive (X+) Reported
TDO
Y Negative (Y-) Reported
TUP
Y Positive (Y+) Reported
TFD
Z Negative (Z-) Reported
TFU
Z Positive (Z+) Reported
Table 4: Directional-TapTM Reporting
INS2
This register tells which function caused an interrupt.
R
R
R
R
R
R
R
R
FFS
BFI
WMI
DRDY
TDTS1
TDTS0
Reserved
TPS
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x17
FFS –Free fall Status (FFS) bit. This bit is cleared when the interrupt latch release register
(INT_REL) is read.
FFS = 0 –No Free fall
FFS = 1 –Free fall has activated the interrupt
BFI –Buffer Full Interrupt (BFI) bit indicates that buffer has been filled. This bit is automatically
cleared when at least one sample from the buffer is read.
BFI = 0 –Buffer is not full
BFI = 1 –Buffer is full

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 15 of 73
WMI –Watermark Interrupt bit indicates that user-defined buffer’s sample threshold (watermark) has
been exceeded when in FIFO or Stream modes. Not used in Trigger mode. This bit is
automatically cleared when buffer is read, and the content is below the watermark.
WMI = 0 –Buffer watermark has not been exceeded
WMI = 1 –Buffer watermark has been exceeded
DRDY –Data Ready (DRDY) interrupt bit indicates that new acceleration data is available in output
data registers 0x08 to 0x0D. This bit is cleared when acceleration data is read or the interrupt
latch release register (INT_REL) is read.
DRDY = 0 - new acceleration data is not available
DRDY = 1 - new acceleration data is available
TDTS<1:0> –TapTM/Double-TapTM Status bits. These bits are cleared when the interrupt latch
release register (INT_REL) is read.
TDTS1
TDTS0
Event
0
0
No Tap
0
1
Single-Tap
1
0
Double-Tap
1
1
undefined
Table 5: TapTM/Double-TapTM Status Reporting Bits
TPS –Tilt Position Status bit
TPS = 0 –Position has not changed
TPS = 1 –Position has changed

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 16 of 73
INS3
This register reports the axis and direction of detected motion that triggered the wakeup interrupt.
R
R
R
R
R
R
R
R
WUFS
BTS
XNWU
XPWU
YNWU
YPWU
ZNWU
ZPWU
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x18
WUFS –Wake up interrupt. This bit is cleared when the interrupt latch release register (INT_REL) is
read.
WUFS = 1 –Motion is above wake up threshold
WUFS = 0 –Motion is below wake up threshold
BTS –Back to sleep interrupt. This bit is cleared when the interrupt latch release register (INT_REL)
is read.
BTS = 1 –Motion is below back to sleep threshold
BTS = 0 –Motion is above back to sleep threshold
XNWU / XPWU / YNWU / YPWU / ZNWU / ZPWU
Bit
Description
XNWU
X Negative (X-) Reported
XPWU
X Positive (X+) Reported
YNWU
Y Negative (Y-) Reported
YPWU
Y Positive (Y+) Reported
ZNWU
Z Negative (Z-) Reported
ZPWU
Z Positive (Z+) Reported
Table 6: Motion DetectionTM Reporting

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 17 of 73
1.10 STATUS_REG (0X19)
This register reports the status of the interrupt.
R
R
R
R
R
R
R
R
0
0
0
INT
0
0
0
WAKE
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x19
INT –reports the combined (OR) interrupt information according to interrupt setting.
0 = no interrupt event
1 = interrupt event has occurred
WAKE –reports the wake/back to sleep state
0 = back-to-sleep state
1 = wake state
Note: Wake is the default state at power-up, shown in STATUS_REG register. For wake engine only
operation, set MAN_SLEEP bit to 1 in CNTL5 register to put KX134-1211 in sleep state for the first
time.
1.11 INT_REL (0X1A)
Interrupt latch release. Latched interrupt source information (INS1-INS3) is cleared and physical interrupt latched pin
is changed to its inactive state when this register is read.
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x1A
Notes: 1. WMI and BFI are not cleared by this command.
2. The latched interrupts are not cleared when INT_REL register is read using the auto
increment read mode in SPI communication, unless it is the starting address.

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 18 of 73
1.12 CONTROL REGISTERS (0x1B –0x20)
The main control functions of the accelerometer can be set via CNTL1 –CNTL6 registers.
CNTL1
Control register 1. Read/write control register that controls the main feature set. Note that to properly change the value
of these registers, the PC1 bit in CNTL1 register must first be set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PC1
RES
DRDYE
GSEL1
GSEL0
TDTE
Reserved
TPE
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00000000
Address:
0x1B
PC1 –controls the operating mode.
PC1 = 0 –stand-by mode
PC1 = 1 –High-Performance or Low Power mode
RES –The RES bit determines the performance mode of the KX134-1211. The noise varies with ODR,
RES and different LP_CNTL1 settings possibly reducing the effective resolution.
RES = 0 –Low Power mode (higher noise, lower current, 16-bit output data)
RES = 1 –High-Performance mode (lower noise, higher current, 16-bit output data)
DRDYE –Data Ready Engine enable bit.
DRDYE = 0 –Data Ready Engine is disabled
DRDYE = 1 –Data Ready Engine is enabled
GSEL<1:0> –G-range Select (GSEL) bits select the acceleration range of the accelerometer outputs
per Table 7. This range is also called a full-scale range of the accelerometer.
GSEL1
GSEL0
Range
0
0
±8g
0
1
±16g
1
0
±32g
1
1
±64g
Table 7: Selected Acceleration Range
TDTE –Tap/Double-TapTM Engine (TDTE) enable bit.
TDTE = 0 –Tap/Double-TapTM Engine is disabled
TDTE = 1 –Tap/Double-TapTM Engine is enabled
Reserved –The value of reserved bit should not be changed
TPE –Tilt Position Engine (TPE) enable bit.
TPE = 0 –Tilt Position Engine is disabled
TPE = 1 –Tilt Position Engine is enabled

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 19 of 73
CNTL2
Control register 2. Read/write control register that primarily controls tilt position state enabling. This register has also
settings to verify proper power up. This register is On-The-Fly (OTF) register and can be written to while the KX134-
1211 is enabled (PC1 bit in CNTL1 register is set to “1”) and the change will be accepted with no interruption in the
operation. The exception is the SRST bit 7. To change the value of the SRST bit, the PC1 bit in CNTL1 register must
first be set to 0.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SRST
COTC
LEM
RIM
DOM
UPM
FDM
FUM
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
00111111
Address:
0x1C
SRST –The Software Reset bit initiates software reset, which performs the RAM reboot routine. This
bit will remain 1 until the RAM reboot routine is finished. Please refer to Technical Note TN027
Power-On Procedure for more information on software reset.
SRST = 0 –no action
SRST = 1 –start POR / RAM reboot routine
Note 1: For I2C Communication: Setting SRST = 1 will NOT result in an ACK, since the part
immediately enters the RAM reboot routine. NACK may be used to confirm this command.
Note 2: To change the value of the SRST bit, the PC1 bit in CNTL1 register must first be set
to 0.
COTC –The Command Test Control bit is used to verify proper ASIC functionality.
COTC = 0 –no action
COTC = 1 –sets COTR register to 0xAA. When COTR register is then read, sets COTC bit to
0 and sets COTR register to 0x55.
LEM, RIM, DOM, UPM, FDM, FUM –these bits control the tilt axis mask. Per Table 8, if a direction’s
bit is set to one (1), tilt in that direction will generate an interrupt. If it is set to zero (0), tilt in that
direction will not generate an interrupt.
Bit
Description
LEM
Left state enable (X-)
RIM
Right state enable (X+)
DOM
Down state enable (Y-)
UPM
Up state enable (Y+)
FDM
Face-Down state enable (Z-)
FUM
Face-Up state enable (Z+)
Table 8: Tilt DirectionTM Axis Mask

± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr. –Ithaca, NY 14850 © 2019 Kionix –All Rights Reserved
tel: [phone] – fax:[phone]-0.17
www.kionix.com - [email protected] Page 20 of 73
CNTL3
Control register 3. Read/write control register that provides control of the Output Data Rate (ODR) for Tilt, Tap, and
Wake-up engines. Note that to properly change the value of these registers, the PC1 bit in CNTL1 register must first be
set to “0”.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OTP1
OTP0
OTDT2
OTDT1
OTDT0
OWUF2
OWUF1
OWUF0
Reset Value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
10101000
Address:
0x1D
OTP<1:0> –ODR Tilt Position (OTP) sets the output data rate for the Tilt Position function per Table
9. The default Tilt Position ODR is 12.5Hz.
OTP1
OTP0
Output Data Rate (Hz)
0
0
1.563
0
1
6.25
1
0
12.5
1
1
50
Table 9: Tilt Position Function Output Data Rate
OTDT<2:0> –ODR Tap/Double-TapTM (OTDT) sets the output data rate for the Directional-TapTM
function per Table 10. The default Directional-TapTM ODR is 400Hz.
OTDT2
OTDT1
OTDT0
Output Data Rate (Hz)
0
0
0
12.5
0
0
1
25
0
1
0
50
0
1
1
100
1
0
0
200
1
0
1
400
1
1
0
800
1
1
1
1600
Table 10:Directional-TapTM Function Output Data Rate
OWUF<2:0> –ODR Wake-Up Function (OWUF) sets the output data rate (per Table 11) at which the
wake up (motion detection) performs its function. The default Motion Wake-Up ODR is
0.781Hz.
Note1: ODR Wake-Up Function setting (OWUF<2:0>) needs to be less than or equal to
accelerometer ODR setting (OSA<3:0>) to avoid irregular resulting acceleration ODRs.
Note 2: If Advanced Data Path data is routed to the Wake-Up engine (ADPE = 1,
ADP_WB_ISEL = 1), OADP<3:0> also sets the ODR for the Wake-Up engines. In this case,
the ODR set by OWUF<2:0> is ignored.