Rohm LSI Series Instruction Manual

TECHNICAL NOTE
Sound Path Selector LSI Series
Mixer & Selector
With 16bit D/A Converters
BU7858KN，BU7893GU
●OUTLINE
This LSI is mounted with stereo 16bit D/A Converter and suitable for higher sound quality and miniaturization of cellular
phone with music play. BU7893GU has a 3D surround enhancement function and hence can play the wide-spreading stereo
sound from stereo speakers that are arranged nearby.
●FEATURE
1) Mounted with Stereo 16bit audio D/A converter
2) Compatible with Stereo analogue interface
3) Stereo headphone amplifier (16Ω)
4) Low-band corrective circuit in headphone amplifier
5) Volume that can adjust the gain
6) Flexible mixing function
●APPLICATION
Portable information & communication equipments such as cellular phone and PDA (Personal Digital Assistant) etc.
Cellular phone with music play
●LINEUP
Function BU7858KN BU7893GU
Stereo audio D/A converter 16bit 16bit
Stereo audio interface format 16bit Right justified
18bit Right justified
IIS
16bit Left justified
16bit Right justified
IIS
3D surround enhancement function No Yes
3 band equalizer No Yes
Stereo headphone amplifier 16Ωdriver 16Ωdriver
Line output (600Ωdriver) Yes No
Headphone amplifier low-band
correction function
Built-in Built-in
Click noise reduction function Yes
(headphone only)
Yes
Package VQFN28 VCSP85H3
Oct. 2007

2/24
●ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Rating Unit
Power-Supply
Voltage
BU7858KN VDD -0.3 ～4.5 V
BU7893GU
DVDDIO
AVDD -0.3 ～4.5 V
DVDDCO -0.3 ～2.5
Power Dissipation BU7858KN Pd 580 *1 mW
BU7893GU 700 *2
Operating
Temperature
BU7858KN TOPR -20 ～+85 ℃
BU7893GU -30 ～+85
Storage
Temperature
BU7858KN TSTG -55 ～+125 ℃
BU7893GU -50 ～+125
*1 5.8mW is decreased every 1℃when using it over 25℃. (mounted on the ROHM standard PCB )
*2 7.0mW is decreased every 1℃when using it over 25℃.
●RECOMMENDED OPERATING CONDITION
【BU7858KN】
Parameter Symbol Min Typ Max Unit
Power-Supply Voltage VDD 2.7 3.0 3.3 V
【BU7893GU】
Parameter Symbol Min Typ Max Unit
Analog Power-Supply Voltage AVDD 2.6 2.8 3.3 V
Digital I/O Power-Supply Voltage DVDDIO DVDDCO 1.8 3.3 V
Digital Core Power-Supply Voltage DVDDCO 1.62 1.8 1.98 V
●ELECTRICAL CHARACTERISTICS
【BU7858KN】
Unless otherwise specified、Ta =25℃、AVDD=DVDD=3.0V
・Analog
Parameter Symbol Min Typ Max Unit Condition
Current Consumption Idd3 －2.3 3.7 mA 16Ωdriver part and no signal
DAC S/(N+D) SN+D －85 －dB
fs=44.1kHz, fin=1kHz, 20kHz
LPF, Vin=-0.5dBFS
DAC S/N SNR －92 －dB
fs=44.1kHz, fin=1kHz
, A-weighted, Vin=0dBFS
Headphone Amplifier Total
Harmonic Distortion THDhp －0.05 0.5 % fin=1kHz, 20kHz LPF, Vin=-10dBV
Headphone Amplifier Maximum
Output PO －10 －mW fin=1kHz, THD=10%, RL=16Ω
Headphone Amplifier Output
Noise Voltage VNO －-94 -80 dBV A-weighted
SPO Maximum Output Level VOMAX1 2.0 －－V
P-P fin=1kHz, THD≦1%, 10kΩLoad
EXTO Maximum Output Level VOMAX2 2.0 －－V
P-P fin=1kHz, THD≦1%, 600ΩLoad
・Digital (DC)
Parameter Symbol Min Typ Max Unit Condition
Digital Input Voltage “L” VIL －－0.2 x
DVDD V
Digital Input Voltage “H” VIH 0.8 x
DVDD －－V
Digital Output Voltage “L” VOL －－0.5 V Iol=-500μA
Digital Output Voltage “H” VOH DVDD
-0.5 －－V Ioh=500μA
Input Leakage Current 1 IIN1 －－±2 μA at 0V, 3V

3/24
・Audio Interface
Parameter Symbol Min Typ Max Unit Condition
MCLKI Frequency fMCLK 4.096 －18.432 MHz
MCLKI Duty Ratio dMCLK 45 －55 %
LRCLK Frequency fs 16 －48 kHz
LRCLK Duty Ratio dLR 45 －55 %
BCLK Frequency fBCK 0.512 －3.072 MHz
BCLK Duty Ratio dBCK 45 －55 %
LRCLK edge to BCLK↑Time tLRS 50 －－ns
BCLK↑to LRCLK Edge Time tSLR 50 －－ns
Data Hold Time tSDH 50 －－ns
Data Set-up Time tSDS 50 －－ns
【BU7893GU】
･Whole Block
Unless otherwise specified、Ta= 25℃、DVDD_CORE=1.8V、DVDD_IO=1.8V、AVDD=2.8V、Digital input terminal is fixed with
DVDD_IO ”L” or ”H” level、The gain settings of the audio paths are all 0dB, and no signal
Parameter Symbol Min Typ Max Unit Condition
DVDD_CORE Stand-by Current
(Core logic block) ISTCO －－10 μA standby，CLKI = DVSS
DVDD_IO Stand-by Current ISTIO －－5 μA standby，CLKI = DVSS
AVDD Stand-by Current ISTA －－5 μA standby
DVDD_CORE Operation Current IDDCO －5 10 mA
DVDD_IO Operation Current IDDIO －0.1 1 mA
BCLK，LRCLK = Input mode
MCLK = L output
AVDD Operation Current 1
(Analog melody) IDDA1 －1.6 2.8 mA
ANAINL→MIX1→SPOL
ANAINR→MIX2→SPOR
AVDD Operation Current 2
(Digital melody) IDDA2 －6.0 10.0 mA
SDI→MIX1→SPOL
SDI→MIX2→SPOR
TCXOI = 19.8MHz，fs = 44.1kHz
･DC Characteristic
Parameter Termin
-al
Symbol Min Typ Max Unit Condition
L Output Voltage Vold All output
terminal※10 －0.30 V Iol=+0.8mA
H Output Voltage Vohd All output
terminal※1
DVDD_IO
-0.30 －DVDD_IO V Ioh=-0.8mA
L Level Input Voltage1 Vild1 All input
terminal※2-0.3 －DVSS+0.5 V
L Level Input Voltage 2 Vild2 CLKI※3-0.3 －※3 V
H Level Input Voltage 1 Vihd1 All input
terminal※2
DVDD_IO
-0.5 －DVDD_IO +0.3 V
H Level Input Voltage 2 Vihd2 CLKI※3※3 －DVDD_CORE
+0.3 V
L Level Input Current Iild All input
terminal※2-1 －1 μA Input terminal voltage
is DVSS
H Level Input Current 1 Iihd1 All input
terminal※2-1 －1 μA Input terminal voltage
is DVDD_IO
H Level Input Current 2 Iihd2 CLKI※3-1 －1 μA Input terminal voltage
is DVDD_CORE
Output OFF Current Iozd Hi-Z
terminal※4-10 －10 μA
※ 1 : They also contain interactive terminals that are set output state.
※ 2 : They also contain interactive terminals that are set input state.
※ 3 : Please connect 100pF coupling capacitor and input 0.5VP-P or more when you input through coupling capacitor.
※ (In address 15h CLKSEL1=0、CLKSEL0=1)
※ 4 : At interactive terminals of input state or three-state terminals of output-disable state

4/24
・Audio Path(MIX)
Unless otherwise specified、Ta =25℃、AVDD=2.8V、reference input level=-6dBV、f=1kHz、A-weighted
、path gain =0dB
Parameter Symbol Min Typ Max Unit Condition
ANAL_V Volume Setting GDACL -11 －+3 dB
1dB step
ANAR_V Volume Setting GDACR -11 －+3 dB
1dB step
・Audio Path (SP PREamp)
Unless otherwise specified、Ta =25℃、AVDD=2.8V、reference input level =-6dBV、f=1kHz、A-weighted、path gain =0dB、
RL=33kΩ
Parameter Symbol Min Typ Max Unit Condition
THD+N THDSP －-70 -60 dB
20kHz LPF
Output Noise Voltage VNOSP －-90 -80 dBV At no a signal
Mute Level MLSP －-90 -80 dB 1kHz BPF
・Audio Path (HP amp)
Unless otherwise specified、Ta =25℃、AVDD=2.8V、reference input level =-6dBV、f=1kHz、A-weighted、path gain =0dB、
RL=16Ω
Parameter Symbol Min Typ Max Unit Condition
THD+N THDHP －-65 -55 dB
20kHz LPF
Output Noise Voltage VNOHP －-90 -80 dBV At no signal
The Maximum Output Power POHP 10 －－mW THD=10%，16Ωload
Channel Separation CSHP －-80 -70 dB Vo=-14dBV，1kHz BPF
Mute Level MLHP －-90 -80 dB 1kHz BPF
HPL_V Volume Setting 1 GA1HPL -48 －0 dB 2dB step
HPL_V Volume Setting 2 GA2HPL -42 －+6 dB 2dB step
HPR_V Volume Setting 1 GA1HPR -48 －0 dB 2dB step
HPR_V Volume Setting 2 GA2HPR -42 －+6 dB 2dB step
・3D Surround, Equalizer, and Audio DAC
Unless otherwise specified、Ta =25℃、AVDD=2.8V、BCLK=64fs、LRCLK=256fs、f=1kHz、
path gain=0dB、SPOL/SPOR output、SPOL/SPOR= no load、output=0dBFS
Parameter Symbol Min Typ Max Unit Condition
Full-scale Amplitude VMAX 1.40 1.68 2.00 VP-P 0.6×AVDD
S/N1 (A-Weighted) DACsn1 70 75 －dB
THD+N1 (20kHz LPF) DACthd1 －-70 -60 dB fs=8，11.025kHz
THD+N2 (20kHz LPF) DACthd2 －-75 -65 dB fs=16，22.05，32，44.1，48kHz
・Audio I/F Format
Unless otherwise specified、Ta =25℃、DVDD_IO=1.62～3.3V、DVDD_CORE=1.62～1.98V
Parameter Symbol Min Typ Max Unit Condition
BCLK Output Frequency FBCKO 0.512 －3.072 MHz
64fs
LRCLK Output Frequency FLRCKO 8 －48 kHz
SDI Set-up Time tSDSU 100 －－nsec
SDI Hold Time tSDH 100 －－nsec
・PLL
Unless otherwise specified、Ta =25℃、AVDD=2.8V、BCLK = no load
Parameter Symbol Min Typ Max Unit Condition
PLL Lock-up Time Tlock1 －－10 msec
PLL Jitter Tjitter1 －200 －psec BCLK terminal，fVCO=65.536MHz

5/24
● REFERENCE DATA
【BU7858KN】
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1000 10000 100000
INPUT SIGNAL FREQ : FIN(Hz)
THD+N (dB)
0.0
2.0
4.0
6.0
8.0
10.0
2.0 2.5 3.0 3.5 4.0 4.5
SUPLLY VOLTAGE : VDD(V)
STAND-BY CURRENT : ICC (μA)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
14.0
2.0 2.5 3.0 3.5 4.0 4.5
SUPLLY VOLTAGE : VDD(V)
OPERATION CURRENT : ICC (mA)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
2.0 2.5 3.0 3.5 4.0 4.5
SUPLLY VOLTAGE : VDD(V)
OPERATION CURRENT : ICC (mA)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-110 -90 -70 -50 -30 -10
INPUT LEVEL : VIN(dBFS)
THD+N (dB)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-110 -90 -70 -50 -30 -10
INPUT LEVEL : VIN(dBFS)
THD+N (dB)
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
10 100 1000 10000 100000
INPUT SIGNAL FREQ : FIN(Hz)
THD+N (dB)
0.01
0.10
1.00
10.00
100.00
-100 -80 -60 -40 -20 0
INPUT LEVEL : VIN(dBV)
THD+N (%)
0.01
0.10
1.00
10.00
100.00
-100 -80 -60 -40 -20 0
INPUT LEVEL : VIN(dBV)
THD+N (%)
0.01
0.10
1.00
10.00
100.00
-100 -80 -60 -40 -20 0
INPUT LEVEL : VIN(dBV)
THD+N (%)
0.01
0.10
1.00
10.00
100.00
-100 -80 -60 -40 -20 0
INPUT LEVEL : VIN(dBV)
THD+N (%)
Fig.2 16bit D/A Converter
Operation Current
Fig.1 Stand-by Current
Fig.3 Headphone Amplifier
Operation Current
Fig.5 16bit D/A Converter Total
Harmonic Distortion (Rch)
Fig.4 16bit D/A Converter Total
Harmonic Distortion (Lch)
Fig.9 Headphone Amplifier Total
Harmonic Distortion (HP_R)
Fig.8 Headphone Amplifier Total
Harmonic Distortion
(
HP
_
L
)
Fig.7 16bit D/A Converter Total
Harmonic Distortion (Rch)
Fig.11 EXTO
Total Harmonic Distortion
Fig.10 SPO
Total Harmonic Distortion
Fig.6 16bit D/A Converter Total
Harmonic Distortion (Lch)

6/24
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2.6 2.8 3.0 3.2 3.4
SUPLLY VOLTAGE : AVDD(V)
STAND-BY CURRENT : ICC (μA)
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.6 2.8 3.0 3.2 3.4
SUPLLY VOLTAGE : AVDD(V)
OPERATION CURRENT : ICC (mA)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
-100 -80 -60 -40 -20 0
INPUT LEVEL (dBFS)
THD+N (dB)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10 100 1000 10000 100000
INPUT SIGNAL FREQUENCY (Hz)
THD+N (dB)
【BU7893GU】
Fig.12 DVDD_CORE
Standby Current
Fig.13 AVDD Standby
Current
Fig.14 DVDD_CORE
Operation Current
(Analog melody)
Fig.15 AVDD Operation
Current (Analog melody)
Fig.16 DVDD_CORE
Operation Current (digital
melody)
Fig.17 AVDD Operation
Current (digital melody)
Fig.18 16bit D/A Converter Total
Harmonic Distortion 1kHz (SPOL)
Fig.19 16bit D/A Converter Total
Harmonic Distortion 1kHz (SPOR)
Fig.20 16bit D/A Converter Total
Harmonic Distortion (SPOL)
Fig.21 16bit D/A Converter Total
Harmonic Distortion (SPOR)
Fig.22 Headphone Amplifier To ta l
Harmonic Distortion (HPOL / HPOR)
Fig.23 Speaker Preamp
Total Harmonic Distortion
(
SPOL / SPOR
)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.6 1.7 1.8 1.9 2.0
SUPLLY VOLTAGE : DVDD_CORE(V)
OPERATION CURRENT : ICC (μA)
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.6 1.7 1.8 1.9 2.0
SUPLLY VOLTAGE : DVDD_CORE(V)
STAND-BY CURRENT: ICC (μA)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
1.6 1.7 1.8 1.9 2.0
SUPLLY VOLTAGE : DVDD_CORE(V)
OPERATION CURRENT : ICC (mA)
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
2.6 2.8 3.0 3.2 3.4
SUPLLY VOLTAGE : AVDD(V)
OPERATION CURRENT : ICC (mA)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
-100 -80 -60 -40 -20 0
INPUT LEVEL (dBFS)
THD+N (dB)
-90.0
-80.0
-70.0
-60.0
-50.0
-40.0
-30.0
-20.0
-10.0
0.0
10 100 1000 10000 100000
INPUT SIGNAL FREQUENCY (Hz)
THD+N (dB)
0.0
0.1
1.0
10.0
100.0
-100 -80 -60 -40 -20 0
INPUT LEVEL (dBV)
THD+N (%)
0.01
0.10
1.00
10.00
100.00
-100 -80 -60 -40 -20 0
INPUT LEVEL (dBV)
THD+N (%)

7/24
●BLOCK CHART
【BU7858KN】
Fig.24 BU7858KN Block Diagram
Fig.25 BU7858KN Pin Assignment (TOP VIEW)
16bit
DAC
16bit
DAC
Dig ital
Audio
I/F
Dig it
-al
ATT
BIAS
RING
BC L K
LRCLK
SDTI
CVCOM NRST SCLK SDATA SCS
SPO
AVSSAVD DDVSSDVDD
MEL_R
CSTEP
LPF
LPF
RXI
HP_L
HP_R
ATT2
MIX-
SEL1
EXTO
MIX-
SEL2
MIX-
SEL3
MIX-
SEL4
MEL_L
EXTI
600Ω
16Ω
16Ω
ATT1
+
MCLKI
ATT3
SW1
SW2
Serial Control
CA_L
CA_R
CSTART
ATT5
MCLKO
PLLC
PLL
+
-
+
-
ATT4
+
-
+
-
ATT
ATT
BC L K
SP Amp
SPO
EXTO
CA_R
CSTART
EXTI
AVDD
CVCOM
HP_R
CSTEP
BU7858KN
AVSS
14
13
12
11
10
21 20 19 18 17 16 15
HP_L
CA_L
8
9NRST
NCS
MEL_L
RXI
RING
MEL_R
PLLC
22
23
24
25
26
28
27
MCLKO
MCLKI
1 2 45 673
LRCLK
BCLK
SDTI
DVDD
DVSS
SCLK
SDATA

8/24
【BU7893GU】
Fig.26 BU7893GU Block Diagram
( TOP VIEW )
Fig.27 BU7893GU Ball Assignment
CPOP
PLL
SPI VREF
VOL
VOL
DAI
DAC
ANAINL
ANAINR
CLKI
PLLC
MCLK
LRCLK
BCLK
SDI
CSTEP SCLK
RSTB DVSS AVSS AVDD
CCL
HPOL
DAC
Sonaptic
3D
VOL
RX
EXT
RX
CSB
Equalizer
Stereo PCM Interface
(MP3,AAC,etc)
Stereo Analog
Interface
(From Melody LSI)
Serial I/F
19.2MHz/
19.68MHz/
19.8MHz
6800p
+
8Ω
16Ω
1μF
0.1μF
SPOL
SP Amp 8Ω
HPOR
CCR
RX
EXT
DACR
VOL
6800p
+
16Ω
SPOR
DACR
DACR
EXT
RX
EXT
SIO
SO COMOUT COMIN
SP Amp
DACL
DACL
DACL
DACL
DACR
+
-6dB
-6dB
+
-6dB
-6dB
DVDD_CORE
DVDD_IO
1μF 1μF
CPOP
100μ
100μ
123456
ATEST3 HPOR HPOL CPOP SPOL TEST4
BCCR RSTB DVSS CCL SPOR COMIN
CSCLK SO CSTEP AVSS
DSIO MCLK COMOUT ANAINR
ECSB PLLC AVDD DVDD_CORE SDI ANAINL
FTEST2 CLKI DVDD_IO BCLK LRCLK TEST1

9/24
●DIGITAL INTERFACE OF 16BIT AUDIO D/A CONVERTER
16bit audio D/A converter equipped with this series can be used with the following audio format.
【BU7858KN】
1) MSB first 16bit data (Right justified)
2) MSB first 18bit data (Right justified)
3) IIS mode 18bit data (Left justified)
4) IIS mode 16bit data (BCLK=32fs)
Fig.28 AUDIO I/F FORMAT (BU7858KN)
BU7858KN is provided with a mode that generates MCLK (Master Clock) by using the built-in PLL, so it is possible to
make a D/A converter operate even if the clocks are only BCLK (64fs/32fs), LRCLK (fs).
The PLL generates MCLK (Master Clock), which is necessary for driving of D/A converter, from BCLK (Bit Clock).
Please connect a capacitor (PLLC) for the filter with DVSS. Moreover, please place the capacitor nearest DVSS of IC in
order to reduce the noise interference.
Then it is possible to monitor the master clock that is generated internally from MCLKO, which is after all the monitor
terminal, and hence does not guarantee drivability and phase-margin.
Please tie the MCLKI terminal to DVSS when PLL is used. And please tie the PLLC terminal to DVSS when PLL is not
used. Moreover, it is not necessary to set the ”PLLPDN” and “SMPR” when PLL is not used.
012
3
4 4 3 2 1 0
Lch Rch
BCLK(64fs)
SDTI
LRCK(fs)
17:MSB, 0:LSB
17 16Don’t Don’t Care 17 16 17 16
Don’t Care
0
1
2
3
6
789
10
01
2
Lch
Rch
BCLK(32fs)
SDTI
LRCLK(fs)
15:MSB
,
0:LSB
15 14 13 12 11 0
1
23
6
78
910
15 14 13 12 11 15 14 13
0123
4
111415
16
17
012 17 16 15 14 11
4
3 2 01Don’t Care Don’t Care
Lch Rch
BCLK(64fs）
SDTI
LRCLK(fs)
17:MSB
,
0:LSB
0123
4
111213
14
15
012 15 14 13 12 11
4
3 2 01Don’t Care Don’t Care
Lch Rch
BCLK(64fs）
SDTI
LRCLK(fs)
15:MSB
,
0:LSB

10/24
【BU7893GU】
Fig.29 AUDIO I/F Format (BU7893GU)
●3D SURROUND ENHANCEMENT FUNCTION
【BU7893GU】
Even under the circumstances of adjacent arrangement of stereo speakers, the wide-spreading acoustic effect can be
achieved because of the output resulting from the digital audio input to which the 3D surround effect has been applied.
Moreover, the stereo sound at the time of audio recording can also be played truly. Please tell us about the parameter
setting when you use this function.
●LOW-BAND CORRECTIVE CIRCUIT
In the headphone output terminals (HP_L, HP_R or HPOL, HPOR), there is a low-band corrective circuit, which corrects
the low-band attenuation.
Fig.30 BU7858KN & BU7893GU Headphone Output Equivalent Circuit
Low-band cut-off frequency fC= 1/(2･π･CL･RL)
Low-band boost frequency fBOOST = 1/(2･π･CCHPx･200kΩ)
Boost gain ABOOST = 20･log((200 kΩ+1/(2･π･f･CCHPx))/100 kΩ)
（the maximum low-band boost is 6dB）
For parameter setting, determine the output coupling capacitance CL and the headphone impedance RLbefore calculating
the low-band cut-off frequency fC. Then determine CCHPx so that the low-band cut-off frequency fC is roughly in agreement
with the low-band boost frequency fBOOST.
The recommended parameter setting of BU7858KN and BU7893GU is CCHPx = 6800pF at the time of CL = 100μF and RL
= 16Ω.
+
-
200kΩ
200kΩ
+
HP_X
or
HPOX
CA_X
or
CCX
CCHPx
CL
RL
OUTPUT
100kΩ
0 1 2 3 13 14 15 16 17 18 29 30 31 123 13
14 15 16 17 18 29 30 31
00
RchLch
BCLK
LRCLK
1. MSBファースト前詰フォーマット
Don't
care
15 14 13 210 15 14 13 2 1 0
Don't
care
Don't
care
Don't
care 15
SDI
3. IISフォーマット
Don't
care
Don't
care
Don't
care
Don't
care
SDI
2. MSBファースト後詰フォーマット
0 1 2 3 4 141516171819 30 31 1 2 3 141516171819 30310 0
RchLch
BCLK
LRCLK
Don't
care
15 14 13 2 1 0 Don't
care
Don't
care
Don't
care 15 14 13 2 1 0 Don't
care
SDI
4
15 14 13 2 1 0 2 1 015 14 13
MSB first right justified format
IIS format
MSB first left justified format

11/24
The frequency characteristic (theorical value) when the recommended constants are used is shown below.
Fig.31 Low-band corrective circuit Frequency characteristic
●CPU INTERFACE
BU7858KN and BU7893GU can be controlled by using CPU interface.
【BU7858KN】
Fig.32 CPU I/F Timing Chart 1 (BU7858KN)
After the falling edge of NCS, SDATA inputs are settled by 16 clock of SCLK, and data is written in the rising edge of NCS.
The data format is “16bit right justified”.
CPU interface is that 1Byte=16bit. It is absolutely necessary to insert the interval of NCS=“H” between first Byte and
Second Byte because it is not compatible with continuous data transmission. For the following th, please wait the time more
than 1 SCLK Clock. (th≧tcyc)
Fig.33 CPU I/F Timing Chart 2 (BU7858KN)
・AC Characteristics
Ta=25℃、AVDD=DVDD=3.0V
Item Symbol Min Typ Max Unit Conditions
SCLK Width tcyc 250 - - ns
SDATA Input Hold Time tdh 50 - - ns
SDATA Input Set-up Time tds 50 - - ns
NCS Set-up Time tcs 50 - - ns
NCS Hold Time tch 50 - - ns
It is recommended to use exclusive lines for CPU interface.
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
1 10 100 1000 10000 100000
Frequency [Hz]
Gain [d B ]
A
fter correction
Before correction
A
mplifier output
A7
SCLK
SDATA
tcs
NCS
tds tdh
A6 D6 D5 D4 D3 D2 D1 D0
A5 A4 A3 A2 D7
A1
tch
tcyc
A0
NCS
SCLK
S
DATA
th

12/24
【BU7893GU】
・Timing Chart
A
D[6]
A
D[5]
A
D[0] Direction DT[7] DT[6] DT[0]DT[1]
SCLK
SIO
SEL
A
D[4]
Tscss
Ts c Thc
When direction is "1": Write operation
When direction is "0": Read operation
・Write Operation
SEL
A
D[6]
A
D[5] DT[7] DT[6] DT[0]
DT[1]
SCLK
SIO
A
D[4]
A
D[0]
Direction”H”
・Read Operation (mode 1): SO_ENABLE (bit0 at register address 14h)=0
SCLK
DT[7] DT[6] DT[1]
SIO Hi-Z
A
D[6]
A
D[5]
A
D[4]
A
D[0]
SEL
Direction”L”
DT[0]
Output data
Ts d
・Read Operation (mode 2): SO_ENABLE (bit0 at register address 14h)=1
SIO
SCLK
SEL
DT[7] DT[6] DT[0]DT[1]
SO
Output data
A
D[6]
A
D[5] AD[4] AD[0]
Direction”L”
DT[5]
Hi-Z Hi-Z
Ts d
Fig.34 CPU I/F Timing Chart (BU7893GU)
DVDD_IO=1.62～3.3V、Ta=- 30～+85℃
Item Symbol Min Typ Max Unit Conditions
Bit Length Ncha 16 －－bit MSB first
SCLK Input Frequency FSCLK －－15 MHz
SCLK ‘L’ Pulse Width Tlsclk 25 －－ns
SCLK ‘H’ Pulse Width Thsclk 25 －－ns
SCLK-SEL Set-up Time Tscss 10 －－ns
Data Set-up Time Tsc 10 －－ns
Data Hold Time Thc 10 －－ns
Delay Time of Data Output Tsd －－30 ns
SIO: Time from SCLK falling edge
SO : Time from SCLK rising edge
It is recommended to use exclusive lines for CPU interface.

13/24
●I2C INTERFACE
【BU7893GU】
In the BU7893GU, the LSI can be controlled by using I2C interface.
The device’s address (slave address) is "1100011(63h)". It is based on the Philips I2C-BUS V2.1’s fast-mode, the
maximum transfer rate of a bit is 400kbps.
A7 A6 A5 A4 A3 A2 A1 W/R
1 1 0 0 0 1 1 0/1
I2C Slave addresses
・Bit Transfer
A data is transferred during the HIGH period of the clock . The data on the SIO line must be stable during this period. The
HIGH or LOW state of the data line can only change when the clock signal on the SCLK line is LOW. When SCL is H and
SDA changes, the START conditions or the STOP condition is generated, and it is interpreted as the control signal.
・START & STOP Conditions
When SIO and SCLK are “H”, there is no data transfer performed on the I2C bus. A HIGH to LOW transition on the SIO line
while SCLK is HIGH is one such unique case. This situation indicates a START condition (S).
A LOW to HIGH transition on the SIO line while SCLK is HIGH defines a STOP condition (P).
The consecutive START and STOP conditions are acceptable.
・Acknowledge
After START condition, 8 bits of data is transferred at a time. The transmitter releases the SIO line, and the receiver
returns the Acknowledge signal by assuming SIO to be “L”.
SIO
SCLK
SIO is stable.
Valid Data
SIO is possible
to change
SIO
SCL S P
START conditions STOP conditions
SCLK 12 89
SIO output
by the transmitter
Acknowledge
Non-Acknowledge
S
START condition
Clock pulse
for Acknowledge
SIO output
by the receiver

14/24
・Writing Protocol
The write protocol is shown below. The register address is transferred in a byte after the slave address and write
command are transferred. The third byte writes the data into the internal register that is indicated by the second byte. After
that, the register address is incremented on automatically (when the register address is between 00h and 16h). However,
when the register address reaches 16h, the register address does not change with the next byte transfer, rather, it accesses
the same register address (16h). The register address is incremented after transfer completion.
・Reading Protocol
It reads from the next byte after writing the slave address and R/W bit. The read register is the following address
accessed at the end. After that, the data of the address incremented is read out. The register addresses are incremented
after transfer completion.
・Combined Reading Protocol
After specifying an internal address, it reads by generating resending start conditions and changing the direction of data
transfer. Afterwards, data from incremented addresses is read. The register addresses are incremented after transfer
completion. Compound writing is possible by writing R/W=0 after resending start condition.
S A A A
P
from master to slave
from slave to master
A=Acknowledge
A=Non-acknowledge
S=START condition
P=STOP condition
Sr=Repeated START condition
R/W=0 ( Write)
Sr 1
R/W=1 ( Read)
A
Slave address
1010 01 0 1
Register address
A7 A6 A5 A4 A3 A2 A1 A0
Slave address
1010 011
Data Data
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 A
Register address
Increment
Register address
Increment
S A A A P
DataRegister addressSlave address
from master to slave
R/W=0(Write)
Data
AD7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0A7 A6 A5 A4 A3 A2 A1 A01010 01 01
Register address
Increment
Register address
Increment
A=Acknowledge
A=Non-Acknowledge
S=START condition
P=STOP condition
from slave to master
1S A P
R/W=1(Read)
Data
A A
Slave address
101 0 0 1 1 D7D6D5D4D3D2D1D0 D7D6D5D4D3D2D1D0
Register address
Increment
Data
Register address
Increment
from master to slave A=Acknowledge
A=Non-Acnkowledge
S=START condition
P=STOP condition
from slave to master

15/24
・Timing Diagram
Fig.35 I2C Timing Diagram
DVDD_IO=1.62～3.3V、Ta=- 30～+85℃
Item Symbol Min Typ Max Unit Conditions
Hold Time at Start Condition tHD;STA 0.6 －－μsec
SCLK “H” Level Time tHIGH 0.6 －－μsec
SCLK “L” Level Time tLOW 1.3 －－μsec
Set-up Time for Repeated Start Condition tSU;STA 0.6 －－μsec
Data Hold Time tHD;DAT 0 －0.9 μsec
Data Set-up Time tSU;DAT 100 －－nsec
Set-up Time for Stop Condition tSU;STO 0.6 －－μsec
Bus Release Time between Stop
Condition and Start Condition tBUF 1.3 －－μsec
● PIN FUNCTION
【BU7858KN】
No. Pin Name I/O Pin Function Power
Equivalent
Circuit
Diagram
1 SDTI I Audio DAC Serial Data Input DVDD A
2 LRCLK I Audio DAC LR Clock DVDD A
3 BCLK I Audio DAC BIT Clock DVDD A
4 DVDD - Digital Power Supply －－
5 DVSS - Digital Ground DVDD －
6 SCLK I Serial Clock for CPU Interface DVDD A
7 SDATA I Serial Data for CPU Interface DVDD A
8 NCS I Serial Chip Selection for CPU Interface DVDD A
9 NRST I Reset Input L: Reset DVDD A
10 CSTEP - Capacitor Connection Terminal for Pop Noise Reduction AVDD C
11 CSTART -
Capacitor Connection Terminal for Pop Noise Reduction
at Start-up
AVDD G
12 CVCOM -
Capacitor Connection Terminal for Internal Reference
Voltage Output
AVDD G
13 HP_R O Headphone Amplifier Output R-ch AVDD H
14 CA_R -
Low-band Correction Capacitor for Headphone Amplifier
R-ch
AVDD C
SCL
SIO
tSU;STA
tBUF tHD;STA
tLOW tHIGH 1/fSCLK
tSU;DAT tHD;DAT tSU;STO
（Repeated）
START
conditions
BIT 7 BIT 6 Acknowledge STOP
condition

16/24
No. Pin Name I/O Pin function Power
Equivalent
Circuit
Diagram
15 CA_L -
Low-band Correction Capacitor for Headphone Amplifier
L-ch
AVDD C
16 HP_L O Headphone Amplifier Output L-ch AVDD H
17 AVSS - Analog Ground －－
18 AVDD - Analog Power Supply －－
19 EXTO O 600ΩDriver Output AVDD H
20 SPO O Line Output for Speaker AVDD H
21 EXTI I External Input AVDD D
22 MEL_L I Melody Input L ch AVDD D
23 MEL_R I Melody Input R ch AVDD D
24 RING I RING Input AVDD E
25 RXI I RXI Input AVDD D
26 PLLC - Capacitor Connection Terminal for PLL Loop Filter DVDD C
27 MCLKO O Master Clock Output DVDD B
28 MCLKI I Master Clock Input DVDD A
Fig.36 Equivalent Circuit Diagrams (BU7858KN)
C
E
BA
FD
GH
100kΩ
(TYP)
200kΩ
(TYP)
PAD PAD PAD
PADPAD
PAD
PAD PAD

17/24
【BU7893GU】
No. Matrix Pin Name I/O Pin Function
Terminal
Conditions Power
Equivalent
Circuit
Diagram
No. at Reset
1 E3 AVDD - Analog Power Supply －AVDD －
2 C6 AVSS - Analog Ground －AVDD －
3 E6 ANAINL I DAC L-ch Input －AVDD G
4 D6 ANAINR I DAC R-ch Input －AVDD G
5 A3 HPOL O Headphone Amplifier Output L-ch Pull-down AVDD H
6 A2 HPOR O Headphone Amplifier Output R-ch Pull-down AVDD H
7 B4 CCL I
Low-band Correction Capacitor for Headphone
Amplifier L-ch Pull-down AVDD I
8 B1 CCR I
Low-band Correction Capacitor for Headphone
Amplifier R-ch Pull-down AVDD I
9 A5 SPOL O L-ch Line Output for Speaker Pull-down AVDD H
10 B5 SPOR O R-ch Line Output for Speaker Pull-down AVDD H
11 D5 COMOUT O Analog Reference Voltage Output Hi-Z AVDD J
12 B6 COMIN I Analog Reference Voltage Input Hi-Z AVDD K
13 A4 CPOP I/O Capacitor Connection Terminal for Pop Noise
Reduction Hi-Z AVDD L
14 C5 CSTEP I/O Capacitor Connection Terminal for Noise
Reduction during Volume Change Hi-Z AVDD L
15 E2 PLLC I/O Capacitor Connection Terminal for PLL Loop Filter －AVDD L
16 E4 DVDD_CORE - Digital Core Power Supply －DVDD_CORE －
17 F3 DVDD_IO - Digital IO Power Supply －DVDD_IO －
18 B3 DVSS - Digital Ground －DVDD_IO,
DVDD_CORE －
19 F2 CLKI I
PLL Reference Clock Input
(19.2/19.68/19.8 MHz) －DVDD_IO D
20 B2 RSTB I Reset Input L: Reset －DVDD_IO A
21 E1 CSB I
CPU Interface Select Pin
(L ：CPU I/F DVDD_IO ：I
2C I/F) －DVDD_IO B
22 C1 SCLK I CPU Interface Clock －DVDD_IO A
23 D1 SIO I/O CPU Interface Data Input/Output
(at Reset Input) Hi-Z DVDD_IO F
24 C2 SO I/O CPU Interface Data Output
(connected to DVSS when not in use) Hi-Z DVDD_IO E
25 E5 SDI I Audio DAC Digital Data Input Hi-Z DVDD_IO C
26 F4 BCLK I/O Audio DAC Bit Clock (Input State at Reset) Hi-Z DVDD_IO E
27 F5 LRCLK I/O Audio DAC LR Clock (Input State at Reset) Hi-Z DVDD_IO E
28 D2 MCLK I/O Audio DAC Master Clock (Input State at reset ) Hi-Z DVDD_IO E
29 F6 TEST1 I
Test Pin (connected to DVSS during normal
operation) Pull-down DVDD_IO C
30 F1 TEST2 I
Test Pin (connected to DVSS during normal
operation) Pull-down DVDD_IO C
31 A1 TEST3 I/O Test Pin (released during normal operation) －DVDD_IO E
32 A6 TEST4 I Test Pin (released during normal operation) －AVDD －

18/24
PAD
A
IN
Schmitt Trigger
PAD
B
IN
PAD
IN
C
PAD
D
IN
PAD
INOUT
E
PAD
INOUT
F
Schmitt Trigger
PAD
IN
G
-
+PAD
OUT
H
PAD
IN
I
PAD
OUT
-
+
J
PAD
IN/OUT
K
PAD
L
IN/OUT
Fig.37 Equivalent Circuit Diagrams (BU7893GU)

19/24
●RECOMMENDED SEQUENCE
【BU7858KN】
Fig.38 BU7858KN Recommended Sequence Flow Chart
Power Supply ON
Reference Voltage ON
(VCOM=1)
Input Path Setting
Mixing Path Setting
Analog Power ON
(PDN=1)
PLL Setting
(PLLPDN=1)
(Using PLL)
DAC Setting
(Using DAC)
DAC MUTE OFF
(Using DAC)
HPAMP RESET Lifting
(Using HPAMP)
Power Supply OFF
RESET
NRST=0 or
PLLPDN=0, VCOM=0
HPAMP RESET
(HPRST=0)
Analog Power OFF
(PDN=0)
PLL OFF
(PLLPDN=0)
(Using PLL)
DAC MUTE ON
(Using DAC)
HPAMP MUTE ON
(Using HPAMP)
Stand-by mode
Play
*1
*2
*1 : When the analog path setting is not changed (Repeated play)
*2 : When the power supply OFF, after playing
*1
Mode Setting Flow

20/24
【BU7893GU】
SAMPLE# AUDIO PATH+ AUDIO DAC BLOCK SETTING SEQUENCE
After powering up and canceling reset, set paths according to the sequence shown as below:
(1) Start up reference voltage
Start up the reference voltage in the REF_PWR register (00h).
To start up the VREF block fast, set the REF_ON bit (bit-0) and BST_ON bit (bit-1) to "1" simultaneously. After starting
up the reference voltage startup, set just the BST_ON bit (bit-1) to "0".
(2) Start up Audio DAC
When using Audio DAC
(2-1) Enable PLL block clock input and start up PLL
Start up the power supply of the PLL and enable clock input to the PLL in the PLL_PWR
register (16h).
Set REF1_ON (bit-1) and PLL_ON (bit-0) to "1" simultaneously.
(2-2) Caution concerning interim between starting up PLL block and starting up Audio DAC block
After starting up the power supply of the PLL in the PLL_PWR register (16h), wait 10 msec before starting up the
Audio DAC.
(2-3) Start up Audio DAC block
Start up the power supply of the Audio DAC in the DAC SET4 register (13h).
Set DAC_ON (bit-5) and DAC_RSTB (Bit-4) to "1".
(2-4) Set 3D surround and Equalyzer parameter
Please tell us about the parameter setting when you use this function.
(3) Start up analog input amplifier to use
Start up the power supply of the input amplifier and input volume in the IAMP_PWR register (01h).
(4) Set input volume
Set the input volume in the IVR_1 register (09h).
(5) Set mixing path
Make mixing path settings in the MIX1 register (02h), MIX2 register (03h), MIX3 register (04h), and MIX4 register (05h).
(6) Set startup noise reduction sequence
Set the sequence time in the POP_TM register (07h).
(7) Set click noise reduction sequence
Set the sequence time in the OVR_TM register (0Ah).
(8) Set output path
Enable the relevant output path in the PATH_CNT register (06h).
(9) Set output volume
Set output volume values =0x18(-48dB) in the OVR_1 register (0Bh).
(10) Ramp up output driver amplifier
Ramp up the output driver amplifier in the DRV_PWR register (08h).
(11) Caution concerning interim between ramping up output driver amplifier and canceling mute
After setting the DRV_PWR register (08h), wait the sequence time set in the POP_TM register (07h) before canceling
mute.
(12) Cancel mute
Cancel mute state of the output driver amplifier in the DRV_MT register (0Ch).
(13) Caution concerning interim between canceling mute and setting output volume
After setting the DRV_MT register (0Ch), wait the sequence time that is set in the OVR_TM register (0Ah) before
subsequently setting output volume.
(14) Set output volume
Set output volume values in the OVR_1 register (0Bh).